JP2007258739A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve soft error resistance by increasing the accumulative node capacity of a SRAM memory cell. <P>SOLUTION: A full CMOS-type SRAM where 6 pcs of MISFET constitute a memory cell, wherein a pair of local wirings L<SB>1</SB>, L<SB>2</SB>that mutually connects input/output terminals of a CMOS inverter are formed, in a high melting point-metal silicide layer formed on the upper layer of a first conductive layer constituting each gate electrode of a MISFETs for driving the memory cell Qd<SB>1</SB>, Qd<SB>2</SB>, a MISFETs for transferring the memory cell Qt<SB>1</SB>, Qt<SB>2</SB>and a MISFETs for loading the memory cell Qp<SB>1</SB>, Qp<SB>2</SB>. An accumulative node capacitive element is formed by disposing reference voltage lines formed in an upper layer of the local wirings L<SB>1</SB>, L<SB>2</SB>so as to be overlapped on the local wirings L<SB>1</SB>, L<SB>2</SB>. One of the local wirings L<SB>1</SB>, L<SB>2</SB>constitutes one electrode of the accumulative node capacitative element. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique that is effective when applied to a semiconductor integrated circuit device having an SRAM (Static Random Access Memory).

  An SRAM as a semiconductor memory device includes a memory cell composed of a flip-flop circuit and two transfer MISFETs (Metal Insulator Semiconductor Field Effect Transistors) at an intersection between a word line and a pair of complementary data lines. ing.

  The flip-flop circuit of the SRAM memory cell is configured as an information storage unit and stores 1-bit information. As an example, the flip-flop circuit of the memory cell includes a pair of CMOS (Complementary Metal Oxide Semiconductor) inverters. Each of the CMOS inverters includes an n-channel type driving MISFET and a p-channel type load MISFET. The transfer MISFET is an n-channel type. That is, this memory cell is configured as a so-called full CMOS (Full Complementary Metal Oxide Semiconductor) type using six MISFETs.

  The mutual input / output terminals of the pair of CMOS inverters constituting the flip-flop circuit are cross-coupled via a pair of wirings (hereinafter referred to as local wirings). The source region of one transfer MISFET is connected to the input / output terminal of one CMOS inverter, and the source region of the other transfer MISFET is connected to the input / output terminal of the other CMOS inverter. One of the complementary data lines is connected to the drain region of one transfer MISFET, and the other of the complementary data lines is connected to the drain region of the other transfer MISFET. A word line is connected to each gate electrode of the pair of transfer MISFETs, and conduction and non-conduction of the transfer MISFETs are controlled by the word lines.

  By the way, with the increase in capacity of semiconductor memory devices in recent years, the area occupied by the memory cells of the above-mentioned complete CMOS SRAM has been steadily decreasing. However, when the area occupied by the memory cell is reduced, the storage node capacitance of the memory cell (pn junction capacitance and gate capacitance parasitic on the storage nodes A and B) is also reduced, and the amount of stored charge is reduced.

  As a result, the resistance to information inversion (so-called α-ray soft error) of the memory cell caused by α rays irradiated on the surface of the semiconductor chip is lowered, and it becomes difficult to ensure stable operation of the memory cells. Therefore, in order to promote miniaturization without degrading the stable operation of the memory cell, measures for securing the amount of accumulated charge are indispensable.

Japanese Patent Laid-Open No. 61-128557 (Patent Document 1) relates to an SRAM in which a flip-flop circuit of a memory cell is composed of an n-channel type driving MISFET and a load resistance element. In an SRAM, an electrode of polycrystalline silicon connected to a power supply voltage (VCC) or a reference voltage (VSS) is arranged above a memory cell, and a capacitance is formed by this electrode, a storage node, and an insulating film sandwiching these electrodes. Thus, the storage node capacity is increased.
JP-A-61-128557

  However, in order to further miniaturize the SRAM memory cell, a new measure for ensuring the amount of charge stored in the memory cell more reliably is indispensable.

  An object of the present invention is to provide a technology capable of increasing the storage node capacity of an SRAM memory cell and improving soft error resistance.

  Another object of the present invention is to provide a technique capable of miniaturizing SRAM memory cells.

  Another object of the present invention is to provide a technique capable of realizing high speed operation and low voltage operation of SRAM memory cells.

  Another object of the present invention is to provide a technique capable of improving the manufacturing yield and reliability of SRAM memory cells.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor integrated circuit device according to the present invention includes a semiconductor substrate having a main surface, a first conductivity type well region formed in the semiconductor substrate, and an active region formed on the well region on the main surface. A first insulating film surrounding the active region, a gate electrode of a MISFET formed on the active region, and a first conductivity type first semiconductor formed in the well region in the well region A second semiconductor region of the first conductivity type formed in the well region, a silicide layer formed on the first semiconductor region and the second semiconductor region, A second insulating film formed on the main surface and on the MISFET and having a connection hole on the first semiconductor region and the second semiconductor region, and formed on the connection hole, the first semiconductor region and the first semiconductor region 2 semiconductor And a conductive layer formed on a region, said first semiconductor regions are those constituting the source region of the MISFET.

A semiconductor integrated circuit device of the present invention includes a semiconductor substrate having a main surface, a memory cell having a first drive MISFET, a second drive MISFET, a first load MISFET, and a second load MISFET, A first insulating film formed on the first and second conductive layers so as to cover the first and second drive MISFETs and the first and second load MISFETs; And first and second local wirings formed on one insulating film,
The first and second drive MISFETs are arranged in a first direction apart from the first and second load MISFETs, and the gate electrodes of the first drive MISFETs and the first drive MISFETs The gate electrode of the load MISFET is integrally provided by the first conductive layer extending in the first direction on the main surface, and the gate electrode of the second drive MISFET, The gate electrode of the second load MISFET is integrally provided by the second conductive layer extending in the first direction on the main surface, and each of the first and second drive MISFETs The source region, channel region, and drain region, and the source region, channel region, and drain region of each of the first and second load MISFETs are provided in the semiconductor substrate, and The first local wiring extends in the first direction and is electrically connected between the drain region of the first driving MISFET and the drain region of the first load MISFET. And the second local wiring extends in the first direction, and is between the drain region of the second driving MISFET and the drain region of the second load MISFET. Are connected to form a second storage node, and a storage node capacitor is provided between the first storage node and the second storage node, and the first local wiring or the second storage node is provided. The two local wirings constitute one electrode of the storage node capacitive element.

A semiconductor integrated circuit device of the present invention includes a semiconductor substrate having a main surface, a memory cell having a first drive MISFET, a second drive MISFET, a first load MISFET, and a second load MISFET, A first insulating film formed on the first and second conductive layers so as to cover the first and second drive MISFETs and the first and second load MISFETs; And first and second local wirings formed on one insulating film,
The first and second drive MISFETs are arranged in a first direction apart from the first and second load MISFETs, and the gate electrodes of the first drive MISFETs and the first drive MISFETs The gate electrode of the load MISFET is integrally provided by the first conductive layer extending in the first direction on the main surface, and the gate electrode of the second drive MISFET, The gate electrode of the second load MISFET is integrally provided by the second conductive layer extending in the first direction on the main surface, and each of the first and second drive MISFETs The source region, channel region, and drain region, and the source region, channel region, and drain region of each of the first and second load MISFETs are provided in the semiconductor substrate, and The first local wiring extends in the first direction and is electrically connected between the drain region of the first driving MISFET and the drain region of the first load MISFET. And the second local wiring extends in the first direction, and is between the drain region of the second driving MISFET and the drain region of the second load MISFET. Are connected to form a second storage node, and the first local wiring and the second storage node are connected to the first local wiring and the layer connected to the second storage node. The storage node capacitive element between the two is configured.

A semiconductor integrated circuit device of the present invention includes a semiconductor substrate having a main surface, a memory cell having a first drive MISFET, a second drive MISFET, a first load MISFET, and a second load MISFET, A first insulating film formed on the first and second conductive layers so as to cover the first and second drive MISFETs and the first and second load MISFETs; And first and second local wirings formed on one insulating film,
The first and second drive MISFETs are arranged in a first direction apart from the first and second load MISFETs, and the gate electrodes of the first drive MISFETs and the first drive MISFETs The gate electrode of the load MISFET is integrally provided by the first conductive layer extending in the first direction on the main surface, and the gate electrode of the second drive MISFET, The gate electrode of the second load MISFET is integrally provided by the second conductive layer extending in the first direction on the main surface, and each of the first and second drive MISFETs The source region, channel region, and drain region, and the source region, channel region, and drain region of each of the first and second load MISFETs are provided in the semiconductor substrate, and The first local wiring extends in the first direction and is electrically connected between the drain region of the first driving MISFET and the drain region of the first load MISFET. And the second local wiring extends in the first direction, and is between the drain region of the second driving MISFET and the drain region of the second load MISFET. Are connected to form a second storage node, and a storage node capacitor is provided between the first storage node and the second storage node, and the first local wiring or the second storage node is provided. 2 local wirings constitute one electrode of the storage node capacitive element, a first capacitive element is provided between the first storage node and the first wiring, and the second storage node And a second capacitive element between the first wiring and the first wiring. It is.

A semiconductor integrated circuit device of the present invention includes a semiconductor substrate having a main surface, a memory cell having a first drive MISFET, a second drive MISFET, a first load MISFET, and a second load MISFET, A first insulating film formed on the first and second conductive layers so as to cover the first and second drive MISFETs and the first and second load MISFETs; And first and second local wirings formed on one insulating film,
The first and second drive MISFETs are arranged in a first direction apart from the first and second load MISFETs, and the gate electrodes of the first drive MISFETs and the first drive MISFETs The gate electrode of the load MISFET is integrally provided by the first conductive layer extending in the first direction on the main surface, and the gate electrode of the second drive MISFET, The gate electrode of the second load MISFET is integrally provided by the second conductive layer extending in the first direction on the main surface, and each of the first and second drive MISFETs The source region, channel region, and drain region, and the source region, channel region, and drain region of each of the first and second load MISFETs are provided in the semiconductor substrate, and The first local wiring extends in the first direction and is electrically connected between the drain region of the first driving MISFET and the drain region of the first load MISFET. And the second local wiring extends in the first direction, and is between the drain region of the second driving MISFET and the drain region of the second load MISFET. Are connected to form a second storage node, and a storage node capacitor is provided between the first storage node and the second storage node, and the first local wiring or the second storage node is provided. The second local wiring constitutes one electrode of the storage node capacitor element, a second insulating film is formed on the first and second local wirings, and a second insulating film is formed on the second insulating film. 1 wiring is formed, and the first local wiring and the first wiring Wiring and the first capacitive element is provided in the second capacitive element is formed between the first wiring and the second local wiring.

The outline of the invention other than the above-described invention of the present application is as follows.
(1) A semiconductor integrated circuit device according to the present invention includes a flip-flop circuit composed of a pair of CMOS inverters composed of a driving MISFET and a load MISFET, and a pair of input / output terminals connected to the flip-flop circuit. In the SRAM in which the memory cell is configured with the transfer MISFET, each gate electrode of the drive MISFET, the load MISFET, and the transfer MISFET is formed in the first conductive layer formed on the main surface of the semiconductor substrate. A pair of local wirings connecting the input / output terminals of the pair of CMOS inverters is formed by a second conductive layer formed on the first conductive layer, and a third layer formed on the second conductive layer. A reference voltage line connected to the source region of the driving MISFET is formed with a conductive layer, and the reference voltage line is connected to the one It is to place so as to overlap with the local interconnection.
(2) In the semiconductor integrated circuit device of the present invention, in the SRAM, a part of the local wiring extends on any one of the gate electrode of the driving MISFET, the load MISFET, or the transfer MISFET. It is.
(3) In the semiconductor integrated circuit device of the present invention, in the SRAM, a part of the local wiring extends on a semiconductor region constituting an input / output terminal of the CMOS inverter.
(4) In the semiconductor integrated circuit device according to the present invention, in the SRAM, a reference voltage supply made of a conductive material having a resistance lower than that of the third conductive layer constituting the reference voltage line is formed above the reference voltage line. A fourth conductive layer is formed, and the fourth conductive layer and the reference voltage line are electrically connected through a connection hole provided in at least one of each memory cell.
(5) In the semiconductor integrated circuit device of the present invention, in the SRAM, the connection hole connecting the fourth conductive layer and the reference voltage line, and the reference voltage line and the source region of the driving MISFET are connected. The connecting hole to be separated is disposed.
(6) In the semiconductor integrated circuit device of the present invention, in the SRAM, the local wiring is composed of a refractory metal silicide film.
(7) In the semiconductor integrated circuit device of the present invention, in the SRAM, the refractory metal silicide layer of the second conductive layer is formed on the drain region of the transfer MISFET, and the refractory metal silicide layer is formed on the refractory metal silicide layer. A pad layer of a third conductive layer is formed, and a data line is connected to the drain region via the pad layer and the refractory metal silicide layer.
(8) In the semiconductor integrated circuit device of the present invention, in the SRAM, the refractory metal silicide layer of the second conductive layer is formed on the source region of the load MISFET, and the refractory metal silicide layer is formed on the refractory metal silicide layer. A pad layer of a third conductive layer is formed, and a reference voltage is supplied to the source region through the pad layer and the refractory metal silicide layer.
(9) In the semiconductor integrated circuit device of the present invention, in the SRAM, a well feeding semiconductor region having a conductivity type different from that of the source region is formed on a main surface of a semiconductor substrate adjacent to the source region of the load MISFET, A power supply voltage is supplied to the source region and the well power supply semiconductor region via a pad layer and the refractory metal silicide layer.
(10) The semiconductor integrated circuit device according to the present invention may be configured with a conductive layer above the first conductive layer in the SRAM, instead of means for configuring the gate electrode of the transfer MISFET with the first conductive layer. To do.
(11) A semiconductor integrated circuit device according to the present invention includes a flip-flop circuit composed of a pair of CMOS inverters comprising a driving MISFET and a load MISFET, and a pair of input / output terminals connected to the flip-flop circuit. In the SRAM in which the memory cell is configured with the transfer MISFET, each gate electrode of the drive MISFET, the load MISFET, and the transfer MISFET is configured with the first conductive layer formed on the main surface of the semiconductor substrate. A second conductive layer formed above the first conductive layer constitutes a pair of local wirings connecting the input / output terminals of the pair of CMOS inverters, and a third conductive layer formed above the second conductive layer. A power supply voltage line connected to the source region of the load MISFET is formed by a conductive layer, and the power supply voltage line is connected to the power supply voltage line. It is to arranged so as to overlap with the pair of local wiring.
(12) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the first conductive type first semiconductor region and the second conductive type second semiconductor region, which are formed on the semiconductor substrate so as to be separated from each other, are connected. When forming, it has the following process (a)-(d).
(A) selectively forming a first silicon layer on a surface of each of the first semiconductor region and the second semiconductor region;
(B) forming a refractory metal film on the entire surface of the semiconductor substrate including on the first silicon layer;
(C) after forming a second silicon layer on the refractory metal film, patterning the second silicon layer into a wiring shape;
(D) The unreacted refractory metal remaining on the semiconductor substrate after siliciding the first silicon layer, the refractory metal film, and the second silicon layer by heat-treating the semiconductor substrate Removing the film;
(13) A method of manufacturing a semiconductor integrated circuit device according to the present invention is connected to a flip-flop circuit composed of a pair of CMOS inverters composed of a driving MISFET and a load MISFET, and a pair of input / output terminals of the flip-flop circuit. In the method of manufacturing an SRAM in which a memory cell is configured with a pair of transfer MISFETs, a pair of local wirings connecting the input / output terminals of the pair of CMOS inverters are formed in the following steps (a) to (d). To form.
(A) The respective surfaces of the first and second conductivity type first semiconductor regions and the second conductivity type second semiconductor region constituting the input / output terminals of the CMOS inverter, and the gate electrodes of the driving MISFET and the load MISFET Selectively forming a first silicon layer on a part of the surface of
(B) forming a refractory metal film on the entire surface of the semiconductor substrate including on the first silicon layer;
(C) after forming a second silicon layer on the refractory metal film, patterning the second silicon layer into a shape of a local wiring;
(D) The unreacted refractory metal remaining on the semiconductor substrate after siliciding the first silicon layer, the refractory metal film, and the second silicon layer by heat-treating the semiconductor substrate Removing the film.
(14) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the SRAM manufacturing method, prior to the step (a), each of the driving MISFET and the load MISFET is performed by dry etching using a photoresist as a mask. Removing a thick insulating film covering a part of the surface of the gate electrode; and etching back the entire surface of the semiconductor substrate to form a thin insulating film covering the surfaces of the first semiconductor region and the second semiconductor region. And removing the thin insulating film on the side wall of the gate electrode.
(15) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the manufacturing method of the SRAM, the height of the bottom surface of the refractory metal silicide layer formed on the surface of each of the first semiconductor region and the second semiconductor region is increased. The height is made higher than the upper surfaces of the gate insulating films of the driving MISFET and the load MISFET.
(16) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in patterning the second silicon layer into a shape of a local wiring in the step (c), the driving MISFET, Of the respective semiconductor regions of the load MISFET, the second silicon layer is not left in at least a part of the semiconductor region that does not constitute the input / output terminal of the CMOS inverter.
(17) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the method for manufacturing an SRAM, after the step (d), a reference voltage line or a power supply voltage line is formed in an upper layer of the local wiring, and the local wiring And a reference voltage line or a power supply voltage line.
(18) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the SRAM manufacturing method, the thickness of the second silicon layer formed on the refractory metal film in the step (c) is changed to the silicide. It is thicker than the film thickness required for conversion.
(19) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the method for manufacturing an SRAM, after the second silicon layer is formed on the refractory metal film in the step (c), the second silicon layer is formed. A second refractory metal film or a silicide film thereof is formed on the silicon layer.
(20) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing the SRAM, a data line and a power supply voltage line in each of the semiconductor regions of the driving MISFET, the transfer MISFET, and the load MISFET A refractory metal silicide layer is simultaneously formed on the surface of the semiconductor region to which any of the reference voltage lines is connected in the step of forming the local wiring.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to one invention of the present application, a capacitor is formed between the reference voltage line and the local wiring by arranging the reference voltage line formed in the upper layer of the local wiring so as to overlap the local wiring. The capacity of the storage node connected to the wiring can be increased, and the resistance to α-ray soft error of the memory cell can be improved.

  According to one invention of the present application, the gate capacitance component of the storage node capacitance is increased by arranging a part of the local wiring so as to overlap with the gate electrode of either the drive MISFET, the load MISFET, or the transfer MISFET. Therefore, it is possible to increase the storage node capacity of the memory cell and improve the alpha ray soft error resistance.

  According to one invention of the present application, by disposing a part of the local wiring so as to overlap the storage node of the memory cell, the diffusion layer capacitance component of the storage node capacitance can be increased. It can be increased to improve the resistance to α-ray soft errors.

  According to one invention of the present application, a low-resistance wiring is disposed above the reference voltage line, and power is supplied from the low-resistance wiring to the reference voltage line through at least one connection hole provided in each memory cell. As a result, the reference voltage can be supplied to each memory cell, so that the reference voltage can be stabilized. As a result, the minimum value (Vcc.min) of the power supply voltage is improved, and the resistance to α-ray soft error of the memory cell can be improved.

  According to one invention of the present application, the connection hole connecting the low-resistance wiring and the reference voltage line and the connection hole connecting the reference voltage line and the source region of the driving MISFET are separated from each other, thereby Therefore, the contact hole formation region can be flattened, and the contact resistance of these connection holes can be reduced to realize high-speed operation and low-voltage operation of the memory cell. .

  According to one aspect of the present invention, a local wiring is formed by causing a silicidation reaction between the polycrystalline silicon film, the refractory metal film deposited thereon, and the second polycrystalline silicon film deposited thereon. By forming the gate electrode, it is possible to prevent the silicon in the semiconductor region constituting the storage node of the memory cell from participating in the silicide reaction. Therefore, the junction leakage current in the semiconductor region is reduced and the operation reliability of the memory cell is improved. Can be improved.

  According to one invention of the present application, a mask alignment margin between the connection hole and the semiconductor region becomes unnecessary by performing the step of forming the connection hole in a part of the gate electrode and the step of exposing the semiconductor region separately. Therefore, the memory cell can be highly integrated by reducing the connection hole area. Further, since the local wiring and the semiconductor region are connected in a self-aligned manner with respect to the sidewall insulating film, a mask alignment margin is not required, so that the memory cell size can be reduced and high integration can be realized.

  According to one invention of the present application, a pair of local wirings connecting the storage nodes of the memory cell are formed of a refractory metal silicide, whereby a p-type impurity in the semiconductor region of the load MISFET or a semiconductor of the driving MISFET is obtained. Since n-type impurities in the region or in the gate electrode can be prevented from interdiffusion through the local wiring, ohmic and low resistance between the semiconductor regions having different conductivity types and between the semiconductor region and the gate electrode can be achieved. Thus, the memory cell can be operated at high speed and low voltage.

  According to the above-described means, even when misalignment occurs in the photoresist used as a mask when etching the upper polycrystalline silicon film, the lower polycrystalline silicon film can be prevented from being scraped. Therefore, the memory cell can be highly integrated by reducing the area of the semiconductor region.

  According to one invention of the present application, a low-resistance refractory metal silicide layer is formed on at least a part of the surface of each of the source region and the drain region of the transfer MISFET, the drive MISFET, and the load MISFET constituting the memory cell. As a result, the resistance of the source region and the drain region can be reduced, so that high speed operation and low voltage operation of the memory cell can be realized.

  According to one invention of the present application, the source region of the load MISFET, the drain region for well feeding, and the power supply voltage line are considered without considering the conductivity type of the pad layer of polycrystalline silicon formed on the refractory metal silicide layer. Can be connected to the source region of the load MISFET and the drain region for well power supply through one connection hole, whereby the source region of the load MISFET can be connected to the source region of the load MISFET. Since the well power supply drain region can be disposed adjacent to each other and the area thereof can be reduced, the memory cells can be highly integrated.

  According to one invention of the present application, when forming a local wiring by silicidation reaction, the polycrystalline silicon film deposited on the refractory metal silicide layer is deposited thicker than necessary for the silicidation reaction. As a result, the thickness of the local wiring is increased and the surface area thereof is increased, so that the capacitance formed between the local wiring and the reference voltage line in the upper layer is increased, thereby increasing the storage node capacitance of the memory cell. Can be further increased to improve the resistance to α-ray soft errors.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

FIG. 3 is an equivalent circuit diagram of the SRAM memory cell according to the present embodiment. As shown in the figure, the SRAM memory cell of the present embodiment has a pair of driving MISFETs Qd ₁ arranged at the intersections between a pair of complementary data lines (data line DL, data line bar DL) and a word line WL. , Qd ₂ , a pair of load MISFETs Qp ₁ , Qp _2, and a pair of transfer MISFETs Qt ₁ , Qt ₂ . The drive MISFETs Qd ₁ and Qd ₂ and the transfer MISFETs Qt ₁ and Qt ₂ are configured by an n-channel type, and the load MISFETs Qp ₁ and Qp ₂ are configured by a p-channel type. That is, this memory cell is composed of a complete CMOS type using four n-channel MISFETs and two p-channel MISFETs.

Of the six MISFETs constituting the memory cell, the drive MISFET Qd ₁ and the load MISFET Qp ₁ constitute a CMOS inverter (INV ₁ ), and the drive MISFET Qd ₂ and the load MISFET Qp ₂ constitute a CMOS inverter (INV _2). ). The mutual input / output terminals (storage nodes A, B) of the pair of CMOS inverters (INV ₁ , INV ₂ ) are cross-coupled via a pair of local wirings L ₁ , L ₂ to store 1-bit information. A flip-flop circuit as an information storage unit is configured.

Said one output terminal of the flip-flop circuit (storage node A) is connected to the source region of the transfer MISFET Qt _1, the other input-output terminal (the storage node B) is connected to the source region of the transfer MISFET Qt ₂ . The drain region of the transfer MISFET Qt ₁ is connected to the data line DL, and the drain region of the transfer MISFET Qt ₂ is connected to the data line bar DL.

Further, one end of the flip-flop circuit (source regions of the load MISFETs Qp ₁ and Qp ₂ ) is connected to the power supply voltage (VCC), and the other end (source regions of the drive MISFETs Qd ₁ and Qd ₂ ) is connected to the reference voltage (VSS). It is connected. The power supply voltage (VCC) is, for example, 5V, and the reference voltage (VSS) is, for example, 0V (GND potential).

The operation of the above circuit will be described. When the storage node A of _one CMOS inverter (INV ₁ ) is at a high potential (“H”), the driving MISFET Qd ₂ is turned on, so that the other CMOS inverter (INV ₂ ) Storage node B becomes low potential ("L"). Therefore, the driving MISFET Qd ₁ is turned OFF, and the high potential (“H”) of the storage node A is held. That is, the state of the mutual storage nodes A and B is held by a latch circuit in which a pair of CMOS inverters (INV ₁ and INV ₂ ) are cross-coupled, and information is stored while the power supply voltage is applied.

To the gate electrode of the transfer MISFET Qt _1, Qt ₂ is the word line WL is connected, the conduction of the transfer MISFET Qt _1, Qt ₂ by the word line WL, nonconductive is controlled. That is, when the word line WL is at a high potential (“H”), the transfer MISFETs Qt ₁ and Qt ₂ are turned on, and the latch circuit and the complementary data lines (data lines DL and DL) are electrically connected. Since they are connected, the potential states (“H” or “L”) of the storage nodes A and B appear on the data lines DL and DL, and are read as information of the memory cells.

In order to write information in the memory cell, the word line WL is set to the “H” potential level, the transfer MISFETs Qt ₁ and Qt ₂ are turned on, and the information on the data lines DL and bar DL is transmitted to the storage nodes A and B. Similarly, in order to read the information of the memory cell, the word line WL is set to the “H” potential level, the transfer MISFETs Qt ₁ and Qt ₂ are turned on, and the information of the storage nodes A and B is transmitted to the data lines DL and DL. To do.

  Next, a specific configuration of the memory cell is shown in FIG. 1 (plan view of a semiconductor substrate showing approximately one memory cell), FIG. 2 (cross-sectional view of the semiconductor substrate taken along line II-II ′ in FIG. 1), and This will be described with reference to FIGS. 1 and 4 to 7 show only the conductive layer of the memory cell, and insulating films such as an element isolation insulating film and an interlayer insulating film are not shown.

Six MISFETs constituting the memory cell are formed in the active region surrounded by the field insulating film 2 of the p ⁻ type semiconductor substrate 1. Each of the driving MISFETs Qd ₁ and Qd ₂ configured by the n-channel type and the transfer MISFETs Qt ₁ and Qt ₂ are formed in the active region of the p-type well 3, and the loading MISFETs Qp ₁ and Qp ₂ configured by the p-channel type are used. Is formed in the active region of the n-type well 4. Each of the p-type well 3 and the n-type well 4 is formed on the main surface of the p-type epitaxial silicon layer 5 formed on the semiconductor substrate 1.

The transfer MISFETs Qt ₁ and Qt ₂ have a gate electrode 6 configured integrally with the word line WL. The gate electrode 6 (word line WL) is formed of a polycrystalline silicon film (or a polycide film in which a polycrystalline silicon film and a refractory metal silicide film are stacked), and is formed of a gate insulating film 7 formed of a silicon oxide film. Formed on top.

The source and drain regions of the transfer MISFETs Qt ₁ and Qt ₂ are a low impurity concentration n ⁻ type semiconductor region 8 and a high impurity concentration n ⁺ type semiconductor region 9 formed in the active region of the p-type well 3. It consists of That is, the source region and the drain region of the transfer MISFETs Qt ₁ and Qt ₂ each have an LDD (Lightly Doped Drain) structure.

The driving MISFET Qd ₁ and the load MISFET Qp ₁ constituting _one CMOS inverter (INV ₁ ) of the flip-flop circuit have a common gate electrode 10 a and the driving MISFET Qp ₁ constituting the other CMOS inverter (INV ₂ ). The MISFET Qd ₂ and the load MISFET Qp ₂ have a common gate electrode 10b. These gate electrodes 10 a and 10 b are formed of the same polycrystalline silicon film as the gate electrodes 6 (word lines WL) of the transfer MISFETs Qt ₁ and Qt ₂ , and are formed on the gate insulating film 7. An n-type impurity (for example, phosphorus (P)) is introduced into the polycrystalline silicon film constituting the gate electrode 6 (word line WL) and the gate electrodes 10a and 10b.

The source region and drain region of each of the driving MISFETs Qd ₁ and Qd ₂ are a low impurity concentration n ⁻ type semiconductor region 8 and a high impurity concentration n ⁺ type semiconductor region 9 formed in the active region of the p type well 3. It is configured. That is, the source region and the drain region of each of the driving MISFETs Qd ₁ and Qd ₂ have an LDD structure. The source and drain regions of the load MISFETs Qp ₁ and Qp ₂ are a low impurity concentration p ⁻ type semiconductor region 11 and a high impurity concentration p ⁺ type semiconductor region formed in the active region of the n-type well 4. 12 is comprised. That is, the source region and the drain region of each of the load MISFETs Qp ₁ and Qp ₂ have an LDD structure.

A pair of silicon oxide insulating films 13 and sidewall insulating films (sidewall spacers) 14 covering the upper and sidewalls of the gate electrodes (6, 10a, 10b) are disposed on the upper layer of the six MISFETs constituting the memory cell. Local wirings L ₁ and L ₂ are formed. The pair of local wirings L ₁ and L ₂ is composed of a refractory metal silicide film formed by reacting a polycrystalline silicon film and a refractory metal film on the semiconductor substrate 1, for example, a cobalt silicide (CoSi _x ) film. ing. As will be described later, the pair of local wirings L ₁ and L ₂ are formed in a self-aligned manner with respect to the sidewall insulating film 14. The sidewall insulating film 14 is formed in a self-aligned manner with respect to the gate electrodes (6, 10a, 10b).

One local wiring L ₁ is connected to the drain region (p ⁺ type semiconductor region 12) of the load MISFET Qp ₁ and the drain region (n ⁺ type semiconductor region 9) of the drive MISFET Qd ₁ and has an opening in the insulating film 13. The connection MISFET Qd ₂ and the load MISFET Qp ₂ are connected to the gate electrode 10 b through the connection hole 15. The other local wiring L ₂ is connected to the drain region (p ⁺ type semiconductor region 12) of the load MISFET Qp ₂ and the drain region (n ⁺ type semiconductor region 9) of the drive MISFET Qd ₂ and has an opening in the insulating film 13. It is connected to the gate electrode 10a of the driving MISFET Qd ₁ and the load MISFET Qp ₁ through the connection hole 15 that is.

The surface of the drain region of the transfer MISFET Qt ₁ ^{(n +} -type semiconductor region 9) is a refractory metal silicide layer, for example, cobalt silicide layers 16 are formed, the drain region of the transfer MISFETQt2 the ^{(n +} -type semiconductor region 9) The same cobalt silicide layer 16 is formed on the surface. Data lines DL and DL are connected to the drain regions of the transfer MISFETs Qt ₁ and Qt ₂ through the cobalt silicide layer 16. The cobalt silicide layer 16 is formed in the same process as the local wirings L ₁ and L ₂ as described later.

A refractory metal silicide layer, for example, a cobalt silicide layer 17 is formed on the surface of the source region (p ⁺ type semiconductor region 12) of the load MISFET Qp ₁ and the n ⁺ type semiconductor region 18 formed adjacent to the source region. is, the source region (p ⁺ -type semiconductor region 12) and the same cobalt silicide layer 17 and also on the surface of the adjacent to the source region is formed n ⁺ -type semiconductor region 18 of the load MISFET Qp ₂ are formed . A power supply voltage (Vcc) is supplied to the source regions of the load MISFETs Qp ₁ and Qp ₂ and the n ⁺ type semiconductor region 18 through a power supply voltage line described later. The cobalt silicide layer 17 is formed in the same process as the local wirings L ₁ and L ₂ and the cobalt silicide layer 16 as described later.

4 and 5 are plan views showing the layout of the pair of local wirings L ₁ and L ₂ and the underlying gate electrodes 10a and 10b.

As shown in FIG. 4, one of the local lines L ₁ is partially extends so as to overlap with the gate electrode 10a, and the other local wiring L _2, extending as a part overlaps with the gate electrode 10b Exist. Although not shown in the drawing, the local wirings L ₁ and L ₂ may extend so as to partially overlap the gate electrode 6 (word line WL).

As described above, the SRAM memory cell according to the present embodiment has the gate electrodes (of the driving MISFET Qd ₁ and the load MISFET Qp ₁ ) as long as the layout allows a part of the local wirings L ₁ and L _2. The gate electrode 10b (of the driving MISFET Qd ₂ and the load MISFET Qp ₂ ) or the gate electrode 6 (of the transfer MISFETs Qt ₁ and Qt ₂ ) (word line WL) is arranged. With this configuration, since the gate capacitance component (C ₁ ) (see FIG. 3) of the storage node capacitance can be increased, the storage node capacitance of the memory cell can be increased and the α-ray soft error resistance can be improved.

Further, as shown by the shaded pattern in FIG. 5, one of the local wirings L ₁ is part of the semiconductor region (the n ⁺ type semiconductor region 9 of the driving MISFET Qd ₁ and the load) constituting the storage node A of the memory cell. The other local wiring L ₂ extends so as to overlap with the p ⁺ type semiconductor region 12 of the MISFET Qp ₁ for use, and a part of the other local wiring L ₂ constitutes the storage node B of the memory cell (n ^{+ of the} driving MISFET Qd ₂ ) ^. It extends to overlap the type ^{p +} -type semiconductor region 12 of the semiconductor region 9 and the load MISFET Qp _2).

That is, the SRAM memory cell of the present embodiment is arranged so that part of the local wirings L ₁ and L ₂ overlaps the storage nodes A and B of the memory cell. With this configuration, the diffusion layer capacitance component of the storage node capacitance can be increased, so that the storage node capacitance of the memory cell can be increased to improve the α-ray soft error resistance.

A reference voltage line 20 is formed on the local wirings L ₁ and L ₂ via a thin insulating film 19 formed of a laminated film of a silicon oxide film and a silicon nitride film. The reference voltage line 20 is disposed so as to cover the upper portions of the local wirings L ₁ and L ₂ . The reference voltage line 20 is composed of a polycrystalline silicon film into which an n-type impurity (for example, P) is introduced, and is a connection hole opened in the insulating film 19 and the insulating film (the same insulating film as the gate insulating film 7). 21 (see FIG. 1) is connected to the respective source regions (n ⁺ type semiconductor regions 9) of the driving MISFETs Qd ₁ and Qd ₂ .

A pad layer 22 made of the same polycrystalline silicon film as the reference voltage line 20 is formed above the drain regions (n ⁺ type semiconductor regions 9) of the transfer MISFETs Qt ₁ and Qt ₂ . The pad layer 22 is electrically connected to the refractory metal silicide layer 16 through a connection hole 23 formed in the insulating film 19. A pad layer 24 made of the same polycrystalline silicon film as that of the reference voltage line 20 is formed on the source layer (p ⁺ type semiconductor region 12) of each of the load MISFETs Qp ₁ and Qp ₂ . . The pad layer 24 is electrically connected to the refractory metal silicide layer 17 through a connection hole 25 opened in the insulating film 19.

6 is a plan view showing the layout of the reference voltage line 20 and the local wirings L ₁ and L ₂ below it, and FIG. 7 is a perspective view of the same.

As shown in the figure, the reference voltage line 20 is formed so as to cover almost the entire upper layer of the local wirings L ₁ and L ₂ . That is, the memory cell of the SRAM of the present embodiment is arranged so as to overlap the reference voltage line 20 formed on the upper layer of the local wiring L _1, L ₂ and the local wiring L _1, L _2. With this configuration, the capacitor (C ₂ ) (see FIG. 3) is formed by the reference voltage line 20, the local wirings L ₁ and L _2, and the thin insulating film 19 sandwiching them, so that it is connected to the local wirings L ₁ and L ₂ . The capacity of the stored storage nodes A and B can be increased, and the resistance to α-ray soft error of the memory cell can be improved.

  A first level metal wiring is formed above the reference voltage line 20 via an interlayer insulating film 26. The interlayer insulating film 26 is composed of a laminated film of, for example, a silicon oxide film and a BPSG (Boro Phospho Silicate Glass) film. The first-layer metal wiring is made of, for example, an aluminum (Al) alloy, and constitutes a power supply voltage line 27, a sub-reference voltage line 28, a sub-word line (or divided word line) 29, a pad layer 30, and the like. .

  The power supply voltage line 27 is electrically connected to the pad layer 24 through a connection hole 31 opened in the interlayer insulating film 26. The sub reference voltage line 28 is electrically connected to the reference voltage line 20 through a connection hole 32 (see FIG. 1) opened in the interlayer insulating film 26. The sub word line 29 is electrically connected to the word line WL through a connection hole (not shown) formed in the interlayer insulating film 26 and the insulating films 19 and 13. The pad layer 30 is electrically connected to the pad layer 22 through a connection hole 33 opened in the interlayer insulating film 26.

  As described above, the SRAM memory cell according to the present embodiment has the sub-reference voltage line 28 made of Al having a lower resistance than that of polycrystalline silicon on the reference voltage line 20 made of a polycrystalline silicon film. The power is supplied from the sub reference voltage line 28 to the reference voltage line 20 through the connection hole 32 provided at least one in each memory cell. With this configuration, since the reference voltage (Vss) can be supplied to each memory cell, the reference voltage (Vss) can be stabilized. As a result, the minimum value (Vcc.min) of the power supply voltage (Vcc) is improved, and the resistance to α-ray soft error of the memory cell can be improved.

Further, as shown in FIG. 1, the SRAM memory cell of the present embodiment includes the connection hole 32 for connecting the sub-reference voltage line 28 and the reference voltage line 20, the reference voltage line 20 and the driving MISFETs Qd ₁ , The connection hole 21 connecting the source region (n ⁺ type semiconductor region 9) of Qd ₂ is spaced apart. With this configuration, a step due to the overlapping of the connection holes 21 and 32 can be avoided, and the connection hole forming region can be flattened. Therefore, the contact resistance of the connection holes 21 and 32 can be reduced, and the memory cell can operate at high speed and low voltage. Operation can be realized.

  A second-layer metal wiring is formed above the first-layer metal wiring via an interlayer insulating film 34. The interlayer insulating film 34 is composed of a three-layer film in which a silicon oxide film 34a, a spin on glass film 34b, and a silicon oxide film 34c are stacked in order from the lower layer. The second-layer metal wiring is made of, for example, an aluminum alloy, and constitutes the data lines DL and bars DL. The data lines DL and bars DL are electrically connected to the pad layer 30 through connection holes 35 formed in the interlayer insulating film 34.

  Next, a method for manufacturing the SRAM memory cell of the present embodiment configured as described above will be described. In each of the drawings (FIGS. 8 to 39) showing the manufacturing method of the memory cell, the cross-sectional view corresponds to the II-II 'line in FIG. In the plan view, only the conductive layer of the memory cell is shown, and the insulating film between the conductive layers is not shown.

First, as shown in FIG. 8, after a p-type epitaxial silicon layer 5 is grown on a semiconductor substrate 1 made of p ⁻ -type single crystal silicon, a well-known LOCOS using a silicon nitride film as a thermal oxidation mask is used. The field insulating film 2 composed of a thick silicon oxide film is formed on the surface of the epitaxial silicon layer 5 by the method. Subsequently, after introducing n-type impurities (P) and p-type impurities (BF ₂ ) into the epitaxial silicon layer 5 by ion implantation using a photoresist as a mask, these impurities are stretched and diffused to form p-type wells. 3 and n-type well 4 are formed. Next, a gate insulating film 7 made of a thin silicon oxide film having a thickness of about 9 nm is formed on each main surface of the p-type well 3 and the n-type well 4 surrounded by the field insulating film 2.

  FIG. 9 is a plan pattern of the active region AR (for one memory cell) surrounded by the field insulating film 2. The memory cell is formed in a rectangular area surrounded by four + marks shown in FIG. As an example, the size of the memory cell is about 4.0 (μm) × 2.8 (μm). Further, FIG. 10 shows a pattern of the active region AR for 16 memory cells.

Next, as shown in FIGS. 11 and 12, the transfer MISFET Qt _1, the gate electrode of the Qt ₂ 6 (word line WL), the driving MISFET Qd _1, Qd ₂ and load MISFET Qp _1, the gate electrode 10a of Qp ₂ , 10b. The gate electrode 6 (word line WL) and the gate electrodes 10a and 10b are deposited on the entire surface of the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method after depositing an appropriate polycrystalline silicon film having a thickness of 100 nm by the CVD method. An insulating film 13 of silicon oxide (film thickness of about 120 nm) is deposited, and the insulating film 13 and the polycrystalline silicon film are patterned by dry etching using a photoresist as a mask. FIG. 13 shows a pattern for 16 memory cells of the gate electrode 6 (word line WL) and the gate electrodes 10a and 10b.

Next, as shown in FIG. 14, n-type impurities (phosphorus (P) and arsenic (As)) are introduced into the p-type well 3 and part of the n-type well 4 by ion implantation using a photoresist as a mask. To do. Next, after removing the photoresist, a p-type impurity (boron fluoride (BF ₂ )) is introduced into the n-type well 4 by ion implantation using the photoresist as a mask, as shown in FIG. Next, after removing the photoresist, a silicon oxide film deposited on the entire surface of the semiconductor substrate 1 is patterned by the RIE (Reactive Ion Etching) method, and as shown in FIG. 16, the gate electrode 6 (word Side wall insulating films (side wall spacers) 14 are formed on the side walls of the line WL) and the gate electrodes 10a and 10b in a self-aligning manner with respect to them.

Next, as shown in FIG. 17, n-type impurities (P, As) are introduced into the p-type well 3 and part of the n-type well 4 by ion implantation using a photoresist as a mask. Next, after removing the photoresist, as shown in FIG. 18, p-type impurities (BF ₂ ) are introduced into the n-type well 4 by ion implantation using the photoresist as a mask.

Next, after removing the photoresist, the n-type impurity and the p-type impurity are thermally diffused to transfer MISFETs Qt ₁ and Qt _{2 on} the main surface of the p-type well 3 as shown in FIG. Source regions and drain regions (n ⁻ type semiconductor region 8 and n ⁺ type semiconductor region 9) of MISFETs Qd ₁ and Qd ₂ are formed, and source regions of the load MISFETs Qp ₁ and Qp ₂ are formed on the main surface of the n type well 4. The drain region (p ⁻ type semiconductor region 11, p ⁺ type semiconductor region 12) is formed. In addition, an n ⁺ -type semiconductor region 18 for well feeding is formed on the main surface of the n-type well 4 adjacent to the source regions (p ⁺ -type semiconductor region 12) of the load MISFETs Qp ₁ and Qp ₂ .

Next, as shown in FIG. 20, a connection hole 15 is formed in the insulating film 13 covering the gate electrodes 10a and 10b of the driving MISFETs Qd ₁ and Qd ₂ by dry etching using a photoresist as a mask. A part of each of the electrodes 10a and 10b is exposed.

Next, after removing the photoresist, as shown in FIG. 21, the entire surface of the semiconductor substrate 1 is etched back, and the source regions of the driving MISFETs Qd ₁ , Qd ₂ and the transfer MISFETs Qt ₁ , Qt ₂ , Thin covering the surfaces of the drain region (n ⁺ type semiconductor region 9), the source regions of the load MISFETs Qp ₁ and Qp ₂ , the drain region (p ⁺ type semiconductor region 12), and the n ⁺ type semiconductor region 18 for supplying the well The insulating film (the insulating film in the same layer as the gate insulating film 7) is removed, and the n ⁺ type semiconductor region 9, the p ⁺ type semiconductor region 12, and the n ⁺ type semiconductor region 18 are exposed.

As described above, in the manufacturing method of the present embodiment, first, the connection hole 15 is formed in the insulating film 13 on the gate electrodes 10a and 10b by dry etching using a photoresist as a mask, and then the entire surface of the semiconductor substrate 1 is etched back. Then, the insulating films covering the surfaces of the n ⁺ type semiconductor region 9, the p ⁺ type semiconductor region 12, and the n ⁺ type semiconductor region 18 are removed.

That is, the step of exposing part of the gate electrodes 10a and 10b and the step of exposing the n ⁺ type semiconductor region 9, the p ⁺ type semiconductor region 12 and the n ⁺ type semiconductor region 18 are performed separately, and the n ⁺ type semiconductor is performed. Region 9, p ⁺ type semiconductor region 12 and n ⁺ type semiconductor region 18 are exposed to sidewall insulating film 14 in a self-aligned manner. With this configuration, a mask alignment margin between the connection hole 15 and the n ⁺ -type semiconductor region 9, the p ⁺ -type semiconductor region 12, and the n ⁺ -type semiconductor region 18 becomes unnecessary, and thus the connection hole 15, the n ⁺ -type semiconductor region 9, Memory cells can be highly integrated by reducing the areas of the p ⁺ type semiconductor region 12 and the n ⁺ type semiconductor region 18.

When there is a margin for mask alignment, instead of the above means, a part of the gate electrodes 10a and 10b, the n ⁺ type semiconductor region 9, the p ⁺ type semiconductor region 12 and the dry etching using a photoresist as a mask The n ⁺ type semiconductor region 18 may be exposed at the same time. In this case, the etching back process is not necessary, and the manufacturing process of the memory cell can be shortened.

Next, as shown in FIGS. 22 and 23, each of the gate electrodes 10a and 10b exposed in the above process, the n ⁺ type semiconductor region 9, the p ⁺ type semiconductor region 12 and the n ⁺ type semiconductor region 18 respectively. A thin polycrystalline silicon film 36 having a thickness of about 40 nm is selectively deposited on the surface by selective CVD. That is, the polycrystalline silicon film 36 is deposited only on the gate electrodes 10a and 10b, the n ⁺ type semiconductor region 9, the p ⁺ type semiconductor region 12 and the n ⁺ type semiconductor region 18, and the insulating film 13 made of a silicon oxide film, Do not deposit on 14. Alternatively, a polycrystalline silicon film 36 is deposited on the entire surface of the semiconductor substrate 1 by a CVD method, and the polycrystalline silicon film 36 is patterned by dry etching using a photoresist as a mask, thereby forming a part of the gate electrodes 10a and 10b, Polycrystalline silicon film 36 may be left on the surfaces of n ⁺ type semiconductor region 9, p ⁺ type semiconductor region 12 and n ⁺ type semiconductor region 18.

Next, as shown in FIG. 24, a thin Co film 37 having a film thickness of about 20 nm is deposited on the entire surface of the semiconductor substrate 1 by sputtering, and then the CVD method or sputtering is performed on the entire surface of the semiconductor substrate 1 as shown in FIG. A thin polycrystalline silicon film 38 having a thickness of about 40 nm is deposited by the method. As described above, the manufacturing method according to the present embodiment uses polycrystalline silicon on the surfaces of part of the gate electrodes 10 a and 10 b, the n ⁺ type semiconductor region 9, the p ⁺ type semiconductor region 12, and the n ⁺ type semiconductor region 18. A film 36, a Co film 37, and a polycrystalline silicon film 38 are deposited, and a Co film 37 and a polycrystalline silicon film 38 are deposited in other regions (on the insulating film). Instead of the Co film 37, another refractory metal film, for example, a thin film such as W, Mo, Ti, or Ta may be deposited.

Next, as shown in FIG. 26, the upper polycrystalline silicon film 38 is patterned by dry etching using the photoresist 39 as a mask to form regions for forming the local wirings L ₁ and L ₂ , transfer MISFETs Qt ₁ and Qt _2. On the surfaces of the drain region (n ⁺ type semiconductor region 9), the source regions (p ⁺ type semiconductor region 12) of the load MISFETs Qp ₁ and Qp ₂ and the n ⁺ type semiconductor region 9 adjacent thereto. Leave 38.

Photoresist 39 as an etching mask of the polycrystalline silicon film 38, the driving MISFET Qd _1, Qd ₂ of the drain region ^{(n +} -type semiconductor region 9) and load MISFET Qp _1, Qp ₂ of the drain region ^{(p +} -type semiconductor The upper part of the region 12) may not be completely covered. That is, as shown in FIG. 26, even if a part of the polycrystalline silicon film 38 on the n.sup. ⁺ Type semiconductor region 9 is etched due to the mask misalignment of the photoresist 39, there is no problem. Absent. This is because even if a part of the polycrystalline silicon film 38 is etched, the underlying Co film 37 serves as an etching stopper, so that the polycrystalline silicon on the surfaces of the n ⁺ type semiconductor region 9 and the p ⁺ type semiconductor region 12 is removed. This is because the film 36 is not etched.

Although there is no particular limitation, in the present embodiment, when the polycrystalline silicon film 38 is etched, of the n ⁺ type semiconductor regions 9 (source region and drain region) of the driving MISFETs Qd ₁ and Qd ₂ , The polycrystalline silicon film 38 is left on the n ⁺ type semiconductor region 9 (drain region) constituting the storage nodes A and B, but on the n ⁺ type semiconductor region 9 (source region) not constituting the storage nodes A and B. Does not leave the polycrystalline silicon film 38. It is not necessary to completely remove the polycrystalline silicon film 38 on the n ⁺ type semiconductor region 9 (source region), and a part of the polycrystalline silicon film 38 remains without being etched due to misalignment of the mask of the photoresist 39. There is no problem.

Next, after removing the photoresist 39, the semiconductor substrate 1 is heat-treated in an inert gas atmosphere at about 700 ° C., and silicided between the polycrystalline silicon film 38, the Co film 37, and the polycrystalline silicon film 36. Cause a reaction. Next, the unreacted Co film 37 remaining on the region where the polycrystalline silicon films 36 and 38 are not deposited is removed by wet etching, thereby forming a cobalt silicide film as shown in FIGS. Local wirings L ₁ and L ₂ and cobalt silicide layers 16, 17 and 36 ′ are formed. FIG. 29 shows a pattern for 16 memory cells of the local wirings L ₁ and L ₂ and the cobalt silicide layers 16, 17 and 36 ′.

As described above, in the manufacturing method of the present embodiment, the pair of local wirings L ₁ and L ₂ that connect between the storage nodes A and B of the memory cell are made of cobalt silicide. Cobalt silicide is a material having a lower electrical resistance than polycrystalline silicon and a material serving as an effective barrier against the diffusion of impurity atoms such as P (phosphorus) and B (boron). Therefore, with this configuration, the p-type impurity in the drain region (p ⁺ type semiconductor region 12) of the load MISFETs Qp ₁ and Qp ₂ , the drain region (n ⁺ type semiconductor region 9) of the drive MISFETs Qd ₁ and Qd ₂ , or Since the n-type impurities in the gate electrodes 10a and 10b can be prevented from interdiffusion through the local wirings L ₁ and L ₂ , the p ⁺ type semiconductor region 12 and the n ⁺ type semiconductor region 9 having different conductivity types can be prevented. In addition, the gate electrodes 10a and 10b can be connected to each other in an ohmic manner with a low resistance, and high-speed operation and low-voltage operation of the memory cell can be realized.

Further, in the manufacturing method of the present embodiment, when the local wirings L ₁ and L ₂ are formed, the drain regions (n ⁺ type semiconductor regions) of the driving MISFETs Qd ₁ and Qd ₂ constituting the storage nodes A and B of the memory cells are formed. 9) and a polycrystalline silicon film 36 are selectively formed on the respective surfaces of the drain regions (p ⁺ type semiconductor regions 12) of the load MISFETs Qp ₁ and Qp ₂ , and a Co film 37 and polycrystalline silicon are further formed thereon. A film 38 is formed to cause a silicidation reaction between the three layers. With this configuration, it is possible to prevent silicon in the n ⁺ type semiconductor region 9 and p ⁺ type semiconductor region 12 constituting the storage nodes A and B of the memory cell from participating in the silicidation reaction. 16 and 17 can be formed shallowly, the junction leakage current of the n ⁺ type semiconductor region 9 and the p ⁺ type semiconductor region 12 can be reduced, and the operation reliability of the memory cell can be improved.

In contrast, when the Co film 37 is directly brought into contact with the n ⁺ type semiconductor region 9 and the p ⁺ type semiconductor region 12 without providing the polycrystalline silicon film 36, the n ⁺ type semiconductor region 9 and the p ⁺ type semiconductor are provided. Since the silicon in the region 12 is involved in the silicidation reaction, the cobalt silicide layers 16 and 17 are deeply formed in the substrate (p-type well 3 and n-type well 4), and the n ⁺ -type semiconductor region 9 and p ^{+ are formed.} Junction leakage current leaking from the type semiconductor region 12 to the substrate increases.

In order to prevent silicon in the n ⁺ -type semiconductor region 9 and the p ⁺ -type semiconductor region 12 from participating in the silicide reaction, the local wires L ₁ and L ₂ are formed even after the formation of the local wires L ₁ and L ₂ by the silicidation reaction. ₁ , L ₂ and its underlying n ⁺ -type semiconductor region 9 and p ⁺ -type semiconductor region 12, the film thickness is controlled so that a polycrystalline silicon film 36 at least larger than the thickness of the gate insulating film 7 remains. Good.

In addition, according to the above configuration, even when a misalignment occurs in the photoresist 39 serving as a mask when etching the upper polycrystalline silicon film 38, the n ⁺ type forming the storage nodes A and B of the memory cell. The polycrystalline silicon film 36 on the semiconductor region 9 and the p ⁺ type semiconductor region 12 can be prevented from being scraped. Therefore, the alignment margin of the photoresist 39 is not required, and the areas of the n ⁺ type semiconductor region 9 and the p ⁺ type semiconductor region 12 can be reduced, and the memory cells can be highly integrated.

In addition, the manufacturing method of the present embodiment has a source region of each of the six MISFETs (transfer MISFETs Qt ₁ and Qt ₂ , drive MISFETs Qd ₁ and Qd ₂ , load MISFETs Qp ₁ and Qp ₂ ) constituting the memory cell. A low-resistance cobalt silicide layer 16 (or 17) is formed on at least a part of the surface of the drain region. With this configuration, the resistance of the source region and drain region in which the cobalt silicide layer 16 (or 17) is formed can be reduced, so that high speed operation and low voltage operation of the memory cell can be realized.

Further, in the manufacturing method of the present embodiment, when the polycrystalline silicon film 38 is etched, the memory cell is stored in the n ⁺ type semiconductor regions 9 (source region and drain region) of the driving MISFETs Qd ₁ and Qd _2. The polycrystalline silicon film 38 is not left on the n ⁺ type semiconductor region 9 (source region) that does not constitute the nodes A and B. With this configuration, it is possible to prevent a short circuit between the source region and the drain region of the driving MISFETs Qd ₁ and Qd _{2 through} the polycrystalline silicon film 38 and the local wirings L ₁ and L ₂ , so that the manufacturing yield and reliability of the SRAM can be reduced. Can be improved.

In the manufacturing method of the present embodiment, the local wirings L ₁ and L ₂ are formed in a self-aligned manner with respect to the sidewall insulating film 14 of the gate electrodes (6, 10a, 10b). With this configuration, when the local wirings L ₁ and L ₂ are connected to the n ⁺ type semiconductor region 9 and the p ⁺ type semiconductor region 12 constituting the storage nodes A and B, there is no need for a mask alignment margin between them. Therefore, as shown in FIG. 28, the distances Z ₁ and Z ₂ along the extending direction of the word line WL can be reduced, and the memory cell size is reduced to realize high integration of the memory cells. be able to.

  Next, as shown in FIG. 30, an insulating film 19 is deposited on the entire surface of the semiconductor substrate 1 by the CVD method. The insulating film 19 is formed by laminating a silicon nitride film having a thickness of about 10 nm on a silicon oxide film having a thickness of about 10 nm.

Next, as shown in FIG. 31, the insulating film 19 on the drain regions (n ⁺ type semiconductor regions 9) of the transfer MISFETs Qt ₁ and Qt ₂ is removed by dry etching using a photoresist as a mask to connect the connection holes. 23, and the insulating film 19 on each of the source regions (p ⁺ type semiconductor regions 12) of the load MISFETs Qp ₁ and Qp ₂ and the well power supply n ⁺ type semiconductor regions 18 adjacent to the source regions is removed. Thus, the connection hole 25 is formed. Although not shown in the figure, the insulating film 19 on the source region (n ⁺ type semiconductor region 9) of the driving MISFETs Qd ₁ and Qd ₂ is removed to form the connection hole 21.

Next, after depositing a polycrystalline silicon film having a film thickness of about 70 nm on the entire surface of the semiconductor substrate 1 by CVD, the polycrystalline silicon film is patterned by dry etching using a photoresist as a mask. As shown, the reference voltage line 20, the pad layer 22, and the pad layer 24 are formed. The reference voltage line 20 is disposed so as to cover the upper portions of the local wirings L ₁ and L ₂ , and is connected to the source regions (n ⁺ type semiconductor regions 9) of the driving MISFETs Qd ₁ and Qd ₂ through the connection holes 21. The pad layer 22 is connected to the cobalt silicide layer 16 through the connection hole 23, and the pad layer 24 is connected to the cobalt silicide layer 17 through the connection hole 25. FIG. 34 shows a pattern for 16 memory cells of the reference voltage line 20 and the pad layers 22 and 24.

  Next, as shown in FIG. 35, an interlayer insulating film 26 is deposited on the entire surface of the semiconductor substrate 1 by the CVD method. The interlayer insulating film 26 is formed by laminating a BPSG film having a thickness of about 300 nm on a silicon oxide film having a thickness of about 150 nm, and then planarizing the BPSG film by reflow.

  Next, after forming connection holes 31 and 33 in the interlayer insulating film 26 by dry etching using a photoresist as a mask, an Al alloy film having a film thickness of about 300 nm is deposited on the entire surface of the semiconductor substrate 1 by sputtering. The Al alloy film is patterned by dry etching using as a mask, and as shown in FIGS. 36 and 37, a power supply voltage line 27, a sub reference voltage line 28, a sub word line 29, and a pad layer 30 are formed on the interlayer insulating film 26. Form.

As described above, the manufacturing method of the present embodiment is adjacent to the source regions (p ⁺ type semiconductor regions 12) of the load MISFETs Qp ₁ and Qp _{2 and} the source regions through the connection holes 31 opened in the interlayer insulating film 26. When the power supply voltage line 27 is connected to the n ⁺ type semiconductor region 18 for supplying the well, a polycrystalline silicon pad layer 24 is provided on the p ⁺ type semiconductor region 12 and the n ⁺ type semiconductor region 18 in advance. Further, when connecting the pad layer 30 to the transfer MISFET Qt _1, Qt ₂ of the drain region ^{(n +} -type semiconductor region 6) through the connection hole 33 opened in the interlayer insulating film 26, previously in the ^{n +} -type semiconductor region 6 A polycrystalline silicon pad layer 22 is provided thereon.

  With this configuration, when the connection holes 31 and 33 are formed by etching the interlayer insulating film 26, the cobalt silicide layers 16 and 17 are not exposed at the bottoms of the connection holes 31 and 33. , 17 can be prevented.

The manufacturing method of this embodiment, the load MISFET Qp1, Qp ₂ of the source region ^{(p +} -type semiconductor region 12) and the ^{n +} -type semiconductor region 18 and the power supply voltage line for well power supply adjacent to the source region 27 And the cobalt silicide layer 16 is formed on the surfaces of the p ⁺ type semiconductor region 12 and the n ⁺ type semiconductor region 18 in advance. With this configuration, the p ⁺ type semiconductor region 12 and the n ⁺ type semiconductor region 18 and the power supply voltage line 27 can be connected without considering the conductivity type of the pad layer 24 of polycrystalline silicon formed on the cobalt silicide layer 16. Since the connection can be ohmic, a power supply voltage (Vcc) can be simultaneously supplied to the p ⁺ type semiconductor region 12 and the n ⁺ type semiconductor region 18 through one connection hole 31. Therefore, the p ⁺ type semiconductor region 12 and the n ⁺ type semiconductor region 18 can be disposed adjacent to each other and their area can be reduced, so that the memory cells can be highly integrated.

  Next, as shown in FIG. 38, an interlayer insulating film 34 is deposited on the entire surface of the semiconductor substrate 1. The interlayer insulating film 34 is formed by spin-coating a spin-on-glass film 34b having a thickness of about 250 nm on a silicon oxide film 34a having a thickness of about 500 nm deposited by CVD, and then etching back the surface of the spin-on-glass film 34b. After planarization, a silicon oxide film 34c having a thickness of about 400 nm is deposited thereon by CVD.

  Thereafter, after forming a connection hole 35 in the interlayer insulating film 34 by dry etching using a photoresist as a mask, an Al alloy film is deposited on the entire surface of the semiconductor substrate 1 by sputtering, and this etching is performed by dry etching using a photoresist as a mask. By patterning the Al alloy film to form the data line DL and the data line bar DL, the SRAM memory cell of the present embodiment is completed. FIG. 39 shows a pattern for 16 memory cells of the data line DL and the data line bar DL.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

In the embodiment, when the local wirings L ₁ and L ₂ are formed, the drain regions (n ⁺ type semiconductor regions 9) and the load for the driving MISFETs Qd ₁ and Qd ₂ constituting the storage nodes A and B of the memory cell are used. A polycrystalline silicon film 36, a Co film 37, and a polycrystalline silicon film 38 are formed on the respective surfaces of the drain regions (p ⁺ type semiconductor regions 12) of the MISFETs Qp ₁ and Qp ₂ to perform a silicidation reaction between the three layers. However, the lower polycrystalline silicon film 36 is not always necessary, and a silicidation reaction is caused between the Co film 37 and the polycrystalline silicon film 38 deposited thereon to cause local wirings L ₁ and L _2. Can also be formed.

In this case, the step of selectively depositing the polycrystalline silicon film 36 on the surface of the drain region (n ⁺ type semiconductor region 9, p ⁺ type semiconductor region 12) becomes unnecessary, and therefore the number of memory cell manufacturing steps is reduced. can do. However, in this case, the Co film 37 is directly deposited on the surface of the drain region (n ⁺ type semiconductor region 9, p ⁺ type semiconductor region 12). In order to prevent the silicidation reaction from proceeding between them, the upper polycrystalline silicon film 38 must be sufficiently thick to supply silicon necessary for the silicidation reaction from the polycrystalline silicon film 38.

Further, when the upper polycrystalline silicon film 38 is patterned by dry etching using a photoresist as a mask, one of the polycrystalline silicon films 38 on the drain region (n ⁺ type semiconductor region 9, p ⁺ type semiconductor region 12). When the portion is etched, the silicidation reaction proceeds between the silicon in the drain region and the Co film 37, so that a sufficient mask alignment margin is secured, and the polycrystalline silicon film 38 is formed in the drain region (n ⁺ -type). It is necessary to prevent the semiconductor region 9 and the p ⁺ type semiconductor region 12) from overlapping with each other.

When the local wirings L ₁ and L ₂ are formed by silicidation reaction, the polycrystalline silicon film 38 deposited on the Co film 37 is deposited thicker than necessary for the silicidation reaction. An unreacted polycrystalline silicon film may be left on the cobalt silicide layer. Alternatively, a refractory metal film or a refractory metal silicide film may be further deposited on the polycrystalline silicon film 38. In this case, as shown in FIG. 40, the thickness of the local wirings L ₁ and L ₂ is larger than that of the cobalt silicide layer alone, so that the surface area is increased. As a result, the capacitance (C ₂ ) formed between the local wirings L ₁ and L ₂ and the upper reference voltage line 20 can be increased. Soft error tolerance can be improved.

In this case, as shown in FIG. 40, the cobalt silicide layer 16 formed on the surface of the drain region (n ⁺ type semiconductor region 9) of the transfer MISFETs Qt ₁ and Qt ₂ and the load MISFETs Qp ₁ and Qp ₂ An unreacted polycrystalline silicon film also remains on the cobalt silicide layer 17 formed on the surface of the source region (p ⁺ type semiconductor region 12). As a result, it is not necessary to form the pad layers 22 and 24 with a polycrystalline silicon film in the same layer as the reference voltage line 20 on the cobalt silicide layers 16 and 17, and the polycrystalline silicon film is patterned to reference voltage line 20. Since the mask alignment margin when forming the memory cell becomes unnecessary, the area of the memory cell can be reduced. Further, when the pad layers 22 and 24 in the same layer as the reference voltage line 20 are not required, the area occupied by the reference voltage line 20 can be increased as shown in FIG. 41, so that the storage node capacity of the memory cell is further increased. It can be increased to improve the resistance to α-ray soft errors.

In the above embodiment, the capacitance (C) is formed between the local wirings L ₁ and L ₂ and the reference voltage line 20 in the upper layer. However, as shown in FIG. an enlarged area of the pad layer 24 for the supply voltage supply formed by the crystalline silicon film is disposed so as to cover the local wiring L _1, L _2, between the pad layer 24 and the local wiring L _1, L ₂ Capacitance may be formed between them. In this case, the reference voltage line 20 is left only in the upper layer of the source region (n ⁺ type semiconductor region 9) of the driving MISFETs Qd ₁ and Qd ₂ .

SRAM memory cell of the embodiment, transfer MISFET Qt _1, Qt driving MISFET Qd ₁ and the gate electrode 6 (word line WL) of _2, Qd ₂ and load MISFET Qp _1, Qp ₂ of the gate electrode 10a, and 10b The gate electrode 6 (word line WL) is composed of a polycrystalline silicon film in the same layer as the gate electrode 10a, 10b (for example, a polycrystalline silicon film in the same layer as the reference voltage line 20). You may comprise. In this case, as shown in FIG. 43, the gate electrode 6 (word line WL) and the gate electrodes 10a and 10b can be arranged so as to partially overlap each other. An SRAM can be highly integrated.

  The present invention is used for a nonvolatile semiconductor memory device having a memory cell having a charge storage layer formed of a silicon nitride film.

It is a top view which shows the memory cell of SRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate in the II-II 'line | wire of FIG. FIG. 3 is an equivalent circuit diagram of an SRAM memory cell according to the present invention. It is a top view which shows the overlap of the local wiring and gate electrode of the memory cell of SRAM of this invention. It is a top view which shows the overlap with the local wiring and storage node of the memory cell of SRAM of this invention. It is a top view which shows the overlap of the local wiring of the memory cell of SRAM of this invention, and a reference voltage line. It is a perspective view which shows the overlap of the local wiring and reference voltage line of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is a top view which shows the active region of the memory cell of SRAM of this invention. It is a top view which shows the active region pattern for 16 memory cells of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is a top view which shows the gate electrode (word line) pattern for 16 memory cells of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is a top view which shows the local wiring pattern for 16 memory cells of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is a top view which shows the reference voltage line pattern for 16 memory cells of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the memory cell of SRAM of this invention. It is a top view which shows the data line pattern for 16 memory cells of SRAM of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the other manufacturing method of the memory cell of SRAM of this invention. It is a principal part top view of the semiconductor substrate which shows the other structure of the memory cell of SRAM of this invention. It is a principal part top view of the semiconductor substrate which shows the other structure of the memory cell of SRAM of this invention. It is a principal part top view of the semiconductor substrate which shows the other structure of the memory cell of SRAM of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Field insulating film 3 P type well 4 N type well 5 Epitaxial silicon layer 6a, 6b Gate electrode 7 Gate insulating film 8 n ⁻ type semiconductor region 9 n ⁺ type semiconductor region 10a, 10b Gate electrode 11 p ⁻ type semiconductor Region 12 p ⁺ type semiconductor region 13 Insulating film 14 Side wall insulating film (side wall spacer)
15 connection hole 16 cobalt silicide layer 17 cobalt silicide layer 18 n ⁺ type semiconductor region 19 insulating film 20 reference voltage line 21 connection hole 22 pad layer 23 connection hole 24 pad layer 25 connection hole 26 interlayer insulation film 27 power supply voltage line 28 sub-reference Voltage line 29 Sub word line 30 Pad layer 31 Connection hole 32 Connection hole 33 Connection hole 34 Interlayer insulating film 34a Silicon oxide film 34b Spin-on glass film 34c Silicon oxide film 35 Connection hole 36 Polycrystalline silicon film 36 'Cobalt silicide layer 37 Co film 38 Polycrystalline silicon film 39 Photoresist AR Active region DL Data line bar DL Data line Qd ₁ MISFET for driving
Qd ₂ drive MISFET
Qp ₁ load MISFET
Qp ₂ load MISFET
Qt ₁ transfer MISFET
Qt ₂ transfer MISFET
WL Word line

Claims (6)

A semiconductor substrate having a main surface;
A first conductivity type well region formed in the semiconductor substrate;
An active region on the well region and formed in the main surface;
A first insulating film surrounding the active region;
A gate electrode of a MISFET formed on the active region;
A first semiconductor region of the second conductivity type formed in the well region, the active region;
A second semiconductor region of the first conductivity type formed in the well region, the active region;
A silicide layer formed on the first semiconductor region and the second semiconductor region;
A second insulating film formed on the main surface and the MISFET and having a connection hole on the first semiconductor region and the second semiconductor region;
A conductive layer formed in the connection hole and formed on the first semiconductor region and the second semiconductor region;
Including
The semiconductor integrated circuit device, wherein the first semiconductor region is a source region of the MISFET. A semiconductor substrate having a main surface;
A first conductivity type well region formed in the semiconductor substrate;
An active region on the well region and formed in the main surface;
A first insulating film surrounding the active region;
A gate electrode of a MISFET formed on the active region;
A first semiconductor region of the second conductivity type formed in the well region, the active region;
A second semiconductor region of the first conductivity type formed in the well region, the active region;
A silicide layer formed on the first semiconductor region and the second semiconductor region;
Including
The semiconductor integrated circuit device, wherein the first semiconductor region is a source region of the MISFET. The semiconductor integrated circuit device according to claim 1 or 2,
The semiconductor integrated circuit device, wherein the MISFET constitutes a load MISFET of an SRAM memory cell. The semiconductor integrated circuit device according to claim 1 or 2,
The semiconductor integrated circuit device, wherein the first semiconductor region and the second semiconductor region are disposed adjacent to each other. The semiconductor integrated circuit device according to claim 1 or 2,
The first semiconductor region and the second semiconductor region are disposed adjacent to each other in the first direction,
A first wiring extending in a second direction intersecting the first direction is formed on the conductive layer;
The semiconductor integrated circuit device, wherein the first wiring is electrically connected to the first semiconductor region and the second semiconductor region through the conductive layer and the silicide layer. The semiconductor integrated circuit device according to claim 5.
The MISFET constitutes a load MISFET of an SRAM memory cell,
The memory cell has a driving MISFET,
The driving MISFET and the load MISFET are spaced apart in the first direction,
A second wiring extending in the second direction is formed on the conductive layer;
The semiconductor integrated circuit device, wherein the second wiring and the first wiring are formed in the same layer.

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