JP2007257169A - Access control method and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the speed of access to a CPU and to reduce the power consumed by the CPU, relating to an access control method and an information processor. <P>SOLUTION: The access control method for controlling access from the outside to the CPU including a bus, a core block and a bus bridge block and being in a sleep state includes holding the core block in a sleep state according to a bus request from the outside, releasing the bus bridge block from the sleep state, and issuing a bus grant to give the right of using the bus to the outside according to the bus request. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an access control method and an information processing apparatus, and more particularly to an access control method for accessing a CPU in a sleep state from an external device and an information processing apparatus using such an access control method.

  As an operation state (or operation mode) for reducing power consumption, the CPU stops the clock supplied to the CPU, decreases the clock frequency, or decreases the voltage supplied to the CPU. A sleep state (or sleep mode).

  When the CPU is in a sleep state, an external device connected to the CPU via a general-purpose local bus becomes an external bus master. When performing read or write access to the CPU from the external bus master, it is necessary to first transfer the data after interrupting the CPU to cancel the CPU sleep state.

  For example, when a CPU includes a core block and a bus bridge block and the CPU is in a sleep state, data is accessed by accessing an SDRAM connected to the CPU SDRAM bus from an external bus master connected to the CPU via a general-purpose local bus. Procedures P1 to P5 for transferring are as follows.

  P1: An interrupt is generated from the external bus master to the CPU via the general-purpose local bus.

  P2: Releases the sleep state of the core block and the bus bridge block in the CPU in response to the interrupt.

  P3: A bus request is issued from the external bus master to the CPU via the general-purpose local bus.

  P4: A bus grant signal giving the right to use the SDRAM bus is issued from the core block in the CPU to the external bus master via the bus bridge and the general-purpose local bus.

  P5: If it is a write access, data is transferred from the external bus master to the SDRAM via the general-purpose local bus and the bus bridge in the CPU in response to the bus grant signal.

For example, Patent Literature 1 and Patent Literature 2 have proposed a method for putting a CPU in a sleep state from the outside.
JP-A-9-274798 JP-A-7-295694

  Conventionally, in order to access a CPU in a sleep state from an external bus master, it is necessary to first issue an interrupt to the CPU from the external bus master to cancel the sleep state of the CPU and then issue a bus request from the external bus master to the CPU. there were. Therefore, in order to cancel the CPU sleep state, it is necessary to generate a dedicated interrupt from the external bus master, and it is difficult to improve the access speed to the CPU. Further, when an interrupt from the external bus master to the CPU occurs, the CPU is released from the sleep state regardless of the type of access, so that it is difficult to reduce the power consumption of the CPU.

  Therefore, an object of the present invention is to provide an access control method and an information processing apparatus capable of improving the access speed to the CPU and reducing the power consumption of the CPU.

  The above problem is an access control method for controlling an external access to a CPU including a bus, a core block, and a bus bridge block, and the core block is controlled based on the external bus request. According to an access control method, wherein the bus bridge block is released from the sleep state, and a bus grant that gives the right to use the bus to the outside is issued based on the bus request. Can be achieved.

  The above-described problem includes a CPU including a core block and a bus bridge block and having a sleep state, and a bus connected to the bus ridge block. The bus bridge block is based on a bus request from the outside. Control means for releasing the bus bridge block from the sleep state and issuing a bus grant that gives the right to use the bus to the outside based on the bus request. This can also be achieved by an information processing apparatus.

  ADVANTAGE OF THE INVENTION According to this invention, the access control method and information processing apparatus which can improve the access speed to CPU and can reduce the power consumption of CPU are realizable.

  In the present invention, when the CPU includes a core block and a bus bridge block, and the CPU is in a sleep state, the CPU is connected to the main memory bus of the CPU from an external bus master connected to the CPU via a general-purpose local bus, for example. The procedures P11 to P14 for transferring data by accessing the main storage unit are as follows.

  P11: A bus request is issued from the external bus master to the bus bridge block in the CPU via the general-purpose local bus.

  P12: The sleep state of the bus bridge block in the CPU is canceled in response to the bus request.

  P13: A bus grant signal that gives the right to use the main memory bus is issued from the bus bridge block in the CPU to the external bus master via the general-purpose local bus.

  P14: For example, in the case of write access, data is transferred from the external bus master to the main memory in response to the bus grant signal via the general-purpose local bus and the bus bridge block in the CPU.

  In order to cancel the sleep state of the CPU, it is not necessary to generate a dedicated interrupt from the external bus master, and the bus request is used, so that the access speed to the CPU can be improved. Also, since the bus request is issued from the external bus master to the bus bridge block in the CPU, the sleep state of only the bus bridge can be released while keeping the sleep state of the core block, thus reducing the power consumption of the CPU. be able to. For example, depending on the access destination and the type of access, a specific block in the CPU and / or a specific block externally connected to the CPU is released from the sleep state and externally connected to another block in the CPU and the CPU. Other blocks can be kept in sleep.

  Embodiments of an access control method and an information processing apparatus according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of an information processing apparatus of the present invention. This embodiment of the information processing apparatus uses an embodiment of the access control method of the present invention.

  The information processing apparatus 1 shown in FIG. 1 includes a CPU 11, a general-purpose local bus 12, an SDRAM 13 constituting a main storage unit, and a high-speed bus 14 for SDRAM (for main storage unit). The CPU 11 includes a block unit 111 and a bus bridge block 112. The block unit 111 in the CPU 11 includes a core block 51 including main parts such as an arithmetic processing unit of the CPU 11 and another block 52. The other block 52 includes an input / output (I / O) block and the like. In FIG. 1, the other block 52 is provided in the CPU 11, but it may be externally connected to the CPU 11 like the SDRAM 13. The bus bridge block 112 is connected to the SDRAM 13 via the SDRAM high-speed bus 14. An external device 31 is connected to the general-purpose local bus 12 to which the bus bridge block 112 is connected.

  The CPU 11 and the externally connected block such as the SDRAM 13 can stop the clock supplied to the CPU 11 or reduce the clock frequency as an operation state (or operation mode) for reducing power consumption. It has a sleep state (or sleep mode) in which the voltage supplied to the CPU 11 is reduced.

  The external device 31 includes at least a CPU having a function of controlling data transfer. The external device 31 performs data transfer by operating as an external bus master when the CPU 11 is in a sleep state.

  When the CPU 11 is in the sleep state, for example, steps S1 to S4 when data is transferred by accessing the SDRAM 13 connected to the SDRAM bus 14 of the CPU 11 from the external device 31 connected to the CPU 11 by the general-purpose local bus 12 It becomes as follows.

  S1: A bus request signal is issued from the external device 31 to the bus bridge block 112 in the CPU 11 via the general-purpose local bus 12.

  S2: The sleep state of the bus bridge block 112 in the CPU 11 is canceled in response to the bus request signal, and the block unit 111 in the CPU 11 is kept in the sleep state.

  S3: A bus grant signal that gives the right to use the SDRAM high-speed bus 14 is issued from the bus bridge block 112 in the CPU 11 to the external device 31 via the general-purpose local bus 12.

  S4: If it is a write access, data is transferred from the external device 31 to the SDRAM 13 via the general-purpose local bus 12 and the bus bridge block 112 in the CPU 11 in response to the bus grant signal, and written to the SDRAM 13. On the other hand, in the case of read access, data read from the SDRAM 13 in response to the bus grant signal is transferred to the external device 31 via the bus bridge block 112 and the general-purpose local bus 12 in the CPU 11.

  In order to cancel the sleep state of the CPU 11, it is not necessary to generate a dedicated interrupt from the external device 31, and the bus request signal is used, so that the access speed to the CPU 11 can be improved. Since the bus request signal is issued from the external device 31 to the bus bridge block 112 in the CPU 11, the sleep state of the block unit 111 can be maintained and the sleep state of only the bus bridge block 112 can be canceled. Power consumption can be reduced. For example, depending on the access destination and the type of access, the sleep state of only a specific block externally connected to the CPU 11 and / or the CPU 11 is canceled, and the other blocks externally connected to the CPU 11 and / or the CPU 11 are in the sleep state. Can also be kept.

  FIG. 2 is a diagram for explaining the operation of the bus bridge block 112. As shown in FIG. 2, the bus bridge block 112 includes a data control unit 61 and a control information processing unit 62.

  The data control unit 61 has a terminal 71 connected to the data bus 121 of the general-purpose local bus 12, exchanges data in the information processing apparatus 1, and exchanges data between the information processing apparatus 1 and the external device 31. Control the exchange. The data bus 121 is composed of a plurality of bits. The data control unit 61 is connected to another block such as an I / O block externally connected to the SDRAM 13 and the CPU 11 and to another block 52 such as a core block 51 and an I / O block in the CPU 11.

  The control information processing unit 62 has terminals 72A to 72C connected to the control bus 122 of the general-purpose local bus 12, and responds to the control of the sleep state of each block in the information processing apparatus 1 and the bus request signal. It is responsible for issuing bus grant signals. The control bus 122 is composed of a plurality of bits. The terminal 72A receives a bus request signal composed of a plurality of bits issued by the external device 31. The terminal 72B outputs a bus grant signal composed of a plurality of bits issued by the control information processing unit 62 to the external device 31. The terminal 72C receives an interrupt signal composed of a plurality of bits generated by the external device 31. The control information processing unit 62 generates a control signal for controlling the sleep state of each block including the bus bridge block 112 in the information processing apparatus 1 based on the bus request signal, and supplies the control signal to the corresponding block. Which block in the information processing apparatus 1 is held in the sleep state and which block is released from the sleep state may be determined in advance according to the access destination and the type of access. Since the control information processing unit 62 is connected to other blocks such as I / O blocks externally connected to the SDRAM 13 and the CPU 11 and other blocks 52 such as the core block 51 and the I / O block in the CPU 11. Control signals are supplied to these blocks.

  Since the bus request signal received by the terminal 72A consists of a plurality of bits, it can indicate the access destination block and the type of access. The control information processing unit 62, based on the access destination and type of access indicated by the bus request signal, is a bus grant signal composed of a plurality of bits that gives the right to use the corresponding bus (for example, the high-speed bus 14) in the information processing apparatus 1. Is output to the external device 31 via the terminal 72B. The access destination and access type indicated by the bus request signal are, for example, SDRAM 13 and write access. In this case, the bus grant signal issued by the control information processing unit 62 gives the external device 31 the right to use the high-speed bus 14. Data can be written from the external device 31 to the SDRAM 13. In this case, the control signal generated by the control information processing unit 62 releases the sleep state of only the bus bridge block 112, for example, and holds the core block 51 and the other blocks 52 in the sleep state.

  In the sleep state, a plurality of run levels may be provided. Between different run levels, the blocks in the information processing apparatus 1 that are the sleep targets are different and / or the power consumption of the information processing apparatus 1 (the sum of all blocks) is different.

  When a plurality of run levels are provided in the sleep state, the run level of each block in the information processing apparatus 1 is also controlled by a control signal generated by the control information processing unit 62. In this case, which block in the information processing apparatus 1 is controlled to which run level in the sleep state and which block is released from the sleep state is determined in advance according to the access destination and the type of access. Information indicating which block is controlled to which run level in the sleep state according to the access destination and the type of access may be stored in a table (not shown) in the control information processing unit 62 in advance, for example. It may be set in a run level setting register (not shown) in the processing unit 62. The control information processing unit 62 independently reads the sleep state and run level of each block in the information processing device 1 by reading the table or the run level setting register based on the access destination and the access type indicated by the bus request signal. A control signal composed of a plurality of bits to be controlled is generated.

  The control information processing unit 62 may use the bus request signal to generate a control signal that controls only the retention and release of the sleep state of each block in the information processing apparatus 1. In this case, the control information processing unit 62 generates another control signal for controlling the run level in the sleep state of each block in the information processing apparatus 1 based on, for example, an interrupt signal composed of a plurality of bits issued by the external device 31. To do.

  Therefore, according to this embodiment, the sleep state of the CPU is not canceled by an interrupt, but the sleep state is canceled by a bus request signal, so that the CPU response is improved. Further, in response to the bus request signal, for example, only the bus bridge block in the CPU is released from the sleep state, so that an information processing apparatus with low power consumption can be configured. This embodiment is particularly suitable for an information processing apparatus having a configuration in which an internal bus in the information processing apparatus and a general-purpose local bus connected to an external device are separated.

In addition, this invention also includes the invention attached to the following.
(Supplementary Note 1) An access control method for controlling external access to a CPU that is in a sleep state including a bus, a core block, and a bus bridge block,
Based on the external bus request, the core block is held in the sleep state and the bus bridge block is released from the sleep state,
An access control method characterized by issuing a bus grant that gives a right to use the bus to the outside based on the bus request.
(Supplementary note 2) The access control method according to supplementary note 1, wherein the bus is connected to a main storage unit of the CPU.
(Supplementary Note 3) The access control method according to Supplementary Note 1 or 2, wherein the sleep state of the CPU and / or another block externally connected to the CPU is held or canceled based on the bus request. .
(Additional remark 4) The block which becomes the object of sleep differs between different run levels, and / or the total power consumption of all the blocks differs, It is characterized by controlling the run level of the sleep state of each block, The access control method according to any one of appendices 1 to 3.
(Supplementary note 5) The access control method according to supplementary note 4, wherein a sleep state and a run level of each block are controlled based on an access destination and an access type included in the bus request.
(Supplementary note 6) The access control method according to supplementary note 4, wherein the run level in the sleep state of each block is controlled based on an external interrupt.
(Appendix 7) A CPU including a core block and a bus bridge block and having a sleep state;
A bus connected to the bass ridge block,
The bus bridge block holds the core block in a sleep state based on a bus request from the outside and releases the bus bridge block from the sleep state. The bus bridge block sends the bus block to the outside based on the bus request. An information processing apparatus comprising control means for issuing a bus grant that gives a right to use the information.
(Supplementary note 8) The information processing apparatus according to supplementary note 7, further comprising a main storage unit of the CPU connected to the bus.
(Additional remark 9) The said CPU is further equipped with the other block externally connected to this CPU, and / or
The information processing apparatus according to appendix 8, wherein the control means holds or cancels the sleep state of the other block based on the bus request.
(Supplementary Note 10) Blocks subject to sleep are different between different run levels and / or the total power consumption of all blocks is different.
The information processing apparatus according to any one of appendices 7 to 9, wherein the control unit controls a run level in a sleep state of each block.
(Supplementary note 11) The information processing apparatus according to supplementary note 10, wherein the control unit controls a sleep state and a run level of each block based on an access destination and an access type included in the bus request.
(Supplementary note 12) The information processing apparatus according to supplementary note 10, wherein the control unit controls the run level of each block in a sleep state based on an external interrupt.

  While the present invention has been described with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made within the scope of the present invention.

It is a block diagram which shows one Example of the information processing apparatus of this invention. It is a figure explaining operation | movement of a bus bridge block.

Explanation of symbols

1 Information processing apparatus 11 CPU
12 General-purpose local bus 13 SDRAM
14 SDRAM High-Speed Bus 31 External Device 51 Core Block 52 Other Block 61 Data Control Unit 62 Control Information Processing Unit 111 Block Unit 112 Bus Bridge Block

Claims (5)

An access control method for controlling external access to a CPU in a sleep state including a bus, a core block, and a bus bridge block,
Based on the external bus request, the core block is held in the sleep state and the bus bridge block is released from the sleep state,
An access control method characterized by issuing a bus grant that gives a right to use the bus to the outside based on the bus request.   The access control method according to claim 1, wherein the run level in the sleep state of each block is controlled. A CPU having a sleep state including a core block and a bus bridge block;
A bus connected to the bass ridge block,
The bus bridge block holds the core block in a sleep state based on a bus request from the outside and releases the bus bridge block from the sleep state. The bus bridge block sends the bus block to the outside based on the bus request. An information processing apparatus comprising control means for issuing a bus grant that gives a right to use the information. Blocks that are subject to sleep are different between different run levels and / or the total power consumption of all blocks is different,
The information processing apparatus according to claim 3, wherein the control unit controls a run level in a sleep state of each block.   The information processing apparatus according to claim 4, wherein the control unit controls the sleep state and the run level of each block based on an access destination and an access type included in the bus request.

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