JP2007251456A - Electronic camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic camera for suppressing a memory capacity required for converting pixel arrangement. <P>SOLUTION: A TG/SG 18 reads electric charges generated by an imaging plane 14f with 128 horizontal pixels by one horizontal pixel line each. A horizontal rearrangement circuit 24 converts the arrangement of pixel data based on read electric charges by using a built-in line memory. The line memory has 128 storage areas each storing pixel data of one pixel. Further, the TG/SG 18 designates 128 pixels belonging to a target horizontal pixel line by 4 cycles at a rate of one pixel per four consecutive pixels. The horizontal rearrangement circuit 24 reads pixel data by 8 pixels each in the order along with the pixel arrangement in the target horizontal pixel line. Further, the horizontal rearrangement circuit 24 writes the pixel data of 8 pixels on the basis of electric charges read by the TG/SG 18 associated with update of the target horizontal pixel line to 8 storage areas corresponding to the read pixel data of the 8 pixels. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic camera, and more particularly to an electronic camera that converts, for example, a pixel array of image data based on charges read from an imaging surface using a memory.

An example of a conventional camera of this type is disclosed in Patent Document 1. According to this prior art, the charge representing the object scene is read from the imaging surface in an interlaced scanning manner. A pixel array of image data based on the read charges is converted into a progressive scan mode using SDRAM.
JP 2004-282331 A [H04N 1/21, 5/225, 5/232, 5/907]

    However, while the conventional technology assumes conversion of a pixel array focusing on the scanning mode, it does not assume any conversion of a pixel array belonging to a pixel line along the scanning direction. In the prior art, a memory capacity corresponding to one frame is required for array conversion.

    Therefore, a main object of the present invention is to provide an electronic camera capable of converting a pixel arrangement in one pixel line along the scanning direction while suppressing a memory capacity.

  An electronic camera (10) according to the invention of claim 1 includes an image pickup means (14) having an image pickup surface (14f) in which a plurality of pixels for generating electric charges are two-dimensionally arranged, and one pixel of electric charge generated on the image pickup surface. Charge reading means (18) for reading line by line, data writing means (24w) for writing pixel data based on the charges read by the charge reading means to the memory (24m), and pixel data written by the data writing means from the memory A data reading means (24r) for reading is provided, the memory has a plurality of storage areas each storing pixel data of one pixel, and the charge reading means has a plurality of pixels belonging to the target pixel line as one continuous M pixel. The ratio is specified over M cycles (M: an integer of 2 or more), and the data readout means sets the pixel data to M * N pixels (N: 1 in the order along the pixel arrangement in the target pixel line). The data writing means reads M * N pixel data read by the data reading means based on the charges read by the charge reading means in association with the update of the pixel line of interest. Write to M * N storage areas corresponding to the pixel data of the pixel.

  The imaging means has an imaging surface on which a plurality of pixels that generate charges are two-dimensionally arranged. The charges generated on the imaging surface are read out one pixel line at a time by the charge reading means. The data writing means writes pixel data based on the charges read by the charge reading means to the memory, and the data reading means reads the pixel data written by the data writing means from the memory.

  Here, the memory has a plurality of storage areas each storing pixel data of one pixel. The charge reading means designates a plurality of pixels belonging to the target pixel line at a ratio of one pixel to consecutive M pixels over M cycles (M: an integer of 2 or more). Further, the data reading means reads pixel data by M * N pixels (N: integer of 1 or more) in order along the pixel arrangement in the target pixel line. Further, the data writing means outputs the pixel data of the M * N pixels based on the charges read by the charge reading means in association with the update of the target pixel line, and the pixels of the M * N pixels read by the data reading means. Write to M * N storage areas corresponding to the data.

  A plurality of pixels belonging to each pixel line is designated at a ratio of one pixel to consecutive M pixels. For this reason, when a plurality of pixels continuous on the pixel line are considered as a set of a plurality of units each having M * N pixels, the pixel arrangement pattern on the memory is common among the plurality of units.

  One unit of pixel data obtained in connection with the update of the target pixel line is written in a storage area corresponding to one unit corresponding to the pixel data of one unit that has been read in consideration of such characteristics. Thereby, the pixel arrangement in one pixel line along the scanning direction can be converted while suppressing the memory capacity.

  The electronic camera according to a second aspect of the present invention is dependent on the first aspect, and the number of storage areas of the memory is equal to or greater than the number of pixels belonging to one pixel line. Thereby, pixel data corresponding to one pixel line is reliably held in the memory.

  The electronic camera according to the invention of claim 3 is dependent on claim 1 or 2, and the numerical value indicated by N is calculated based on the number of storage areas of the memory, the number of write patterns of the data writing means, and the numerical value indicated by M. Is done.

The electronic camera according to the invention of claim 4 is dependent on claim 3, wherein when the number of storage areas of the memory is ST and the number of write patterns of the writing means is K, the numerical value indicated by N is ST / M ^K Is equal to the number indicated by

  An electronic camera according to a fifth aspect of the invention is dependent on any one of the first to fourth aspects, and the memory has a data input port and a data output port separately.

  According to the present invention, the plurality of pixels belonging to each pixel line is designated at a rate of one pixel for consecutive M pixels. For this reason, when a plurality of pixels continuous on the pixel line are considered as a set of a plurality of units each having M * N pixels, the pixel arrangement pattern on the memory is common among the plurality of units.

  One unit of pixel data obtained in connection with the update of the target pixel line is written in a storage area corresponding to one unit corresponding to the pixel data of one unit that has been read in consideration of such characteristics. Thereby, the pixel arrangement in one pixel line along the scanning direction can be converted while suppressing the memory capacity.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

  Referring to FIG. 1, a digital camera (electronic camera) 10 of this embodiment includes an optical lens 12. An optical image representing the object scene is irradiated on the imaging surface 14 f of the image sensor 14 through the optical lens 12. The imaging surface 14f is covered with a color filter (not shown) having a primary color Bayer array. The plurality of filter elements constituting the color filter respectively correspond to the plurality of light receiving elements forming the imaging surface. Accordingly, the amount of charge generated in each light receiving element reflects one of the light amounts of R (Red), G (Green), and B (Blue). The light receiving element may be defined as “pixel”.

  When the power is turned on, the CPU 36 gives a corresponding command to the TG / SG 18 in order to read out the electric charge generated on the imaging surface 14f in a thinning manner. The CPU 36 further connects the switches SW1 and SW2 to the terminals T1 and T3, respectively, and activates the video encoder 46.

  The TG / SG 18 generates a vertical synchronization signal Vsync every 1/30 seconds, and provides a plurality of timing signals synchronized with the vertical synchronization signal Vsync to each of the image sensor 14 and the CDS / AGC / AD circuit 16. The imaging surface 14f is subjected to pre-exposure every time the vertical synchronizing signal Vsync is generated, and the charges generated thereby are subjected to thinning-out reading by raster scanning. The low-resolution raw image signal formed by the read charges has a frame rate of 30 fps.

  The CDS / AGC / AD circuit 16 performs a series of processes of correlated double sampling, automatic gain adjustment, and A / D conversion on the raw image signal output from the image sensor 14, and outputs raw image data that is a digital signal. . The raw image data output from the CDS / AGC / AD circuit 16 is given to the signal processing circuit 20 via the switches SW1 and SW2.

  The signal processing circuit 20 performs processing such as white balance adjustment, color separation, and YUV conversion on the given raw image data. The image data in the YUV format thus generated is given to the memory control circuit 40 through the buffer circuit 22 and the bus B1, and is written into the SDRAM 42 by the memory control circuit 40.

  The video encoder 46 reads out the image data thus stored in the SDRAM 42 through the memory control circuit 40. The read image data is supplied to the video encoder 46 through the bus B1 and the buffer circuit 44, and converted into an NTSC composite video signal. The converted composite video signal is applied to the LCD monitor 48. As a result, a through image representing the scene is reproduced on the screen.

  When a recording operation is performed by the key input device 38, the CPU 36 connects the switches SW1 and SW2 to the terminals T2 and T4, respectively. In response to the generation of the vertical synchronization signal Vsync, the CPU 36 instructs the TG / SG 18 to read all the charges generated on the imaging surface 14f. The TG / SG 18 performs the main exposure on the image sensor 18 and reads out all the charges generated on the image pickup surface 14f by taking four field periods (= 1/30 seconds * 4). In the first field period, the 4m-3th (m: 1, 2, 3,...) Horizontal pixel line is a readout target, and in the second field, the 4m-2th horizontal pixel line is a readout target. In the third field period, the 4m-1 horizontal pixel line is a readout target, and in the fourth field, the 4mth horizontal pixel line is a readout target. The reading of charges is interrupted when the four field period elapses.

  However, the reading order in the horizontal direction is different from the arrangement order of the pixels belonging to the horizontal pixel line. That is, the charge generated in each horizontal pixel line is read out over four cycles at a rate of one pixel per four consecutive pixels. 2 to 3, when each horizontal pixel line is considered as a set of pixel blocks formed by continuous four pixels, first the leftmost pixel of each pixel block is to be read, and then each pixel The second pixel from the right of the block is the readout target. Subsequently, the second pixel from the left of each pixel block is to be read, and then the rightmost pixel of each pixel block is to be read.

  Accordingly, assuming that the number of pixels belonging to each horizontal pixel line is “128”, and consecutive identification numbers are assigned to these pixels in the manner of “1”, “2”, “3”,. The identification number of the pixel to be read changes first in the order of “1” → “5” → “9” → “13” →... “121” → “125”, and then “3” → “7”. → "11" → "15" → ... "123" → "127" in this order, "2" → "6" → "10" → "14" → ... "122" → "126" And “4” → “8” → “12” → “16” →... “124” → “128”.

  The raw image signal of each field output from the image sensor 14 is subjected to the same processing as described above by the CDS / AGC / AD circuit 16 and converted into raw image data. The converted raw image data is given to the horizontal rearrangement circuit 24 through the switch SW1. The horizontal rearrangement circuit 24 performs an array conversion process on the pixel data of each horizontal pixel line forming the raw image data. The identification number of the pixel data having the converted pixel array changes in the order of “1” → “2” → “3”... “126” → “127” → “128”. The raw image data output from the horizontal rearrangement circuit 24 is written into the SDRAM 44 via the buffer circuit 26, the bus B1, and the memory control circuit 42.

  Subsequently, the CPU 36 gives an instruction to the signal processing circuit 20, the JPEG encoder 32, and the I / F 50 in order to perform recording processing on the high-resolution raw image data stored in the SDRAM 42. The signal processing circuit 20 reads the raw image data stored in the SDRAM 42 through the memory control circuit 40 in a progressive scanning manner. The read raw image data is given to the signal processing circuit 20 via the bus B1, the buffer circuit 28, and the switch SW2, and is converted into YUV format image data. The converted image data is given to the memory control circuit 40 via the buffer circuit 22 and the bus B1, and is written into the SDRAM 42 by the memory control circuit 40.

  The JPEG encoder 32 reads out the image data stored in the SDRAM 42 through the memory control circuit 40. The read image data is given to the JPEG encoder 32 via the bus B1 and the buffer circuit 30, and subjected to JPEG compression. The compressed image data generated thereby is given to the memory control circuit 40 through the buffer circuit 34 and the bus B1, and is written in the SDRAM 42 thereby. The I / F 50 reads the compressed image data stored in the SDRAM 42 through the memory control circuit 40 and records the read compressed image data on the recording medium 52 in a file format.

  Referring to FIG. 4, the horizontal rearrangement circuit 24 is formed by a dual port type line memory 24m, a write controller 24w, and a read controller 24r. The line memory 24m has 128 storage areas each storing pixel data of one pixel. Physical addresses “1” to “128” are assigned to the 128 storage areas, respectively. Pixel data is input from the data input port P1 and output from the data output port P2.

  Each of the write controller 24w and the read controller 24r divides the 128 storage areas provided in the line memory 24m into four area groups as shown in FIG. 5, FIG. 8, or FIG. Assign virtually. The numerical value “4” indicating the number of area groups coincides with the number of pixels forming the pixel block shown in FIGS.

  5, 8 or 11, the X address “1” is commonly assigned to the physical addresses “1” to “32”, and the X address “2” is assigned to the physical addresses “33” to “64”. Commonly assigned. The X address “3” is commonly assigned to the physical addresses “65” to “96”, and the X address “4” is commonly assigned to the physical addresses “97” to “128”.

  Y addresses “1” to “32” are assigned to physical addresses “1” to “32”, respectively, are assigned to physical addresses “33” to “64”, and physical addresses “65” to “96” are assigned. And physical addresses “97” to “128”, respectively.

  Among the plurality of horizontal pixel lines forming the raw image data output from the CDS / AGC / AD circuit 16, the 3n-2nd (n: 1, 2, 3,...) Horizontal pixel line is as shown in FIG. Is written in the line memory 24m, the 3n-1 horizontal pixel line is written in the line memory 24m as shown in FIG. 8, and the 3n-th horizontal pixel line is written in the line memory 24m as shown in FIG. .

  The 3n-2nd horizontal pixel line is read from the line memory 24m as shown in FIGS. 6A to 6H and FIGS. 7A to 7H, and the 3n-1th horizontal pixel line is read out. The horizontal pixel lines are read from the line memory 24m in the manner shown in FIGS. 9A to 9H and FIGS. 10A to 10H, and the 3n-th horizontal pixel line is shown in FIG. The data is read from the line memory 24m in the manner shown in (A) to FIG. 12 (H) and FIG. 13 (A) to FIG.

  Here, the access operation of the 3n-2nd horizontal pixel line corresponds to "Phase 1", the access operation of the 3n-1st horizontal pixel line corresponds to "Phase 2", and the 3nth horizontal pixel line The access operation corresponds to “Phase 3”. The phase may be defined as “pattern”.

The number of read pixels per time from the line memory 24m is common between the phases 1 to 3. The number of read pixels is obtained by the calculations of Equations 1 to 2.
[Equation 1]
N = ST / M ^K
M: number of cycles required to read out one horizontal pixel line or number of pixels forming a pixel block (= 4)
K: Number of phases (= 3)
ST: Number of storage areas or number of pixels belonging to each horizontal pixel line (= 128)
N: Pixel number coefficient [Formula 2]
PX = M * N
PX: Number of readout pixels per time According to the number 1, a constant M indicating the number of cycles required for reading one horizontal pixel line (or the number of pixels forming a pixel block) is raised to a constant K indicating the number of phases. The A constant ST indicating the number of storage areas provided in the line memory 24m (or the number of pixels belonging to each horizontal pixel line) is divided by a power value, whereby a pixel number coefficient N is obtained. In this embodiment, the constants M, K, and ST are “4”, “3”, and “128”, respectively. For this reason, the pixel number coefficient N is “2”.

  According to Equation 2, the constant M is multiplied by the pixel number coefficient N calculated by Equation 1. Thus, a numerical value PX indicating the number of read pixels per time is calculated. In this embodiment, the numerical value PX indicates “8”. Accordingly, in any of the phases 1 to 3, the pixel data is read from the line memory 24m by 8 pixels (that is, 8 pixels as one unit).

In phase 1, virtual write addresses Xw and Yw are calculated according to Equation 3.
[Equation 3]
Xw = int ((Hnum-1) / (ST / M)) + 1
Yw = (Hnum-1)% (ST / M) +1
Hnum: horizontal pixel identification number According to Equation 3, the constant ST is divided by the constant M in determining the write address Xw. A numerical value “Hnum−1” obtained by subtracting “1” from a numerical value Hnum indicating the identification number of the horizontal pixel is further divided by the calculated division value. The write address Xw is defined by a numerical value obtained by adding “1” to the integer part of the division value. In obtaining the write address Yw, the constant ST is divided by the constant M. The numerical value “Hnum-1” is further divided by the calculated division value. The write address Yw is defined by a numerical value obtained by adding “1” to the remainder of the division.

  “ST / M” is “32”. Therefore, if the numerical value Hnum is “38”, the write addresses Xw and Yw are “3” and “10”, respectively. If the numerical value Hnum is “83”, the write addresses Xw and Yw are “2” and “21”, respectively. As a result, the pixel data of 128 pixels belonging to the 3n-2nd horizontal pixel line is written in the line memory 24m as shown in FIG. Note that the numbers in parentheses in FIG. 5 indicate the writing order of pixel data (the same applies to FIGS. 8 and 11).

In phase 1, virtual read start addresses Xr and Yr are calculated according to Equation 4.
[Equation 4]
Xr = 1
Yr = N * Rcnt + 1
Rcnt: Read count (0 to 15)
The number of storage areas of the line memory 24m (the number of pixels belonging to one horizontal pixel line) is “128”, and the number of read pixels per time is “8”. Therefore, the pixels of 128 pixels stored in the line memory 24m. To read data, 16 read operations are required. Therefore, the variable Rcnt for counting the number of readings is cyclically updated between “0” and “15”. In phase 1, the read address Xr always indicates “1”, while the read address Yr is calculated by multiplying the pixel number coefficient N by the variable Rcnt.

  Therefore, the read start addresses Xr and Yr are (Xr, Yr) = (1,1) → (1,3) → (1,5) → (1,7) → (1,9) → (1,11 ) → (1,13) → (1,15) → (1,17) → (1,19) → (1,21) → (1,23) → (1,25) → (1,27) → It is updated in the order of (1,29) → (1,31).

  Further, the readout controller 24r uniquely determines the position and readout order of the 8 pixels of interest for one readout process in the phase 1 using the readout start addresses Xr and Yr as reference positions. As a result, the pixel data stored in the line memory 24m is changed from FIG. 6 (A) → FIG. 6 (B) → FIG. 6 (C) → FIG. 6 (D) → FIG. 6 (E) → FIG. 6 (G) → FIG. 6 (H) → FIG. 7 (A) → FIG. 7 (B) → FIG. 7 (C) → FIG. 7 (D) → FIG. 7 (E) → FIG. 7 (F) → FIG. (G) → Read in the order of FIG.

In phase 2, virtual write addresses Xw and Yw are calculated according to Equation 5.
[Equation 5]
Xw = (int ((Hnum-1) / N))% M + 1
Yw = (Hnum-1)% N + int ((Hnum-1) / PX) * N + 1
Although detailed description of the mathematical formula is omitted, if the numerical value Hnum is “47”, the write addresses Xw and Yw are “2” and “12”, respectively. If the numerical value Hnum is “92”, the write addresses Xw and Yw are “4” and “29”, respectively. As a result, the pixel data of 128 pixels belonging to the 3n-1st horizontal pixel line is written to the line memory 24m in the manner shown in FIG.

In phase 2, virtual read start addresses Xr and Yr are calculated according to Equation 6.
[Equation 6]
Xr = (Rcnt% M) * N
Yr = Rcnt% M
Therefore, the read start addresses Xr and Yr are (Xr, Yr) = (1,1) → (2,1) → (3,1) → (4,1) → (1,3) → (2,3 ) → (3,3) → (4,3) → (1,5) → (2,5) → (3,5) → (4,5) → (1,7) → (2,7) → It is updated in the order of (3, 7) → (4, 7).

  Also in the phase 2, the readout controller 24r uniquely determines the positions and readout order of the 8 pixels of interest for one readout process with the readout start addresses Xr and Yr as reference positions. As a result, the pixel data stored in the line memory 24m is as follows: FIG. 9 (A) → FIG. 9 (B) → FIG. 9 (C) → FIG. 9 (D) → FIG. 9 (E) → FIG. 9 (G) → FIG. 9 (H) → FIG. 10 (A) → FIG. 10 (B) → FIG. 10 (C) → FIG. 10 (D) → FIG. 10 (E) → FIG. 10 (F) → FIG. Data are read in the order of (G) → FIG.

In phase 3, virtual write addresses Xw and Yw are calculated according to Equation 7.
[Equation 7]
Xw = int ((Hnum-1) / PX)% M + 1
Yw = int ((((Hnum-1)% PX) / N) * PX + ((Hnum-1)% PX)% N + int ((Hnum-1) / (ST / M)) * N + 1
Therefore, if the numerical value Hnum is “52”, the write addresses Xw and Yw are “2” and “23”, respectively. If the numerical value Hnum is “111”, the write addresses Xw and Yw are “4” and “12”, respectively. As a result, the pixel data of 128 pixels belonging to the 3nth horizontal pixel line is written into the line memory 24m in the manner shown in FIG.

In phase 3, virtual read start addresses Xr and Yr are calculated according to Equation 8.
[Equation 8]
Xr = Rcnt% M * PX
Yr = int (Rcnt% M)
Therefore, the read start addresses Xr and Yr are (Xr, Yr) = (1,1) → (1,9) → (1,17) → (1,25) → (2,1) → (2,9 ) → (2,17) → (2,25) → (3,1) → (3,9) → (3,17) → (3,25) → (4,1) → (4,9) → It is updated in the order of (4, 17) → (4, 25).

  Also in the phase 3, the read controller 24r uniquely determines the position and read order of the 8 pixels of interest for one read process with the read start addresses Xr and Yr as reference positions. As a result, the pixel data stored in the line memory 24m is as shown in FIG. 12 (A) → FIG. 12 (B) → FIG. 12 (C) → FIG. 12 (D) → FIG. 12 (E) → FIG. 12 (G) → FIG. 12 (H) → FIG. 13 (A) → FIG. 13 (B) → FIG. 13 (C) → FIG. 13 (D) → FIG. 13 (E) → FIG. 13 (F) → FIG. Data are read in the order of (G) → FIG.

  As can be seen from the above description, the image sensor 14 has an imaging surface 14f in which a plurality of pixels are two-dimensionally arranged. The charges generated on the imaging surface 14f are read out by the TG / SG 18 for each horizontal pixel line. The write controller 24w writes pixel data based on the read charges to the line memory 24m, and the read controller 24r reads the pixel data stored in the line memory 24m.

  Here, the line memory 24m has 128 storage areas each storing pixel data of one pixel. The TG / SG 18 designates a plurality of pixels belonging to the target pixel line over four cycles (= M cycles) at a rate of one pixel to four consecutive pixels (= M pixels). Further, the read controller 24r reads pixel data by 8 pixels (= M * N pixels) in order along the pixel arrangement in the target pixel line. In addition, the writing controller 24w outputs the pixel data of 8 pixels (= M * N pixels) based on the charges read by the TG / SG 18 in association with the update of the target pixel line, read by the reading controller 24r. Write into 8 (= M * N) storage areas corresponding to pixel data of pixels (= M * N pixels).

  A plurality of pixels belonging to each horizontal pixel line is designated at a ratio of one pixel to consecutive M pixels. For this reason, when a plurality of pixels continuous on the horizontal pixel line is considered as a set of a plurality of units each having M * N pixels, the pixel arrangement pattern on the line memory 24m is common among the plurality of units.

  One unit of pixel data obtained in connection with the update of the target pixel line is written in a storage area corresponding to one unit corresponding to the pixel data of one unit that has been read in consideration of such characteristics. Thereby, the pixel arrangement in one pixel line along the scanning direction can be converted while suppressing the memory capacity.

  In this embodiment, “3” is assumed as the number of phases (= K). However, when the number of phases (= K) is “2”, the pixel number coefficient (= N) is “8”. The number of read pixels (= PX) per time from the line memory 24m is “32”. As a result, the pixel data stored in the line memory 24m is read in the order of FIG. 14 (A) → FIG. 14 (B) → FIG. 14 (C) → FIG. Data are read in the order of FIG. 15 (A) → FIG. 15 (B) → FIG. 15 (C) → FIG. 15 (D). The read addresses are 32 addresses surrounded by bold lines in each of FIGS. 14A to 14D and FIGS. 15A to 15D.

  In this embodiment, the number of horizontal pixels (= Hsize) is set to “128” and the number of cycles (= M) required for reading out charges from one horizontal pixel line is set to “4”, so the number of phases (= K). If “3”, the pixel number coefficient (= N) is “2”, and if the phase number (= K) is “2”, the pixel number coefficient (= N) is “8”.

  However, if the number of horizontal pixels (= Hsize) is set to “128” while the number of cycles (= M) required for reading out charges from one horizontal pixel line is set to “3”, the number of phases (= K) is set to “3”. In any case of “2” and “2”, the above-described formula 1 is not satisfied. This problem is that a memory area corresponding to a numerical value Hsize ′ that is closest to the horizontal pixel number (= Hsize) in a range exceeding the horizontal pixel number (= Hsize) is secured in the line memory 24m, and this numerical value Hsize ′ and the horizontal pixel number This can be solved by writing dummy pixel data corresponding to the difference from (= Hsize) to the line memory 24m.

  In this embodiment, “3” or “2” is assumed as the number of phases (= K), but the number of phases (= K) is not limited to this.

It is a block diagram which shows the structure of one Example of this invention. It is an illustration figure which shows an example of the pixel arrangement | sequence of the imaging surface provided in the image sensor applied to the FIG. 1 Example. It is an illustration figure which shows a part of electric charge read-out operation | movement from the image sensor applied to the FIG. 1 Example. It is a block diagram which shows an example of a structure of the horizontal rearrangement circuit applied to FIG. 1 Example. FIG. 5 is an illustrative view showing one portion of a write operation to a line memory applied to the embodiment in FIG. 4; (A) is an illustrative view showing a part of the read operation from the line memory shown in FIG. 5, (B) is an illustrative view showing another part of the read operation from the line memory shown in FIG. (C) is an illustrative view showing another part of the read operation from the line memory shown in FIG. 5, and (D) is an illustrative view showing still another part of the read operation from the line memory shown in FIG. FIG. (A) is an illustrative view showing a part of the read operation from the line memory shown in FIG. 5, (B) is an illustrative view showing another part of the read operation from the line memory shown in FIG. (C) is an illustrative view showing another part of the read operation from the line memory shown in FIG. 5, and (D) is an illustrative view showing still another part of the read operation from the line memory shown in FIG. FIG. FIG. 10 is an illustrative view showing another portion of the write operation to the line memory applied to the embodiment in FIG. 4; (A) is an illustrative view showing a part of the read operation from the line memory shown in FIG. 8, and (B) is an illustrative view showing another part of the read operation from the line memory shown in FIG. (C) is an illustrative view showing another part of the read operation from the line memory shown in FIG. 8, and (D) is an illustrative view showing still another part of the read operation from the line memory shown in FIG. FIG. (A) is an illustrative view showing a part of the read operation from the line memory shown in FIG. 8, and (B) is an illustrative view showing another part of the read operation from the line memory shown in FIG. (C) is an illustrative view showing another part of the read operation from the line memory shown in FIG. 8, and (D) is an illustrative view showing still another part of the read operation from the line memory shown in FIG. FIG. FIG. 10 is an illustrative view showing still another portion of the write operation to the line memory applied to the embodiment in FIG. 4; (A) is an illustrative view showing a part of the read operation from the line memory shown in FIG. 11, and (B) is an illustrative view showing another part of the read operation from the line memory shown in FIG. (C) is an illustrative view showing another part of the read operation from the line memory shown in FIG. 11, and (D) is an illustrative view showing still another part of the read operation from the line memory shown in FIG. FIG. (A) is an illustrative view showing a part of the read operation from the line memory shown in FIG. 11, and (B) is an illustrative view showing another part of the read operation from the line memory shown in FIG. (C) is an illustrative view showing another part of the read operation from the line memory shown in FIG. 11, and (D) is an illustrative view showing still another part of the read operation from the line memory shown in FIG. FIG. (A) is an illustrative view showing a part of a read operation from a line memory of another embodiment, and (B) is an illustrative view showing another part of a read operation from the line memory of another embodiment. (C) is an illustrative view showing another part of the read operation from the line memory of another embodiment, and (D) is still another one of the read operation from the line memory of the other embodiment. It is an illustration figure which shows a part. (A) is an illustrative view showing a part of a read operation from a line memory of another embodiment, and (B) is an illustrative view showing another part of a read operation from the line memory of another embodiment. (C) is an illustrative view showing another part of the read operation from the line memory of another embodiment, and (D) is still another one of the read operation from the line memory of the other embodiment. It is an illustration figure which shows a part.

Explanation of symbols

10 ... Digital camera 16 ... Image sensor 18 ... TG / SG
24 ... Horizontal rearrangement circuit 42 ... SDRAM

Claims (5)

An imaging unit having an imaging surface in which a plurality of pixels that generate electric charges are two-dimensionally arranged;
Charge reading means for reading out the charges generated on the imaging surface one pixel line at a time;
Data writing means for writing pixel data based on the charges read by the charge reading means to a memory; and data reading means for reading pixel data written by the data writing means from the memory;
The memory has a plurality of storage areas each storing pixel data of one pixel,
The charge readout means designates a plurality of pixels belonging to the target pixel line over M cycles (M: an integer of 2 or more) at a ratio of one pixel to consecutive M pixels,
The data reading means reads the pixel data by M * N pixels (N: integer of 1 or more) in order along the pixel arrangement in the target pixel line,
The data writing means is a pixel of M * N pixels read by the data reading means based on pixel data of M * N pixels based on the charges read by the charge reading means in association with the update of the target pixel line. An electronic camera that writes to M * N storage areas corresponding to data.   The electronic camera according to claim 1, wherein the number of storage areas of the memory is equal to or greater than the number of pixels belonging to one pixel line.   3. The electronic camera according to claim 1, wherein the numerical value indicated by N is calculated based on the number of storage areas of the memory, the number of write patterns of the data writing means, and the numerical value indicated by M. The number of storage areas which memory has a ST, when the number of write patterns of the writing means and the K, value that the N is shown is equal to a number indicated by ST / M ^K, claim 3 electronic camera according.   The electronic camera according to claim 1, wherein the memory has a data input port and a data output port individually.

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