JP2007250862A - Semiconductor device, integrated circuit and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device formed by three-dimensionally arranging devices each employing a semiconductor film having crystal grains grown from a starting point and capable of acquiring desired device characteristics in the device arranged in any layer, and to provide a method of manufacturing the same. <P>SOLUTION: This semiconductor device is formed in such a way that device layers 102, 103 each having the same configuration as that of a device layer 101 are stacked on the device layer 101 provided with a starting point section layer 211 having a plurality of micrepores G11, G12 on its surface and a device forming layer 212 formed using semiconductor films 201, 202 containing substantial single crystal grains formed using the micropres G11, G12 as a starting point. The micropores (e.g. micropores G21) belonging to the device layers 101-103 are formed at positions spaced in a plan view from the micropores (e.g. micropores G11, G31) belonging to the adjacently arranged other devices 101-103. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, an integrated circuit, and an electronic device.

In recent years, for the purpose of speeding up thin film transistors (TFTs), a technique for preventing a crystal grain boundary from entering a TFT channel region by forming a semiconductor film having large crystal grains has been studied. . For example, Patent Document 1 discloses a technique for forming a silicon crystal grain having a large grain size by forming a fine hole on a substrate and crystallizing a semiconductor film using the fine hole as a starting point for crystal growth. Yes. Further, in Patent Document 2, an impurity implantation region (for example, a source / drain region) of such a semiconductor film is also formed of substantially single crystal grains so that impurity activation can be performed smoothly to increase the speed of the semiconductor device.
JP-A-11-87243 JP-A-2005-294628

  According to the technique described in Patent Document 2, the speed of the TFT itself can be increased. However, if the integration and high integration of various devices in an integrated circuit are to be realized, the wiring width will be reduced accordingly, and the relative wiring length will increase, resulting in an increase in propagation delay between transistors. . In order to cope with such a problem, since there is a limit in reducing the resistance of the wiring material and reducing the dielectric constant of the interlayer insulating film, it is necessary to consider a three-dimensional arrangement of devices capable of drastically shortening the wiring length.

By the way, in the semiconductor film described in Patent Document 1 or the like, a fine hole (starting point portion) serving as a starting point for crystal growth is disposed in the planar region, and a minute step or stress is present in the vicinity of the fine hole. It tends to occur. Although the Patent Document 2 does not discuss any three-dimensional IC, it is considered that the positional relationship between the micropores and the device is extremely important for obtaining desired device characteristics when the device is three-dimensionally arranged. .
Accordingly, an object of the present invention is to provide a device using a semiconductor film having crystal grains grown from a starting portion in a three-dimensional arrangement and to obtain desired device characteristics in any device arranged in any layer. An object of the present invention is to provide a semiconductor device that can be manufactured and a manufacturing method thereof.

In order to solve the above problems, a semiconductor device of the present invention is a semiconductor device including a semiconductor film formed on a substrate, and has a starting portion layer having a plurality of fine holes on the surface, and the fine holes as starting points. A plurality of device layers each including a device forming layer formed using a semiconductor film including substantially single crystal grains formed as a layer, and the micropores belonging to any of the device layers are arranged adjacent to each other It is formed in the position spaced apart from the said micropore which belongs to said other said device layer by planar view.
Since the microhole is used as a starting point (grain filter) of the semiconductor film containing the substantially single crystal grain, the microhole has a structure in which a part of the semiconductor film is embedded instead of a cavity. Yes. Therefore, in the vicinity of the fine hole, a minute step or the like due to stress or the concave shape of the fine hole is likely to occur. And when such a micropore is unevenly distributed in a specific site | part, a big stress may be applied to the site | part and a big level | step difference may arise. Therefore, in the present invention, in the laminated structure of a plurality of device layers, the plane positions of the micropores are shifted in the adjacent device layers, and this configuration disperses the stress near the micropores and prevents the occurrence of a large step. Can be done. As a result, the device characteristics can be stabilized, and further, the long-term reliability can be improved by dispersing the stress.

It is preferable that the device having the semiconductor film belonging to an arbitrary device forming layer is formed at a position separated from the micropore in a region surrounded by the micropore belonging to the device layer.
As described above, stress and steps are likely to occur in the vicinity of the microhole, and when a device is configured using a semiconductor film that includes the microhole in a planar region or a semiconductor film that is positioned in the vicinity of the microhole, the threshold voltage may vary. This is because mobility may be lowered.

The planar distance between the device in the device layer and the fine hole surrounding the device is preferably 5 times or more the minimum design rule of the device.
The “minimum design rule” corresponds to the minimum width of a semiconductor film or a wiring member constituting the device. When the device is a thin film transistor, the gate length or the like corresponds to the minimum design rule. In addition, by setting the distance between the fine hole and the device to be 5 times or more of the minimum design rule, it is possible to prevent the device from being affected by the stress and step caused by the fine hole, and the stability and long-term reliability of the device. This is an effective configuration for ensuring the above.

The plurality of device layers include a first device layer and a second device layer that have substantially the same planar arrangement of the micropores, and the first device layer, the second device layer, In the meantime, it is preferable that at least one device layer having a plane arrangement of the micropores different from that of the first device layer and the second device layer is provided. That is, when the planar positions of the micropores are made the same in a plurality of device layers, at least one other device layer having a different micropore arrangement is provided between the device layers having the same arrangement.
By adopting such a configuration, it is possible to disperse stress caused by the micropores, and it is possible to ensure device stability and long-term reliability. And, by making the planar position of the micropores the same in a plurality of device layers, the regions suitable for device formation in these device layers are also the same, so that the device can be easily connected between the device layers. can get.

  It is preferable that the arrangement pattern and arrangement interval of the micropores in each device layer are substantially the same. By adopting such a configuration, the size of substantially single crystal grains in the semiconductor film of each device formation layer can be made uniform, and the grain boundary distribution of the single crystal grains can be made uniform. Can be formed.

  The fine holes may be arranged at equal intervals in the left-right and up-down directions in a plan view. Or the said micropore can also be set as the structure arranged so that all the said micropores adjacent in planar view may become equal intervals. Even when any of the above arrangement forms is adopted, according to the semiconductor device of the present invention, stabilization of the device and improvement of long-term reliability can be realized.

  The arrangement interval of the micropores in each device layer is preferably 0.5 μm or more and 3 μm or less. If the arrangement interval is 0.5 μm or less, the region separated from the micropores suitable for device formation is too narrow, and if it is 3 μm or more, it includes substantially single crystal grains starting from the micropores. This is because it takes a lot of time to form the semiconductor film. In addition, the arrangement interval of the micropores in each device layer is more preferably 1 μm or more and 2 μm or less. This is because a semiconductor film including substantially single crystal grains can be formed in a short time while sufficiently securing a device formation region.

An integrated circuit of the present invention is an integrated circuit including the semiconductor device of the present invention, and an electronic device of the present invention is an electronic device including the semiconductor device of the present invention.
Since the semiconductor device of the present invention is stable and has high performance, all integrated circuits configured by integrating semiconductor devices, electro-optical devices such as liquid crystal display devices and organic EL display devices, other general electronic devices, For example, mobile phones, video cameras, personal computers, head-mounted displays, rear or front projectors, fax machines with display functions, digital camera finders, portable TVs, electronic notebooks, electronic bulletin boards, and advertising displays Can be used.

(First embodiment)
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a partial cross-sectional view showing a schematic configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view showing the arrangement of micropores (grain filters; starting point portions) in the semiconductor device shown in FIG. The “semiconductor device” according to the present invention generally refers to a device formed using a semiconductor film having substantially single crystal grains, which will be described later. In the present invention, transistors, diodes, resistors, Inductors, capacitors, and other active or passive elements are included.

A semiconductor device 100 shown in FIG. 1 includes a silicon substrate 105, a substrate layer 110 including a semiconductor element (device) formed on the silicon substrate 105, a first device layer 101 sequentially stacked on the substrate layer 110, A second device layer 102, a third device layer 103, and a protective layer 104 formed on the third device layer 103 are provided.
FIG. 1 is a diagram for explaining the laminated structure of the substrate layer 110 and the device layers 101 to 103 in the semiconductor device 100 of the present embodiment. For the thin film transistors and the like formed in the device layers 101 to 103, FIG. Examples of devices that can be formed in the layers 101 to 103 are shown and do not constitute a device having a specific structure.

  The substrate layer 110 includes a silicon substrate 105, MOS transistors Q11 and Q12 formed on the silicon substrate 105, and an element isolation region 114. Further, source / drain regions 112 a to 112 d are formed in the silicon substrate 105. A gate insulating film 113 is formed on the silicon substrate 105 between the source / drain regions 112 a and 112 b, and a gate electrode 116 is formed on the gate insulating film 113. Sidewalls 118 are formed on the side end surfaces of the gate electrode 116. Low-concentration impurity implantation regions of the source / drain regions 112a and 112b are formed on the silicon substrate 116 on both sides of the gate electrode 116, and the transistors Q11 and Q12 have a so-called LDD (Lightly Doped Drain) structure. It has become. The element isolation region 114 is formed of a groove formed on the surface of the silicon substrate 105, and electrically isolates the transistors Q11 and Q12.

  An interlayer insulating film 106 is formed to cover the transistors Q11 and Q12, and connection wirings 121 to 123 made of aluminum or the like are formed on the interlayer insulating film 106. Four contact holes are formed through the interlayer insulating film 106 to reach the source / drain regions 112a, the gate electrode 116, and the source / drain regions 112c and 112d, respectively, and a metal such as tungsten is formed in the contact holes. Contact portions (plugs) C11 to C14 made of a material are formed. The source / drain region 112a and the connection wiring 121 are electrically connected through the contact portion C11, and the gate electrode 116 of the transistor Q11 and the transistor Q12 are connected through the contact portion C12, the connection wiring 122, and the contact portion C13. The source / drain region 112c is electrically connected, and the source / drain region 112d and the connection wiring 123 are electrically connected via the contact portion C14.

  The first device layer 101 includes a starting point layer 211 made of an insulating film formed so as to cover the connection wirings 121 to 123 and the interlayer insulating film 106 of the substrate layer 110, and a device formed on the starting point layer 211. And a formation layer 212. The starting point layer 211 has a configuration in which a plurality of first micro holes G11 are arranged on a silicon oxide film as an insulating film. The first microhole G11 preferentially advances crystal growth using one crystal nucleus as a seed when the amorphous silicon film formed on the starting portion layer 211 is melt-crystallized to form a crystallized semiconductor film. This is also called “grain filter”.

  A thin film transistor (TFT) Q13 which is a device using the crystallized semiconductor film 201 and a thin film transistor Q14 which is a device using the crystallized semiconductor film 202 are included in the device formation layer 212 on the starting portion layer 211. An interlayer insulating film 107 is formed so as to cover these thin film transistors Q13 and Q14. On the interlayer insulating film 107, connection wirings 124 to 126 made of aluminum or the like are formed. A plurality of contact holes penetrating the interlayer insulating film 107 are formed, and contact portions C15 to C17 are formed by arranging tungsten or the like in these contact holes. The connection wiring 124 and the gate electrode 116 of the thin film transistor Q13 are electrically connected via the contact portion C15, and the connection wiring 123 and the source / drain region of the thin film transistor Q14 are electrically connected via the contact portion C16. The connection wiring 124 and the source / drain region of the thin film transistor Q14 are electrically connected through the contact portion C17.

  The crystallized semiconductor films 201 and 202 constituting the thin film transistors Q13 and Q14 are semiconductor films formed by patterning a semiconductor film containing substantially single crystal grains grown from the fine holes G11 and G12 formed in the starting portion layer 211. Specifically, an amorphous silicon film is formed on the starting portion layer 211 including the fine holes G11 and G12, and the amorphous silicon film is irradiated with laser light. Can be formed by melt crystallization. The semiconductor film formed in this way is an aggregate of substantially single crystal grains grown about the fine holes G11 and G12, and includes a regular grain boundary such as Σ3, Σ9, and Σ27, but does not contain an irregular grain boundary. Become a film. In general, irregular grain boundaries contain a large number of unpaired electrons, which is a major factor in the deterioration of characteristics and variations in the characteristics of the elements formed there. By forming an element in a single crystal grain, an element having excellent characteristics can be realized.

The second device layer 102 formed on the first device layer 101 has a configuration in which an origin layer 221 and a device formation layer 222 are stacked. The starting point layer 221 has a configuration in which a plurality of micropores (grain filters) G21, G22, and G23 are arranged on the surface of the silicon oxide film, like the starting point layer 211 of the first device layer 101. In the device forming layer 222, crystallized semiconductor films 203, 204, and 205 are formed by patterning a semiconductor film including substantially single crystal grains formed from the fine holes G21, G22, and G23 as a starting point into a predetermined planar shape. ing. Of these crystallized semiconductor films, the crystallized semiconductor film 204 is used to form the thin film transistor Q15. The thin film transistor Q15 has the same configuration as the thin film transistor Q13 of the first device layer 101. An interlayer insulating film 108 is formed so as to cover the semiconductor films 203 to 205 and the thin film transistor Q15.
Via the contact portions C18-20 provided in the contact holes formed in the interlayer insulating film 108, the connection wirings 127, 128 on the interlayer insulating film 108, the crystallized semiconductor films 203, 204, and the gate of the thin film transistor Q15 The electrode 116 is electrically connected.

  The third device layer 103 formed on the second device layer 102 has a configuration in which a starting point layer 231 and a device forming layer 232 are sequentially stacked. The starting point layer 231 has a configuration in which a plurality of fine holes (grain filters) G31 and G32 are arranged on the surface of the silicon oxide film, like the starting point layer 221 of the second device layer 102. In the device forming layer 232, crystallized semiconductor films 206 and 207 are formed by patterning a semiconductor film containing substantially single crystal grains formed from the fine holes G31 and G32 into a predetermined planar shape. Of these crystallized semiconductor films, the crystallized semiconductor film 207 is used to form the thin film transistor Q16. The thin film transistor Q16 has the same configuration as the thin film transistor Q13 of the first device layer 101. An interlayer insulating film 109 is formed so as to cover the semiconductor films 206 and 207 and the thin film transistor Q16. Via the contact portions C21 and C22 provided in the contact hole formed in the interlayer insulating film 109, the connection wirings 129 and 130 on the interlayer insulating film 108, the crystallized semiconductor film 207, and the gate electrode 116 of the thin film transistor Q15 Are electrically connected.

  A protective layer 104 is partially formed on the third device layer 103, and the connection wiring 129 extending from the edge of the protective layer 104 functions as an external connection terminal (electrode pad). It has become. The protective layer 104 can be formed using an insulating resin material such as an acrylic resin or a polyimide resin.

  As described above, the semiconductor device 100 according to the present embodiment has a configuration in which a plurality of device layers 101 to 103 each including the starting portion layers 211, 221, and 231 are stacked on the substrate layer 110. In the semiconductor device 100 of the present embodiment, the planar arrangement of the fine holes G11, G12, G21 to G23, G31, and G32 in the starting point layers 211, 211, and 231 is as shown in FIG. The stress generated in the vicinity of each minute hole is prevented from affecting the operation of the device (such as a thin film transistor).

  In FIG. 2, each microhole including the microholes G11 and G12 formed in the first device layer 101 is shown as a first microhole G10, and the microhole G21 formed in the second device layer 102 is shown. Each microhole including -G23 is shown as a second microhole G20, and each microhole including microholes G31 and G32 formed in the third device layer 103 is shown as a third microhole G30.

As shown in FIG. 2, the micropores G10, G20, G30 in each layer are formed at positions that do not overlap each other in a plane, and are arranged so that adjacent micropores are equidistant in each starting point layer. ing. That is, when attention is paid to one minute hole G100 among the first minute holes G10 indicated by black circles in FIG. 2, six first minute holes G101 are formed at each apex of a regular hexagon centering on the minute hole G100. To G106 are arranged.
Further, three second micro holes G201 to G203 are formed at the center of a triangle formed by a line segment connecting the first micro hole G100 and the six first micro holes G101 to G106. The three third micro holes G301 to G303 are alternately arranged counterclockwise around the first micro hole G100.

  The starting point layers 211, 211, and 231 have a structure in which silicon (a part of the crystallized semiconductor film) is embedded in the fine holes G10, G20, and G30 formed on the surface of the silicon oxide film, respectively. As described above, among the device layers 101 to 103, stress is likely to occur, and since a minute step is generated due to the concave shape of the microhole, the semiconductor layer and the interlayer insulating film are also prone to defects. If such fine holes G10, G20, and G30 are formed at positions close to each other, there is a risk of adversely affecting the neighboring devices. For example, in a thin film transistor, the threshold voltage (Vth) may change or the mobility may decrease.

  Therefore, in the present embodiment, as shown in FIG. 2, the micropores G10, G20, G30 of each starting point layer are arranged at positions that do not overlap each other in a planar manner, and the devices formed in the device forming layers 212, 222, 232 On the other hand, the structure that contributes to the stabilization of the initial characteristics of the devices formed in each device layer is realized so as not to be affected by the defects caused by the stress and the fine holes. Further, the fine holes G10, G20, G30 are arranged at equal intervals in the respective starting portion layers 211, 211, 231, and the adjacent fine holes G10, G20, G30 are arranged at equal intervals in a plan view. By adopting such a configuration, the stress distribution in each of the device layers 101, 102, and 103, as well as the stress distribution between the stacked layers, are achieved, and the long-term reliability of the semiconductor device is improved. Yes.

  In each starting part layer 211, 211, 231, the arrangement interval of the micropores is preferably 0.5 μm or more and 3 μm or less. When the arrangement interval is 0.5 μm or less, the region separated from the micropores suitable for device formation becomes too narrow, and when it is 3 μm or more, a substantially single-crystal semiconductor film starting from the micropores This is because it takes a lot of time to form.

  As shown in FIG. 2, each of the device layers 101 to 103 is periodically formed with micropores G10, G20, and G30, and a semiconductor film grown from the micropores G10, G20, and G30 as a starting point. The devices of the respective device formation layers 212, 222, and 232 are formed by using what is patterned into a desired shape. In such a configuration, stress is generated at the positions where the micro holes G10, G20, and G30 are formed as described above. For example, a fine region is formed in the planar region of the crystallized semiconductor film 201 included in the thin film transistor Q13 illustrated in FIG. If the hole G11 (first fine hole G10) is included, there is a possibility that a threshold voltage change or a mobility decrease may occur in the thin film transistor Q13. Therefore, in each of the device layers 101 to 103 of the semiconductor device 100 according to the present embodiment, it is preferable to form a device at a position separated from the micropores of the starting portion layer included in each device layer.

  For example, in the first device layer 101 having the starting portion layer 211 formed by periodically arranging the first micro holes G10 indicated by black dots in FIG. 2, devices (thin film transistors Q13, Q13) formed in the device forming layer 212 are provided. Q14) is preferably formed in a triangular region in plan view surrounded by three adjacent first micro holes G10 (for example, micro holes G100, G101, G102), and is formed in the device forming layer 212. More preferably, the distance of 5 times or more of the minimum design rule is arranged away from the first microhole G10. The minimum design rule is the minimum width of the members constituting the device, for example, the gate width or the element isolation region width of the MOS transistor. Therefore, when the minimum design rule is 0.25 μm, the distance between the first minute hole G10 and the device is set to 1.25 μm or more. In the above description, the first device layer 101 has been described as an example, but the same applies to the second device layer 102 and the third device layer 103.

  By the way, as shown in FIG. 2, for example, an upper second fine hole G20 or a third fine hole G30 is formed at the center of the region surrounded by the first fine hole G10 of the first device layer 101. Has been placed. According to the rule regarding the distance between the fine hole and the device, the device formed in the device forming layer 212 is preferably located on the center side of the region surrounded by the three first fine holes G10 in FIG. . Then, the second micro hole G20 or the third micro hole G30 is disposed on the device of the device forming layer 212, but the number of insulating films constituting the starting point layer 221 on the device forming layer 212 is several. Since it has a thickness of about μm, the effect on the device is small compared to the micropores formed in the same device layer, and even if the upper micropores are located directly above the device, it will hinder device operation. Absent.

  In the present embodiment, the case where the substrate layer 110 is a device in which devices (transistors Q11 and Q12) are formed on the silicon substrate 106 has been described. However, the configuration of the substrate layer 110 is not limited. The substrate layer 110 may be a glass substrate, a quartz substrate, a silicon substrate, or the like that does not include a device.

  In the present embodiment, three device layers 101 to 103 are stacked, but it is needless to say that a semiconductor device may be formed by stacking four or more device layers. In this case, the micro holes in the fourth device layer of the fourth layer are preferably formed at positions that do not overlap with the micro holes G10, G20, and G30 of the device layers 101 to 103 in a plane. Or you may form in the position which overlaps with the 1st minute hole G10 planarly. Further, when the fifth device layer of the fifth layer is provided, the micropores of the fifth device layer and the micropores of the fourth device layer are not overlapped with the micropores of the fourth device layer. It is good to form in the position which overlaps planarly.

  In the present embodiment, the thin film transistors Q13 to Q16 are formed in the device layers 101 to 103. However, the present invention uses a semiconductor film including substantially single crystal grains grown from micropores. Any semiconductor device including a formed device can be applied, and devices in each layer do not have to have the same function. For example, an analog-logic circuit is formed in the first device layer 101, an SRAM memory is formed in the second device layer 102, and an I / O circuit having a high voltage portion is formed in the third device layer 103. A semiconductor device having a composite function may be configured. Moreover, it is also possible to change the arrangement | sequence form of micropore G10, G20, G30 according to the characteristic of the device formed in each device layer 101-103. For example, in a device layer that forms a circuit having redundancy such as a memory, from the aspect in which the arrangement of the micro holes is arranged at the apex of the equilateral triangle shown in FIG. You may change to the aspect (refer FIG. 5) which arrange | positions a micropore in a vertex.

[Method for Manufacturing Semiconductor Device]
Next, a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.
In the method for manufacturing a semiconductor device according to the present invention, a first device layer 101, a second device layer 102, and a third device layer 103 are sequentially stacked on a substrate layer 110. And the process of laminating | stacking the 2nd device layer 102 and the 3rd device layer 103 laminated | stacked on the 1st device layer 101 repeats the process similar to the formation process of the 1st device layer 101. Therefore, in the following, the formation process of the first device layer 101 will be described in detail.

(Micropore formation process)
First, using a normal semiconductor process, as shown in FIG. 1, various devices such as transistors Q11 and Q12 are formed on a silicon substrate 105, an interlayer insulating film 106 covering the devices is formed, and a substrate layer 110 is formed. Is made. Next, a silicon oxide film as an insulating film is formed over the substrate layer 110. Examples of a method for forming a silicon oxide film on the substrate layer 110 include a physical vapor deposition method such as a plasma chemical vapor deposition method (PECVD method), a low pressure chemical vapor deposition method (LPCVD method), or a sputtering method. It is done. For example, a silicon oxide film having a thickness of several hundred nm can be formed by PECVD.

Next, as shown in FIG. 3A, the first minute hole G10 is formed at a predetermined position of the silicon oxide film on the substrate layer 110, so that the starting point layer 211 is obtained. For example, by performing a photolithography process and an etching process, the first micro hole G10 having a circular cross section can be opened at a predetermined position in the plane of the starting portion layer 211. Examples of the etching method include reactive ion etching using plasma of CHF ₃ gas.

  Here, the first micropore G10 is a “grain filter” that plays a role of preferentially advancing crystal growth using one crystal nucleus as a seed in a melt crystallization process described later. The first fine hole G10 is preferably formed in a cylindrical shape, for example, but may have a shape other than the cylindrical shape (for example, a conical shape, a prismatic shape, a pyramid shape, etc.). Also, after forming a hole having a relatively large diameter (for example, about 500 nm), a new insulating film (silicon oxide film in this example) is deposited on the entire surface of the substrate to reduce the diameter of the first hole G10. May be formed.

(Film formation process)
Next, as shown in FIG. 3B, an amorphous silicon film (non-single-crystal silicon film) 200a is formed in the first micro hole G10 and on the starting portion layer 211. The amorphous silicon film 200a can be formed by PECVD, LPCVD, atmospheric pressure chemical vapor deposition (APCVD), sputtering, or the like. Note that in this step, a polycrystalline silicon film may be formed as the non-single-crystal semiconductor film instead of the amorphous silicon film. In this step, it is desirable to form a relatively thick film so as to increase the size of substantially crystal grains obtained by melt crystallization. Specifically, the amorphous silicon film 200a is a film having a thickness of 150 nm or more. It is preferable to form it thickly.

(Melt crystallization process)
Next, as shown in FIG. 3C, the amorphous silicon film 200a is melt-crystallized by irradiating the amorphous silicon film 200a with a laser. For example, it is preferable to use a XeCl pulse excimer laser (wavelength 308 nm, pulse width 30 nsec) and perform laser irradiation at an energy density of 0.4 to 1.5 J / cm ² . Note that a solid laser, a gas laser, or the like may be used instead of the excimer laser. Thereby, as will be described later, a crystalline silicon film (single crystal silicon film) 200 in a substantially single crystal state is formed.

Here, most of the irradiated XeCl pulse excimer laser is absorbed near the surface of the amorphous silicon film 200a. This 0.139Nm ^-1 absorption coefficient of amorphous silicon and crystalline silicon at a wavelength (308 nm) of the XeCl pulsed excimer laser, respectively, is larger and 0.149nm ^-1. In addition, the silicon oxide film constituting the starting point layer 211 is substantially transparent to the laser and does not absorb the energy of the laser, and therefore is not melted by laser irradiation. As a result, the amorphous silicon film 200a in the region other than the first fine hole G10 is almost completely melted over the entire film thickness direction. In addition, the amorphous silicon film 200a in the first microhole G10 is melted on the upper side and is not melted (partially melted) at the bottom of the first microhole G10.

  Solidification of silicon after laser irradiation proceeds from the inside of the first microhole G10 first, and then reaches a portion (surface side portion) where the amorphous silicon film 200a is in a substantially completely melted state. At this time, some crystal grains are generated in the vicinity of the bottom of the first microhole G10, but the cross-sectional dimension of the first microhole G10 (in this embodiment, the diameter of a circle) is the same as that of one crystal grain. By setting it to a level or a little smaller, only one crystal grain reaches the upper part (opening) of the first micro hole G10. Thereby, in the substantially completely melted portion of the amorphous silicon film 200a, crystal growth proceeds with one crystal grain reaching the upper portion of the first microhole G10 as a nucleus, and FIG. As shown in FIG. 3, a crystalline silicon film 200b having a substantially single crystal state is formed in a region having the first micro hole G10 substantially at the center. At this time, the flatness on the surface of the crystalline silicon film 200b may be lowered as shown in the figure due to the influence of crystallization.

  In the present embodiment, “substantially single crystal” means not only a single crystal grain but also a state close to this, that is, even if a plurality of crystals are combined, the number is small, and the viewpoint of the properties of the semiconductor thin film This includes the case where the film has properties equivalent to those of a semiconductor thin film formed from a single crystal. The crystalline silicon film 200b has few defects inside, and the effect of reducing the trap level density near the center of the forbidden band in the energy band can be obtained in terms of electrical characteristics of the semiconductor film. Moreover, since it can be considered that there is almost no crystal grain boundary, an effect of greatly reducing the barrier when carriers such as electrons and holes flow can be obtained. When this crystalline silicon film 200b is used for an active layer (source / drain region or channel region) of a thin film transistor (device) as described later, an excellent thin film transistor having a small off-current value and a high mobility is obtained.

(Planarization process)
When the flatness of the surface of the substantially monocrystalline crystalline silicon film 200b is low, the surface of the crystalline silicon film 200b is planarized by CMP (chemical mechanical polishing). Hereinafter, a process of planarizing the surface of the crystalline silicon film 200b by CMP (chemical mechanical polishing) will be described.
The surface roughness of the crystalline silicon film 200b is increased particularly when the first fine holes G10 are arranged close to each other. That is, since the crystal grains grown around each of the first micro holes G10 collide with each other, the boundaries (grain boundaries) between the crystal grains rise, and the surface of the crystalline silicon film 200b is uneven.

  As shown in FIG. 3D, the surface of the crystalline silicon film 200b is planarized by CMP. At this time, the surface of the crystalline silicon film 200b is smoothed, and the leakage current near the substrate side is reduced, that is, in order to avoid the punch-through phenomenon, a process of reducing the thickness of the crystalline silicon film 200b is also performed. Do it. In this case, polishing is preferably performed until the thickness of the crystalline silicon film 200b becomes 50 nm or less.

  Here, an example of suitable conditions for performing the CMP will be described. For example, a soft polyurethane pad and a polishing liquid in which an abrasive such as silica particles is dispersed in an ammonia-based or amine-based alkaline solution are used in combination. The polishing liquid is an alkaline solution having a hydrogen ion concentration of pH 9.0 or less, and the surface roughness of the crystalline silicon film 200b can be reduced to 1 nm or less by CMP treatment using the polishing liquid. As a result, as shown in FIG. 3 (E), a crystallized semiconductor that is a high-quality crystalline silicon film that has excellent surface flatness with a surface roughness of 1 nm or less and that can achieve element miniaturization by thinning. A membrane 200 is obtained.

(Element formation process)
Next, taking a thin film transistor (device) as an example, a process for forming a device using the crystallized semiconductor film 200 manufactured by the above-described manufacturing method will be described. Through the thin film transistor formation process described below, for example, the thin film transistors Q13 and Q14 shown in FIG. 1 can be formed.

FIG. 4 is a diagram for explaining the element forming step.
First, as illustrated in FIG. 4A, the crystallized semiconductor film 200 is formed by patterning the crystallized semiconductor film 200 to remove a portion unnecessary for formation of the thin film transistor and perform shaping. At this time, patterning may be performed so as to include a plurality of crystallized semiconductor films 200 formed adjacent to each other.

  Next, as illustrated in FIG. 4B, an insulating film 108 a made of silicon oxide or the like is formed over the starting portion layer 211 and the crystallized semiconductor film 200. The insulating film 108a can be formed using, for example, an electron cyclotron resonance PECVD method (ECR-CVD method) or a PECVD method. A direct oxidation method using high-density plasma may be used. This insulating film 108a functions as a gate insulating film of the thin film transistor, and corresponds to the gate insulating film 113 of the thin film transistors Q13 and Q14 shown in FIG.

Next, as shown in FIG. 4C, a metal thin film of tantalum or aluminum is formed by a sputtering method and then patterned to form a gate electrode 200D. The gate electrode 200D corresponds to the gate electrode 116 of the thin film transistors Q13 and Q14 shown in FIG.
Next, impurity ions serving as donors or acceptors are implanted using the gate electrode 200D as a mask, and source / drain regions 200B and 200C and a channel region 200A are formed in a self-aligned manner with respect to the gate electrode 200D. When manufacturing an NMOS transistor, for example, phosphorus (P) as an impurity element is implanted into the source / drain region at a concentration of 1 × 10 ¹⁶ cm ⁻² . Thereafter, the XeCl excimer laser is irradiated at an irradiation energy density of about 400 mJ / cm ² or heat treatment is performed at a temperature of about 250 ° C. to 450 ° C. to activate the impurity element.

  Next, as illustrated in FIG. 4D, an insulating film 108c formed of a silicon oxide film or the like is formed over the insulating film 108a and the gate electrode 200D. For example, the insulating film 108c having a thickness of about 500 nm is formed by PECVD. Next, contact holes reaching the source / drain regions 200B and 200C are opened in the insulating films 108b and 108c, and source / drain electrodes 120 are formed in the contact holes and in the peripheral portions of the contact holes on the insulating film 108c. . The source / drain electrode 120 can be formed by depositing aluminum by sputtering, for example. Alternatively, after selectively burying tungsten only in the contact hole, an aluminum film is patterned on the insulating film 108c and electrically connected to the tungsten plug to form the source / drain electrode 120. Good. Alternatively, a contact hole reaching the gate electrode 200D can be opened in the insulating film 108c to form a terminal electrode for the gate electrode 200D. As described above, the thin film transistor Q as the device according to the present embodiment can be manufactured. By forming the interlayer insulating film made of a silicon oxide film or the like so as to cover the thin film transistor Q, the first thin film transistor Q shown in FIG. The device layer 101 (the origin layer 211 and the device formation layer 212) can be formed.

  If the first device layer 101 is formed by the above steps, the second device layer 102 and the third device layer 103 can be formed by sequentially repeating the steps of forming the first device layer 101. . Then, if the protective layer 104 is patterned on the third device layer 103, the semiconductor device 100 of this embodiment can be manufactured.

  In the example shown in FIG. 4, for convenience of explanation, the first micro hole G10 is shown to be located immediately below the thin film transistor. However, as described above, the position where the first micro hole G10 is formed is The thin film transistor Q is preferably located outside the crystallized semiconductor film 200. In this case, in the patterning step described with reference to FIG. 4A, the first fine hole G10 is formed when a portion to be an active region (channel region 200A, source / drain regions 200B, 200C, etc.) of the thin film transistor Q is patterned. What is necessary is just to remove the formation position.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG.
FIG. 5 is an explanatory diagram showing a planar arrangement of the fine holes (grain filters) G10, G20, and G30 in the semiconductor device 400 of the present embodiment. The semiconductor device 400 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in the arrangement of the fine holes G10, G20, and G30 for obtaining a crystallized semiconductor film. The configuration is the same as that of the semiconductor device 100. Therefore, the semiconductor device 400 of this embodiment also has a structure in which three device layers 101 to 103 are sequentially stacked on the substrate layer 110.

  In the first embodiment, the micro holes G10, G20, and G30 provided in the three device layers 101 to 103 formed on the substrate layer 110 are arranged so as not to overlap each other in a plane. Since stress caused by the fine holes G10, G20, and G30 is also three-dimensionally dispersed, it can be said that the arrangement of the fine holes G10, G20, and G30 is the most suitable. However, on the other hand, as described above, the device formation position in each of the device layers 101 to 103 is preferably a region that is planarly separated from the micro holes G10, G20, and G30, as shown in FIG. In the arrangement form of the fine holes, an area that can be suitably used for forming a device is narrowed. In addition, since the three adjacent minute holes G10 (G20, G30) are arranged so as to be located at the apex of the equilateral triangle, when trying to form a device, wiring, etc. avoiding the formation position of the minute hole, Shape and wiring routing are limited.

  Therefore, in the semiconductor device 400 of this embodiment, as shown in FIG. 5, the micro holes G10, G20, G30 of each layer are arranged at the intersections of the square lattice. Specifically, the first micro holes G101 to G109 (G10) included in the first device layer 101 are arranged at equal intervals in the horizontal direction in the figure, and the second micro holes included in the second device layer 102 are arranged. The holes G201 to G209 (G20) are arranged almost at the center of a square area surrounded by four first microholes G10 (for example, the first microholes G101, G102, G105, and G104) adjacent in plan view. ing. Further, the third micro holes G301 to G309 (G30) included in the third device layer 103 are arranged at positions overlapping the first micro holes G101 to G109 in plan view.

  By arranging the fine holes G10, G20, and G30 as described above, the device formation layers 212, 222, and 232 have regions where devices can be suitably formed compared to the semiconductor device 100 of the first embodiment. Can be taken big. Further, since the micro holes G10, G20, and G30 are arranged at equal intervals in the vertical and horizontal directions in FIG. 5, restrictions on the device shape and the routing of the wiring are eased in each device forming layer. Therefore, an arrangement that can reduce device variations in a large-scale area can be realized, and high performance of the semiconductor device can be easily achieved.

  In the case of the present embodiment, the third micro hole G30 of the third device layer 103 is formed at a position overlapping in plan view corresponding to the first micro hole G10 of the first device layer 101. By adopting such a configuration, the device formation regions of the device layers 101 to 103 in the device formation layers 212, 222, and 232 have a portion where the device formation regions overlap each other in a plane, and thus a device is formed in the overlap region. Thus, there is an advantage that device connection between the device layers 101 to 103 is facilitated.

  As described above, stress is likely to occur at the formation positions of the fine holes G10, G20, and G30. Therefore, it is preferable to form the fine holes G10, G20, and G30 in a position where they overlap in a plane in order to cause concentration of the stress. Absent. However, in the present embodiment, the first microhole G10 and the third microhole G30 that are separated via the second device layer 102 are formed at positions that overlap in a plane. It is considered that the stress caused by each of G30 does not directly affect the device layers 103 and 101 of each other.

  In the present embodiment, the second microhole G20 of the second device layer 102 is positioned farthest from the micropores G10 and G30 in the first device layer 101 and the third device layer 103 (adjacent four holes). It is considered that the stress caused by the micropores does not affect between the adjacent device layers because it is arranged at the center of the first micropore G10. Further, with respect to the second fine hole G20 located in the middle, the fine holes G10 and G30 of the adjacent device layers 101 and 103 are formed at symmetrical positions, so that the fine holes G10, G20 and G30 as the whole semiconductor device are formed. The stress caused by is distributed equally three-dimensionally, which contributes to improving the long-term reliability of the semiconductor device.

  In the present embodiment, similar to the semiconductor device 100 according to the first embodiment, three device layers 101 to 103 are stacked, but a semiconductor device is configured by stacking four or more device layers. Of course, it is good. In this case, the micro hole in the fourth device layer of the fourth layer is preferably formed at a position overlapping the second micro hole G20 in a planar manner. Further, when the fifth device layer of the fifth layer is provided, it is preferable that the micropores of the fifth device layer be formed at a position overlapping the third micropore G30 in a plane.

(Integrated circuits, electro-optical devices, electronic equipment)
Next, specific examples of an integrated circuit, an electro-optical device, and an electronic device that include the semiconductor device described above will be described.
The integrated circuit in the present invention refers to a circuit (chip) in which semiconductor devices and related wirings are integrated and wired so as to exhibit a certain function.
The electro-optical device in the present invention refers to a general device including an electro-optical element that includes the semiconductor device according to the present invention and emits light by an electrical action or changes the state of light from the outside, and emits light by itself. And those that control the passage of light from the outside. For example, as an electro-optical element, a liquid crystal element, an electrophoretic element having a dispersion medium in which electrophoretic particles are dispersed, an EL (electroluminescence) element, and an electron-emitting element that emits light by applying electrons generated by applying an electric field to a light-emitting plate An active matrix display device provided.
The electronic apparatus of the present invention refers to a general apparatus having a certain function provided with the semiconductor device according to the present invention, and includes, for example, an electro-optical device and a memory. The configuration is not particularly limited, but for example, an IC card, a mobile phone, a video camera, a personal computer, a head-mounted display, a rear-type or front-type projector, a fax machine with a display function, a digital camera finder, a portable TV , DSP devices, PDAs, electronic notebooks, electronic bulletin boards, advertising announcement displays, and the like.

<Integrated circuit>
FIG. 6 is a diagram showing a configuration of a memory cell array which is an embodiment of an integrated circuit according to the present invention. The memory cell array shown in FIG. 6 includes an SRAM memory cell 41 having two store nodes N1 and N2, a write / read circuit 42 that writes data to the memory cell 41 and reads data from the memory cell 41, and A read circuit 43 that reads data from the memory cell 41 in a separate system and a word line drive circuit 44 that drives a word line when writing or reading data are included.

  Memory cell 41 includes inverting circuits INV1 and INV2 and N-channel MOS transistors QN1 and QN2 that constitute one port as a whole. The inverting circuit INV1 has an input connected to the first store node N1 and an output connected to the second store node N2. The inverting circuit INV2 has an input connected to the second store node N2 and an output connected to the first store node N1. The source-drain path of the transistor QN1 is connected between the first store node N1 and the bit line BLa. The source-drain path of the transistor QN2 is connected between the second store node N2 and the bit line BLb. The gates of the transistors QN1 and QN2 are connected to the word line WL.

  The memory cell array has a configuration to which a semiconductor device having a structure in which a plurality of device layers according to the present invention are stacked is applied. For example, a memory cell array having a structure in which a device layer in which a memory cell 41 is formed, a device layer in which a write / read circuit 42 is formed, and a device layer in which a word line driving circuit 44 is formed is stacked. Is done. With such a configuration, the chip area can be remarkably reduced as compared with the conventional one, so that the integration of the integrated circuit can be highly integrated, downsized, and the performance can be easily improved. It is possible to stabilize the initial characteristics and improve long-term reliability by optimizing the above.

<Electro-optical device>
FIG. 7 shows a circuit connection diagram in the electro-optical device 500 according to the present invention. The electro-optical device (display device) 500 according to this embodiment includes a light emitting layer OELD that can emit light by an electroluminescence effect in each pixel region, a storage capacitor that stores a current for driving the light emitting layer OELD, and thin film transistors T1 to T4. Configured. A scanning line Vsel and a light emission control line Vgp are supplied from the driver 501 to each pixel region. From the driver 502, a data line Idata and a power supply line Vdd are supplied to each pixel region. By controlling the scanning line Vsel and the data line Idata, current programming for each pixel region is performed, and light emission by the light emitting layer OELD can be controlled.

The electro-optical device 500 having the above-described configuration is configured by applying a semiconductor device having a structure in which a plurality of device layers according to the present invention are stacked. For example, by adopting a configuration in which the plurality of thin film transistors T1 to T4 are arranged in a plurality of device layers, the formation region of the switching element occupying the pixel region can be narrowed.
The drive circuit is an example of a circuit in the case where an electroluminescent element is used as a light emitting element, and other circuit configurations are possible. In addition, it is also preferable that an integrated circuit constituting each of the drivers 501 and 502 is formed by the semiconductor device according to the present invention.

<Electronic equipment>
FIG. 8 is a diagram illustrating a specific example of an electronic apparatus including the electro-optical device described above. FIG. 8A shows an application example to a mobile phone. The mobile phone 630 includes an antenna portion 631, an audio output portion 632, an audio input portion 633, an operation portion 634, and the electro-optical device 500 of the present invention. . As described above, the electro-optical device according to the invention can be used as a display unit of an electronic apparatus. FIG. 8B shows an application example to a video camera. The video camera 640 includes an image receiving unit 641, an operation unit 642, an audio input unit 643, and the electro-optical device 500 of the present invention. FIG. 8C illustrates an application example to a television, and the television 700 includes the electro-optical device 500 of the present invention. The electro-optical device according to the present invention can be similarly applied to a monitor device used for a personal computer or the like. FIG. 8D shows an application example to a roll-up television, and the roll-up television 710 includes the electro-optical device 500 of the present invention. Further, the electronic device is not limited to these, and can be applied to various electronic devices having a display function. For example, in addition to these, a fax machine with a display function, a finder for a digital camera, a portable TV, an electronic notebook, an electric bulletin board, a display for advertising, etc. are also included. The semiconductor device according to the present invention can be applied alone as a component part of an electronic device, in addition to being included in the electronic device as described above as a component part of the electro-optical device.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the gist of the present invention. For example, in the above-described embodiments, a silicon film is taken as an example of the semiconductor film, but the semiconductor film is not limited to this. In the above-described embodiments, a thin film transistor has been described as an example of a device formed using a crystallized semiconductor film. However, the device is not limited to this, and is a thin film diode, a capacitor, or the like. May be.

1 is a partial cross-sectional configuration diagram illustrating an outline of a semiconductor device according to a first embodiment. The top view which shows arrangement | positioning of a micropore similarly. Sectional process drawing for demonstrating a manufacturing method same as the above. Sectional process drawing for demonstrating a manufacturing method same as the above. The top view which shows arrangement | positioning of the micropore of the semiconductor device which concerns on 2nd Embodiment. FIG. 11 illustrates an example of an integrated circuit. FIG. 3 is a diagram illustrating an example of an electro-optical device. FIG. 9 illustrates a plurality of configuration examples of an electronic device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100,400 Semiconductor device, 101-103 device layer, 110 board | substrate layer, 211,221,231 origin part layer, 212,222,232 device formation layer, G10-G12, G100-G109 1st micropore (grain filter) , G20 to G23, G201 to G209 Second fine hole (grain filter), G30 to G32, G301 to G309 Third fine hole, C11 to C22 contact part, Q11, Q12 MOS transistor, Q13 to Q16 Thin film transistor (device) .

Claims (11)

A semiconductor device comprising a semiconductor film formed on a substrate,
A plurality of device layers each including a starting portion layer having a plurality of micropores on a surface and a device forming layer formed using a semiconductor film including substantially single crystal grains formed using the micropores as a starting point; And
2. The semiconductor device according to claim 1, wherein the micro hole belonging to an arbitrary device layer is formed at a position spaced apart from the micro hole belonging to another device layer disposed adjacently in plan view. The semiconductor device according to claim 1,
A device having the semiconductor film belonging to an arbitrary device forming layer is formed at a position separated from the microhole in a region surrounded by the microhole belonging to the device layer. . The semiconductor device according to claim 2,
The semiconductor device according to claim 1, wherein a planar distance between the device in the device layer and the fine hole surrounding the device is at least five times the minimum design rule of the device. The semiconductor device according to any one of claims 1 to 3,
The plurality of device layers include a first device layer and a second device layer having substantially the same planar arrangement of the micropores,
Between the first device layer and the second device layer, at least one device layer having a planar arrangement of the micropores different from that of the first device layer and the second device layer is provided. A semiconductor device. The semiconductor device according to any one of claims 1 to 4,
2. A semiconductor device according to claim 1, wherein the arrangement form and arrangement interval of the micropores in each device layer are substantially the same. The semiconductor device according to claim 5,
2. The semiconductor device according to claim 1, wherein the micro holes are arranged at equal intervals on the left, right, and top in a plan view. The semiconductor device according to claim 5,
2. The semiconductor device according to claim 1, wherein the micro holes are arranged so that all the micro holes adjacent in a plan view are equally spaced. The semiconductor device according to any one of claims 1 to 7,
The semiconductor device is characterized in that the arrangement interval of the micropores in each device layer is not less than 0.5 μm and not more than 3 μm. The semiconductor device according to claim 8,
The semiconductor device is characterized in that the arrangement interval of the micropores in each device layer is 1 μm or more and 2 μm or less.   An integrated circuit comprising the semiconductor device according to claim 1.   An electronic apparatus comprising the semiconductor device according to claim 1.

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