JP2007243667A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of flexibly coping with various generation modes of pulses. <P>SOLUTION: After receiving a pulse of an external clock signal CLK, for example, a reference pulse signal RPUL with a narrower pulse width than the external clock signal is generated, and the RPUL is circulated in a delay ring part DLYRG to which a unit delay block DLYBK is connected in a ring shape. Using output signals OUT [1] to [n], from each unit delay block DLYBK [1] to [n] an internal pulse signal IPUL with a predetermined pulse width is continuously generated. Furthermore, the number of times of the generation of the OUT[1] to [n] is counted, and a stoppage signal STP is generated, when the predetermined number of times is reached. The STP is supplied to the DLYRG to stop the circulation of the RPUL. As a result, the number of times of the generation of the IPUL can be set. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device including a circuit that generates an internal clock faster than an external clock.

  According to a study by the present inventor, the following can be considered as the technology of the clock generation circuit.

  For example, Patent Document 1 is a device that compensates for a skew between an external clock and an internal clock, and includes a configuration in which unit delay elements are arranged in a ring shape and a pulse generated at the rising edge of the internal clock is rotated in the ring. A clock signal delay device is shown. This ring is for setting the delay time. The delay time is roughly set from the count result of the number of rotations of the pulse in the ring, and the delay time is finely set from the position where the pulse stops in the ring. Is called. When such a configuration is used, the number of unit delay elements can be reduced.

Patent Document 2 discloses a ring register control type delay locked loop including a configuration in which unit delay elements are arranged in a ring shape as in Patent Document 1. This ring generates an output clock by delaying the input clock according to the phase detection result of the input clock and the output clock. Specifically, an output clock is generated by delaying the input clock by determining the incident position and rotation speed within the ring of the input clock according to the phase detection result. When such a configuration is used, the number of unit delay elements can be reduced, and a small-area delay locked loop (DLL) can be realized.
JP-A-11-306759 JP 2003-69424 A

  By the way, as a result of the study of the technique of the clock generation circuit as described above, the following has been clarified.

  Usually, the clock signal supplied to the semiconductor chip has a duty ratio of 50%. Such a clock signal having a uniform duty ratio is generated by a PLL (Phase Locked Loop) circuit, a DLL (Delay Locked Loop) circuit, or the like. However, such a clock signal maintains a duty ratio of 50% immediately after the PLL circuit or the like, but when transmitted through a clock tree inside the semiconductor chip, it is 50% due to factors such as process, power supply voltage, and temperature. It will shift from. Such a change in duty ratio occurs not only inside the semiconductor chip but also due to a transmission line on the mounting substrate, for example, outside the semiconductor chip. In recent years, the speed of clock signals has been increased, and with this increase in speed, changes in the duty ratio are becoming more prominent.

  On the other hand, the semiconductor chip generally generates an internal clock signal based on the supplied clock signal (external clock signal), and operates inside the semiconductor chip based on the internal clock signal. Many of such semiconductor chips generate an internal clock signal that is faster than an external clock signal and operate the semiconductor chip at a higher speed than the speed of the external clock signal. In such a semiconductor chip, for example, a system in which a PLL circuit or the like is mounted inside and an external clock signal is multiplied thereby to generate an internal clock signal is used. Such a method is useful for a logic semiconductor chip such as a CPU. For example, in a semiconductor chip such as a memory, a pulse signal having a certain pulse width is provided during one cycle of an external clock signal. There are cases where it is desired to generate an arbitrary number of times. In such a case, it is difficult to apply a method using a PLL circuit or the like.

  Therefore, for such a semiconductor chip, for example, a circuit as shown in FIG. 8 can be used. FIG. 8 shows an example of a clock generation circuit studied as a premise of the present invention, where (a) is a circuit diagram and (b) is an operation waveform diagram of (a). In the clock generation circuit of FIG. 8A, the internal clock signal CLKA is obtained by NAND operation and inversion of the output signal of the delay circuit DLY1 and the external clock signal CLK, which is a signal obtained by delaying and inverting the external clock signal CLK. Is generated. Further, the NAND circuit calculates and inverts the output signal of the delay circuit DLY2, which is a signal obtained by delaying and inverting the output signal of DLY1, and the output signal of the delay circuit DLY3, which is a signal obtained by further delaying and inverting the output signal of DLY2. Thus, the internal clock signal CLKB is generated.

  By using such a circuit, two internal clock signals CLKA and CLKB having a predetermined pulse width can be generated serially during one cycle of the external clock signal CLK as shown in FIG. 8B. At this time, the pulse widths of CLKA and CLKB can be adjusted by the delay times of DLY1 and DLY3, respectively, and the interval between CLKA and CLKB can be adjusted by the delay time of DLY2. However, in order to accurately adjust the pulse widths of CLKA and CLKB, it is necessary to secure the 'H' section of the external clock signal CLK longer than the section Tw of FIG. 8B. Then, if the duty ratio fluctuates due to various factors as described above and the 'H' section of the external clock signal CLK becomes short, a desired internal clock signal cannot be generated.

  Accordingly, one of the objects of the present invention is to provide a semiconductor integrated circuit device that can flexibly cope with various pulse generation specifications in view of such problems and the like. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor integrated circuit device according to the present invention includes a circuit that generates a reference pulse signal, a delay ring circuit that includes a plurality of delay circuits connected in a ring shape and circulates the input reference pulse signal, and a plurality of delay circuits. And a circuit for generating a second pulse signal having a desired pulse width using a plurality of phase pulse signals obtained from the output. The reference pulse signal is generated by receiving a first pulse signal such as a clock 'H' pulse signal, for example, and has a pulse width narrower than this pulse width.

  According to such a configuration, the second pulse signal having a desired pulse width can be continuously generated a plurality of times depending on the setting of the delay time of the delay circuit and which of the plurality of phase pulse signals is used. Become. Also, a reference pulse signal having a narrow pulse width is once generated from the clock, and the second pulse signal is generated by circulating this reference pulse signal. However, the duty ratio of the clock fluctuates in this reference pulse signal. However, since it can be generated easily or reliably, the second pulse signal can be generated stably regardless of fluctuations in the duty ratio of the clock. Therefore, a semiconductor integrated circuit device that can flexibly cope with various pulse generation specifications can be realized. Further, the area can be reduced by using the delay ring circuit.

  The semiconductor integrated circuit device according to the present invention further includes a counter circuit that outputs a stop signal when the number of generations of the pulse signals of a plurality of phases reaches a predetermined number in addition to the configuration described above, and a delay ring circuit However, in response to this stop signal, the circulation of the reference pulse signal is stopped. As a result, in addition to the pulse width of the second pulse signal described above, the number of occurrences can be controlled, so that it is possible to flexibly cope with various pulse generation specifications. Further, since the circulation of the reference pulse signal is stopped after the second pulse signal is generated a predetermined number of times, it is possible to suppress wasteful power consumption.

  In addition to the configuration as described above, the semiconductor integrated circuit device according to the present invention further includes a circuit that receives the first pulse signal and generates a reset signal, and the delay ring circuit receives the reset signal and receives a delay ring. Each node in the circuit is set to an initial state. As a result, unnecessary pulses that may be generated in the delay ring circuit can be removed before the reference pulse signal is circulated, thereby preventing malfunction and the like.

  A brief description of effects obtained by typical inventions among the inventions disclosed in the present application can realize a semiconductor integrated circuit device that can flexibly cope with various pulse generation specifications.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In the drawing, the PMOS transistor is distinguished from the NMOS transistor by adding a circle symbol to the gate. Further, in the drawing, the connection of the substrate potential of the MOS transistor is not specified, but the connection method is not particularly limited as long as the MOS transistor can operate normally.

(Embodiment 1)
FIG. 1 is a circuit block diagram showing an example of an outline of the configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIGS. 1 (a) to (d) show each component divided. Yes. First, the core of the configuration example of FIG. 1 is the circuit block of FIG. The circuit block in FIG. 1A includes, for example, a reference pulse generation circuit RPG that receives an external clock signal CLK and outputs a reference pulse signal RPUL, and a delay ring unit DLYRG that receives RPUL and cyclically adds a delay to the reference pulse generation circuit RPG. Composed.

  The reference pulse generation circuit RPG receives the external clock signal CLK and, for example, sets the pulse width of the “H” level that is sufficiently smaller than the pulse width of the “H” level (first pulse signal) of CLK to be as thin as possible. The provided reference pulse signal RPUL is output. The delay ring unit DLYRG includes n (n ≧ 2) unit delay blocks DLYBK [1] to [n] each connected in a ring shape. The reference pulse signal RPUL is input to DLYBK [1], the output of DLYBK [1] is serially input to DLYBK [2], DLYBK [3], ..., DLYBK [n], and the output of DLYBK [n] is DLYBK Returned to the input of [1]. Here, the outputs of DLYBK [1] to [n] are output signals OUT [1] to [n], respectively.

  Each of the unit delay blocks DLYBK [1] to [n] has a configuration as shown in FIG. The unit delay block DLYBK shown in FIG. 1B includes a 2-input NOR circuit NR and a delay circuit DLYA connected to the output thereof. The delay circuit DLYA delays and inverts the output of the NOR circuit NR, and when the reset signal RST or the stop signal STP is input, fixes a node of each circuit constituting the DLYA and fixes the output logic. Prepare. When such DLYBK is applied to DLYBK [1] to [n] in FIG. 1A, in DLYBK [1], the reference pulse signal RPUL is input to one of the NOR circuits NR and DLYBK [n] is input to the other. The output signal of the delay circuit DLYA is input, and the output signal of DLYBK [1] is input to one of the NRs of DLYBK [2]. Further, since the other NR of DLYBK [2] and the other NR of DLYBK [3] to [n] are fixed to the ground voltage GND, these NRs substantially function as an inverter circuit.

  The circuit block configured as shown in FIG. 1A receives a reference pulse signal (signal with a narrow pulse width) RPUL from the reference pulse generation circuit RPG to DLYBK [1]. The RPUL operates to circulate in the delay ring unit DLYRG. At this time, the input RPUL is sequentially output as output signals OUT [1], OUT [2],..., OUT [n], OUT [1],. That is, OUT [1] to [n] output multiple-phase pulse signals having different phases. The RPUL cycle in the delay ring unit DLYRG is stopped when the reset signal RST or the stop signal STP is input, and the logic of OUT [1] to [n] is fixed.

  The RPULs sequentially output in the output signals OUT [1] to [n] are input to circuit blocks as shown in FIGS. 1 (c) and 1 (d). FIG. 1C shows a pulse generation circuit IPG. The IPG has a desired pulse width using, for example, two (1 in some cases) of OUT [1] to [n]. An internal pulse signal (second pulse signal) IPUL provided with is generated. At this time, the IPUL is generated using the pulse width of IPUL and the interval between IPULs (IPUL generation cycle) using the delay time of unit delay block DLYBK and any phase in OUT [1] to [n]. It can be adjusted depending on how you do it.

  On the other hand, FIG. 1 (d) shows a counter circuit CUNT, which uses any one (single or plural) of OUT [1] to [n] to calculate the number of pulse generations. Count. Then, the CUNT outputs a stop signal STP when the number of pulse generations reaches a predetermined number. The stop signal STP is input to the delay ring unit DLYRG in FIG. 1A, whereby the RPUL cycle stops, and OUT [1] to [n] are fixed to a predetermined logic. Then, the pulse generation circuit IPG in FIG. 1C also stops generating the internal pulse signal IPUL.

  Note that the reset signal RST in FIGS. 1A and 1B is generated immediately after the power is turned on, for example, every time the external clock signal CLK is input. Accordingly, unnecessary pulses in the DLYRG can be removed before the reference pulse signal RPUL circulates in the delay ring unit DLYRG, and malfunction can be prevented. Further, if the delay time of each unit delay block DLYBK is configured to be sufficiently smaller than the period of CLK, the output signals OUT [1] to [n] are each output a plurality of times during one period of CLK. Accordingly, the internal pulse signal IPUL can be generated a plurality of times during one CLK period. When the next CLK is input, DLYRG is once reset and the same operation is performed again.

  With the configuration and operation as described above, for example, the internal pulse signal IPUL having a predetermined pulse width can be generated a predetermined number of times within one cycle of the external clock signal CLK. At this time, since the delay ring part DLYRG as shown in FIG. 1A is used, the circuit area can be reduced. That is, for example, when it is desired to increase the number of occurrences of the internal pulse signal IPUL, in the configuration as shown in FIG. 8A, it is necessary to add delay circuits DLY in a corresponding amount, but the delay ring unit DLYRG does not need that. .

  Furthermore, even when the duty ratio of the external clock signal CLK varies, it is not affected. That is, in FIG. 1A, the reference pulse signal RPUL having the narrowest possible pulse width is generated from the external clock signal CLK by the reference pulse generating circuit RPG. Since this RPUL may have a narrow pulse width, Even if the duty ratio fluctuates relatively large, it can be generated without any problem. Since the internal pulse signal IPUL is generated based on the stably generated RPUL, the IPUL can be stably generated without being affected by the duty ratio of the clock signal CLK.

  FIG. 2 is a circuit diagram showing an example of the detailed configuration of FIGS. 1 (a) and 1 (b). FIG. 3 is a circuit diagram showing an example of the detailed configuration of FIGS. 1 (c) and 1 (d). FIG. 4 is a waveform diagram showing an example of the operation of FIG. 2 and FIG. In FIG. 2, the reference pulse generation circuit RPG and the delay ring unit DLYRG described above and a generation circuit for the reset signal RST are shown as other circuits. The reference pulse generation circuit RPG includes, for example, inverter circuits INV20 to INV22, a NAND circuit ND20, and two delay circuits DLY4 and DLY5 each including five stages of inverter circuits. An external clock signal CLK is input to INV20. The output of INV20 becomes one input of ND20 through INV21, and the other signal from INV20 is input through DLY4 and DLY5 to the other of ND20. Then, the reference pulse signal RPUL is generated from the output of the ND 20 via the INV 22.

  Further, the output of INV20 and the output of DLY4 are input to the NOR circuit NR20, the output of NR20 is connected to one input of the NOR circuit NR21, and the inverted reset signal RSTB is generated from the output of NR21. The output of the NAND circuit ND21 is connected to the other input of the NR21, the ring activation signal RINGEN is connected to one input of the ND21, and the inverted signal PS1B of the operation selection signal PS is connected to the other input of the ND21. Is connected. An internal clock activation signal ICKEN is generated from the output of ND21 through an inverter circuit.

  Here, for example, the delay ring unit DLYRG includes four unit delay blocks DLYBK [1] to [4]. Similar to the description in FIG. 1A, the reference pulse signal RPUL is connected to one input of the NOR circuit NR [1] of DLYBK [1], and the other input of NR [1] is connected to DLYBK. The output of [4] (that is, output signal OUT [4]) is connected. The unit delay block DLYBK [1] includes a NOR circuit NR [1] and a delay circuit DLYA connected to the output thereof. In the delay circuit DLYA, the output of NR [1] is connected to one input of the NAND circuit ND1 [1] via an inverter circuit, and the output of ND [1] is connected to the NAND circuit ND2 [ 1], and the output of ND2 [1] is connected to DLYBK [2] via an inverter circuit.

  The unit delay blocks DLYBK [2] to [4] have the same configuration as that of DLYBK [1]. As described with reference to FIG. 1A, the NOR circuits NR [2] to [4] included in each of the unit delay blocks DLYBK [2] to [4] ] Is connected to the ground voltage GND, and the other input is connected to the output from the previous unit delay block DLYBK. Further, here, NAND circuits ND1 [1], ND2 [1], ND1 [3], ND2 [3], ND1 [4] included in each of DLYBK [1], [3], [4]. ], ND2 [4] is connected to the other reset input signal RSTB. On the other hand, a state signal STATE4B corresponding to the stop signal STP described in FIG. 1A is connected to the other inputs of the two NAND circuits ND1 [2] and ND2 [2] included in DLYBK [2]. Yes.

  FIG. 3 shows the above-described pulse generation circuit IPG, counter circuit CUNT, and the like. Here, the pulse generation circuit IPG includes an RS latch circuit including two three-input NAND circuits ND30 and ND31. One of the three inputs of the ND30 is connected to an output obtained by NANDing the output signal OUT [1] of the DLYBK [1] in FIG. 2 and the internal clock activation signal ICKEN (“H” level when activated). The other one is connected to the output of ND31. The remaining one is connected to a circuit that outputs the “H” level via the PMOS transistor MP30 when the operation selection signal PS is “L” level (external CLK through mode OFF), and the operation selection signal PS is “H”. When it is at level (external CLK through mode ON), it is connected to the external clock signal CLK2D. Therefore, if the external CLK through mode ON is selected, the RS latch circuit including ND30 and ND31 is controlled by CLK2D, and the CLK2D signal is transmitted to IPUL. On the other hand, one of the three inputs of the ND 31 is connected to an inverted signal of the output signal OUT [3] of the DLYBK [3] in FIG. 2, and the other one is connected to the output of the ND 30 and the remaining 1 One is connected to the inverted reset signal RSTB. Then, an internal pulse signal IPUL is generated from the output of the ND 30.

  Here, in consideration of high speed, the counter circuit CUNT uses four-stage through latch circuits LT1 to LT4. LT1 latches the data input D using the inverted reset signal RSTB as the data input D and the output signal OUT [2] of DLYBK [2] in FIG. 2 as the clock input CK. LT2 latches the data input D using the output of LT1 as the data input D and the output signal OUT [4] of DLYBK [4] of FIG. 2 as the clock input CK. LT3 latches the data input D using the output of LT2 as the data input D and the output signal OUT [2] of DLYBK [2] of FIG. 2 as the clock input CK. LT4 latches the data input D using the output of LT3 as the data input D and the output signal OUT [3] of DLYBK [3] in FIG. 2 as the clock input CK. Then, an inverted signal of the output of LT4 is connected to DLYBK [2] in FIG. 2 as a state signal (stop signal) STATE4B. Further, when LT1 to LT4 receive the reset signal RST, the data output is reset to the 'L' level.

  The circuits shown in FIGS. 2 and 3 operate as shown in FIG. 4, for example. As shown in FIG. 4, the circuits of FIGS. 2 and 3 are main circuits that generate two internal clock signals ICLKA and ICLKB having a certain pulse width, for example, during one cycle of the external clock signal CLK. Has become a department. At this time, ICLKB has a specification that occurs after a fixed time has elapsed from ICLKA. Note that the circuit that finally outputs ICLKA and ICLKB is not an essential part of the present invention, and is omitted in FIGS.

  In FIG. 4, first, the external clock signal CLK is input in a state where the operation selection signal PS is at the “L” level and the ring activation signal RINGEN is at the “H” level. The reference pulse generation circuit RPG in FIG. 2 receives this CLK and generates a reference pulse signal RPUL, and the NOR circuit NR20 in FIG. 2 generates a reset signal RST. At this time, the pulse width of RPUL is substantially equal to the sum of the delay times of the delay circuits DLY4 and DLY5, and the pulse width of RST is substantially equal to the delay time of DLY4. FIG. 4 shows an example in which the duty ratio of the external clock signal CLK is biased. Even in such a case, the delay time of DLY4 and DLY5 is sufficiently shorter than the pulse width ('H' level) of CLK. By doing so, the RPUL pulse width is not affected. That is, there is no problem unless the CLK pulse width is shorter than the delay time of DLY4 and DLY5.

  The reset signal RST (inverted reset signal RSTB) is input to DLYBK [1], [3], [4] in the delay ring unit DLYRG of FIG. 2, and this may cause unnecessary pulses that may be generated in DLYRG. Is removed. This operation is performed while RST is at the “H” level (RSTB is at the “L” level). Accordingly, the logic of each node in DLYBK [1], [3], [4] is fixed, and the output signal OUT [1], [3], [4] are fixed to the 'L' level. The output signal OUT [2] is also fixed to the “L” level by transmitting the “L” level of OUT [1].

  In this way, pulses in DLYRG are removed and RST returns to the 'L' level, while the reference pulse signal RPUL is input to the NOR circuit NR [1] of DRYBK [1]. This RPUL becomes the output signal OUT [1] after the delay time of DLYBK [1], and then becomes the output signal OUT [2] after the delay time of DLYBK [2]. [3] and [4] are obtained. Thereafter, OUT [4] is fed back to DLYBK [1], and similarly, output signals OUT [1] to [4] having different phases in units of delay times of the unit delay blocks are obtained.

  Here, OUT [1] and OUT [3] are input to the pulse generation circuit (RS latch) IPG of FIG. 3, and an internal pulse signal IPUL rising at OUT [1] and falling at OUT [3] is obtained. On the other hand, in the through latch circuits LT1 to LT4 of FIG. 3, the respective data outputs STATE1 to STATE4 are set to ‘L’ level by RST, and thereafter, the data output STATE1 of LT1 is set to ‘H’ level by OUT [2]. Thereafter, the data outputs STATE 2, 3, 4 of LT 2, 3, 4 are sequentially set to the “H” level by OUT [4], [2], [3].

  When the data output STATE4 becomes 'H' level, the inverted data output STATE4B is input to DLYBK [2] in FIG. Then, the output logic of the NAND circuits ND1 [2] and ND2 [2] provided near the entrance and near the exit in the DLYBK [2] is fixed to the “H” level, and accordingly, ND1 [2] and ND2 [2 ] Is also fixed, and the output signal OUT [2] is fixed to the “L” level. As a result, pulse transmission after DLYBK [2] is stopped, and OUT [3], [4] also maintain the 'L' level. In addition, after OUT [2] is fixed to the “L” level, output signal OUT [1] for one time is generated in DLYBK [1] before DLYBK [2]. Is not transmitted after DLYBK [2], and the pulse cycle in DLYRG is completely stopped. When the next external clock signal CLK is input, the reset signal RST and the reference pulse signal RPUL are generated in the same manner, and the pulse circulation is performed again.

  The internal clock signals ICLKA and ICLKB shown in FIG. 4 can be generated using the internal pulse signal IPUL and data outputs (state signals) STATE1 to STATE4, although the circuit is not shown. For example, ICLKA only needs to output IPUL in a section where STATE2 is at ‘L’ level, and ICLKB only needs to output IPUL in a section where STATE2 is at ‘H’ level and STATE4 is at ‘L’ level.

  2 and 3 are examples of the configuration of FIG. 1 and, of course, are not limited to the circuits as shown in FIGS. For example, in FIG. 3, the number of stages of the through latch circuit LT and the output signals OUT [1] to [4] according to the width and number of pulses to be generated within one cycle of the external clock signal CLK and various timing margins. ] May be changed. In some cases, for example, an edge trigger counter circuit is used instead of the through latch circuit LT, and a pulse circulation stop signal is simply generated after counting a predetermined number of generations of a predetermined output signal. The method may be used. In FIG. 2, for example, the OR output of the inverted reset signal RSTB and the data output (stop signal) STATE4B can be input to each unit delay block DLYBK [1] to [4]. Of course, it is also possible to change the types of logic operation elements (NAND circuits and NOR circuits) in the DLYBK by changing the polarities of RPUL and RST.

  As described above, by using the semiconductor integrated circuit device according to the first embodiment of the present invention, for example, an internal clock signal having a predetermined pulse width is generated a predetermined number of times within one cycle of the external clock signal. It is possible to flexibly cope with various pulse generation specifications. In addition, the circuit area can be reduced. Furthermore, a stable internal clock signal can always be generated without depending on the duty ratio of the external clock signal.

(Embodiment 2)
In the second embodiment, a configuration example and an operation thereof are assumed assuming that the circuit shown in FIGS. 2 and 3 described in the first embodiment is applied to a memory circuit such as an SRAM (Static Random Access Memory). An example will be described. FIG. 5 is a circuit block diagram showing an example of a schematic configuration of a semiconductor integrated circuit device according to the second embodiment of the present invention. FIG. 6 is a waveform diagram showing an operation example of the semiconductor integrated circuit device of FIG.

  The semiconductor integrated circuit device shown in FIG. 5 includes, for example, an internal clock generation circuit ICLK_GEN, a decoder circuit DEC, an address latch circuit ADD_LT, a data input / output circuit DIO, a memory array MEM_ARY, and the like. The internal clock generation circuit ICLK_GEN includes, for example, the circuits of FIGS. 2 and 3 as described above, and receives the external clock signal CLK and outputs the internal clock signal CLKI <1: 0>. The address latch circuit ADD_LT receives external address signals ADRA, ADRB and CLKI <1: 0> and outputs an internal address signal ADRI.

  The decoder circuit DEC receives ADRI and outputs a memory cell selection signal WD. The data input / output circuit DIO receives an external data input signal DIN or CLKI <1: 0>, outputs an internal data input signal DINI, receives an internal data output signal DOUTI, and outputs an external data output signal DOUT. . The memory array MEM_ARY includes a plurality of SRAM memory cells arranged in an array, receives WD and DINI, and outputs DOUTI.

  Such a semiconductor integrated circuit device operates as shown in FIG. 6, for example. First, when the external clock signal CLK is input, the internal clock signal CLK <0> is generated by the internal clock generation circuit ICLK_GEN during one period of CLK, and the internal clock signal CLK <1> is generated after a certain period of time. Generated. When the internal clock signal is generated, the circuit as shown in FIGS. 2 and 3 is operated as shown in FIG. 4, and ICLKA in FIG. 4 corresponds to CLK <0> and ICLKB is set to CLK <1. It corresponds to>.

  At the rising edge of CLK, external address signals ADRA and ADRB are input to the address latch circuit ADD_LT, and these signals are latched by ADD_LT. The ADD_LT outputs the latched address signal to the decoder circuit DEC as the internal address signal ADRI at the timing of CLK <0> and CLK <1>, respectively. The DEC decodes each ADRI and outputs the memory cell selection signal WD (WD 'H' pulse) to the memory array MEM_ARY twice during one CLK period.

  When CLK rises, in addition to ADRA and ADRB, an external data input signal DIN is input to the data input / output circuit DIO, and the DIO latches this DIN. In FIG. 6, it is assumed that the read / write operation is performed within one cycle of CLK, and the memory array MEM_ARY receives the first WD and reads data from the corresponding memory cell. It is output to DIO as an internal data output signal DOUTI. The DIO latches DOUTI using the timing of CLK <0> and outputs it as an external data output signal DOUT.

  In parallel with the output of DOUT, the DIO outputs the latched DIN to the memory array MEM_ARY as the internal data input signal DINI at the timing of CLK <1>. At this time, in addition to DINI, the second WD is input to MEM_ARY. In MEM_ARY, DINI is written to the memory cell selected by this WD.

  As described above, by using the semiconductor integrated circuit device according to the second embodiment of the present invention, a memory circuit having various effects as described in the first embodiment can be realized. In addition, for example, in an SRAM or the like, particularly high speed is required. Therefore, even when the SRAM is mounted inside a CPU or the like, or when the SRAM is mounted as a single unit on a dielectric substrate, the duty of the external clock signal CLK is increased. The ratio can fluctuate significantly. Even in such a case, the memory operation can be surely performed by using the semiconductor integrated circuit device as shown in FIG.

(Embodiment 3)
The third embodiment will be described assuming that the circuit shown in FIG. 1 described in the first embodiment is applied to, for example, a non-pipeline type divider. FIG. 7 is an explanatory diagram showing a configuration example and an operation example in the semiconductor integrated circuit device according to the third embodiment of the present invention. FIG. 7 shows a schematic configuration of a non-pipeline type divider. The non-pipelined divider is, for example, a hardware implementation of an algorithm that performs floating-point division. In the outline of the configuration and operation, first, when a given divisor or dividend is a denormalized number, normalization is performed using a barrel shifter. Next, subtraction between exponent parts and division between mantissa parts are performed, normalization and rounding are performed, and a quotient is output. In addition, exception processing such as when a quotient code is generated or the divisor is 0 is also performed.

  Here, when dividing the mantissa parts, it is known to use a method called a subtraction shift method. When this subtraction shift method is realized by hardware, as shown in FIG. 7, a process for performing a subtraction shift three times by a sequential circuit is performed eight times. As a circuit for controlling such a tour, it is beneficial to use the circuit as shown in FIG. That is, for example, when an external clock signal is input, an internal clock signal having the same pulse width is generated eight times during one cycle of the external clock signal, and a subtraction shift is performed three times based on the internal clock signal. Operate the circuit.

  Thus, by using the semiconductor integrated circuit device according to the third embodiment of the present invention, a divider having various effects as described in the first embodiment can be realized. In a non-pipeline type divider, the calculation speed is usually governed by the speed of the external clock signal, so that it is difficult to maximize the speed performance of the divider circuit. . Therefore, if a circuit for generating a unique internal clock signal as described above is provided in the divider and the period of the internal clock signal is set to the maximum speed of the divider, generally a long time is required. Floating point division processing can be performed at high speed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The semiconductor integrated circuit device of the present invention can be widely applied to all devices that need to generate a pulse signal having a predetermined pulse width a predetermined number of times, and in particular, high speed and small area. This is useful when applied to a memory circuit, a high-speed logic circuit, or the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram showing an example of a configuration outline of a semiconductor integrated circuit device according to a first embodiment of the present invention, and (a) to (d) show each component divided. It is a circuit diagram which shows an example of the detailed structure of Fig.1 (a), (b). It is a circuit diagram which shows an example of the detailed structure of FIG.1 (c), (d). FIG. 4 is a waveform diagram showing an example of the operation of FIGS. 2 and 3. In the semiconductor integrated circuit device by Embodiment 2 of this invention, it is a circuit block diagram which shows an example of the structure outline | summary. FIG. 6 is a waveform diagram showing an operation example of the semiconductor integrated circuit device of FIG. 5. FIG. 11 is an explanatory diagram showing a configuration example and an operation example in a semiconductor integrated circuit device according to a third embodiment of the present invention. 1 shows an example of a clock generation circuit studied as a premise of the present invention, where (a) is a circuit diagram and (b) is an operation waveform diagram of (a).

Explanation of symbols

ADD_LT Address latch circuit ADRA, ADRB External address signal ADRI Internal address signal CK Clock input CLK, CLK2D External clock signal CUNT counter circuit D Data input DEC Decoder circuit DIN External data input signal DINI Internal data input signal DIO Data input / output circuit DKYBK Unit delay Block DKYRG delay ring unit DLY, DLYA delay circuit DOUT external data output signal DOUTI internal data output signal GND ground voltage ICLK_GEN internal clock generation circuit ICLKA, ICLKB, CLKI internal clock signal INV inverter circuit IPG pulse generation circuit LT through latch circuit MEM_ARY memory array MP PMOS transistor ND NAND circuit NR NOR circuit OU T output signal PS operation selection signal RINGN ring activation signal RPG reference pulse generation circuit RPUL reference pulse signal RST reset signal STATE state signal STP stop signal WD memory cell selection signal

Claims (10)

A circuit for receiving a first pulse signal input from the outside and generating a reference pulse signal having a pulse width narrower than a pulse width of the first pulse signal;
A delay ring circuit comprising a plurality of delay circuits connected in a ring shape, wherein when the reference pulse signal is input, the input reference pulse signal is circulated through the plurality of delay circuits;
A circuit for generating a second pulse signal having a desired pulse width by using a plurality of phase pulse signals obtained from outputs of the plurality of delay circuits in association with circulation of the reference pulse signal. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1.
Furthermore, the counter circuit that counts the number of occurrences of the pulse signals of the plurality of phases and outputs a stop signal when the number of occurrences reaches a predetermined number of times,
The delay ring circuit has means for stopping the circulation of the reference pulse signal in response to the stop signal. The semiconductor integrated circuit device according to claim 1.
And a circuit for receiving the first pulse signal and generating a reset signal,
The delay ring circuit has means for receiving the reset signal and setting a node of each circuit included in the delay ring circuit to an initial state. The semiconductor integrated circuit device according to claim 2.
The counter circuit further generates a state signal that changes its state in time series using the plurality of phase pulse signals,
The circuit for generating the second pulse signal generates the second pulse signal by using the plurality of phase pulse signals and the state signal. A circuit for receiving a first pulse signal input from the outside and generating a reference pulse signal having a pulse width narrower than a pulse width of the first pulse signal;
A circuit for receiving the first pulse signal and generating a reset signal;
A delay ring circuit comprising a plurality of stages of delay circuits connected in a ring, and circulating while delaying the reference pulse signal;
A circuit for generating a second pulse signal having a desired pulse width by using a plurality of phase pulse signals obtained from the output of each stage in the plurality of stages of delay circuits;
A counter circuit that counts a plurality of phase pulse signals obtained from the output of each stage in the plurality of stages of delay circuits;
A logic operation element having a plurality of inputs is provided at the input of the first-stage delay circuit, which is one of the plurality of delay circuits,
The reference pulse signal is input to one of the plurality of inputs,
The other one of the plurality of inputs receives an output from a delay circuit at the final stage, which is another one of the plurality of delay circuits.
2. The semiconductor integrated circuit device according to claim 1, wherein the delay ring circuit has means for receiving the reset signal or the output signal from the counter circuit and setting each node of the plurality of stages of delay circuits to an initial state. The semiconductor integrated circuit device according to claim 5.
The circuit for generating the reference pulse signal generates the reference pulse signal using a logical operation of the first pulse signal and a pulse signal obtained by delaying the first pulse signal. apparatus. The semiconductor integrated circuit device according to claim 5.
The circuit that generates the second pulse signal uses two pulse signals from the plurality of phase pulse signals, forms a rising edge of the second pulse signal with one pulse signal, and generates the second pulse signal with the other pulse signal. A semiconductor integrated circuit device comprising a latch circuit for forming a falling edge of a second pulse signal. The semiconductor integrated circuit device according to claim 5.
Each of the plurality of stages of delay circuits includes:
A first logic operation element and a second logic operation element, wherein one of a plurality of inputs is connected to the reset signal or an output signal from the counter circuit;
An odd number of inverter circuits connected in series between the first logic operation element and the second logic operation element;
2. A semiconductor integrated circuit device according to claim 1, wherein each node of the plurality of stages of delay circuits is set to an initial state in response to input of the reset signal or an output signal from the counter circuit. A delay ring circuit that is connected to each other in a ring shape and circulates while delaying the pulse signal;
And a circuit for generating a pulse signal having a desired pulse width using a plurality of pulse signals extracted from different nodes in the delay ring circuit. The semiconductor integrated circuit device according to claim 9.
The semiconductor integrated circuit device further comprises a circuit for stopping the circulation of the pulse signal in the delay ring circuit when the generated pulse signal is generated a predetermined number of times.

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