JP4071873B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a DLL (Delayed Locked Loop) circuit.
In recent years, semiconductor integrated circuit devices have been increased in speed and integration, and it has become necessary to supply a clock signal whose phase is synchronized to a predetermined circuit. Specifically, for example, in a synchronous DRAM (SDRAM), a signal that is phase-synchronized with an external clock signal using a DLL (Delay Locked Loop) circuit is supplied to a plurality of output buffer circuits. Yes. In order for the DLL circuit to cope with a high frequency, a highly accurate digital DLL circuit is required.
[0002]
[Prior art]
FIG. 1 is a block diagram showing an example of a conventional DLL circuit. In the figure, an external clock signal input from the outside via a clock input pad 150 is supplied to a delay circuit 154 and a frequency divider 156 as a real clock through an input circuit 152 functioning as a buffer. The frequency divider 156 divides the external clock signal by, for example, a division ratio of 2/8, a high level H for two cycles of the external clock signal, and a low level L dummy clock Z for six cycles, A reference clock X having a high level H for six cycles at a low level L for two cycles of the inverted external clock signal is generated.
[0003]
The reference clock X is supplied to the phase comparator 158, and the dummy clock Z is delayed through the dummy delay circuit 160 and the dummy circuit 162 and then supplied to the phase comparator 158. The dummy circuit 162 is the same circuit as the input circuit 152 and the output circuit 168. The phase comparator 158 compares the phase of the dummy clock Z delayed from the dummy circuit 162 with the reference clock X, generates a phase difference signal, and supplies the phase difference signal to the delay control circuit 164. The delay control circuit 164 controls the delay amount of the dummy delay circuit 160 in such a direction that the phase difference disappears based on the phase difference signal. Thus, the delayed dummy clock Z rises so that the rising edge of the reference clock X coincides with the rising edge of the reference clock X, that is, the delayed dummy clock Z is k cycles of the external clock signal with respect to the reference clock X (here k = 2). ) The delay amount of the dummy delay circuit 160 is variably controlled so as to be delayed.
[0004]
By the way, the delay circuit 154 to which the real clock is supplied has the same configuration as the dummy delay circuit 160, and is controlled by the delay control circuit 164 so as to have the same delay amount as the dummy delay circuit 160, and is delayed by the delay circuit 154. The real clock is supplied to the output circuit 168. The output circuit 168 buffers the data on the data bus in synchronization with the real clock and outputs it from the data output pad 170.
[0005]
Here, since the dummy circuit 162 is the same circuit as the input circuit 152 and the output circuit 168, in the state where the delayed dummy clock Z is delayed by k cycles of the external clock signal with respect to the reference clock X, the data output pad Data output from 170 is synchronized with an external clock signal input to the clock input pad 150.
[0006]
Incidentally, the output circuit 168 may require the real clock and an inverted real clock obtained by inverting the real clock. This is a case where the DRAM that supplies read data to the output circuit 168 performs high-speed access that apparently doubles the access speed by reading data in synchronization with the real clock and the inverted real clock. In such a case, in the circuit of FIG. 1, an inverted real clock is generated by using an inverter in the output circuit 168, but in addition to this, a DLL circuit shown in FIG. 2 is conventionally used.
[0007]
FIG. 2 is a block diagram showing another example of a conventional DLL circuit. In the figure, an external clock signal input from the outside via a clock input pad 200 is supplied to a ½ frequency divider 203 through an input circuit 202 functioning as a buffer. The 1/2 divider 203 divides the external clock signal by 1/2 to generate a divided clock, and the delay circuit 205 and the divider 206 of the 180 degree DLL block 204 and the delay of the 0 degree DLL block 234 The circuit 235 and the frequency divider 236 are supplied.
[0008]
The frequency divider 206 of the 180-degree DLL block 204 divides the frequency-divided clock by, for example, a division ratio of 1/8, and is a dummy having a high level H for one cycle of the external clock signal and a low level L for seven cycles. A clock Z and a reference clock X having a high level H for seven cycles at a low level L for one cycle of the external clock signal obtained by inverting the clock Z are generated.
The reference clock X is supplied to the phase comparator 208, and the dummy clock Z is delayed through the dummy delay circuit 220 and the dummy delay circuit 221 and then supplied to the phase comparator 208. The dummy circuit 212 is the same circuit as the input circuit 202 and the output circuit 218. The phase comparator 208 compares the phase of the delayed dummy clock Z from the dummy circuit 212 with the reference clock X, generates a phase difference signal, and supplies the phase difference signal to the delay control circuit 214. The delay control circuit 214 controls the delay amounts of the dummy delay circuits 210 and 211 in a direction in which the phase difference disappears based on the phase difference signal. Thus, the delayed dummy clock Z rises so that the rising edge of the reference clock X coincides with the rising edge of the reference clock X, that is, the delayed dummy clock Z is k cycles of the external clock signal with respect to the reference clock X (here k = 2). ) The delay amounts of the dummy delay circuits 210 and 211 are variably controlled so as to be delayed by an amount equivalent to.
[0009]
The delay circuit 205 to which the divided clock is supplied has the same configuration as the dummy delay circuits 210 and 211, and is controlled by the delay control circuit 214 so as to have the same delay amount as the dummy circuit 212. In contrast to being delayed by the dummy delay circuits 210 and 211, the divided clock is delayed by 180 degrees because it is delayed by the delay circuit 205 of one stage, and the divided clock delayed by 180 degrees is This is supplied to the delay circuit 215 of the 0-degree DLL block 234.
[0010]
The frequency divider 236 of the 0-degree DLL block 234 divides the frequency-divided clock by, for example, a division ratio of 1/8, and is a dummy having a high level H for one cycle of the external clock signal and a low level L for seven cycles. A clock Z and a reference clock X having a high level H for seven cycles at a low level L for one cycle of the external clock signal obtained by inverting the clock Z are generated.
The reference clock X is supplied to the phase comparator 238, and the dummy clock Z is delayed through the dummy delay circuit 240 and the dummy circuit 242 and then supplied to the phase comparator 238. The dummy circuit 242 is the same circuit as the input circuit 202, the 1/2 frequency divider circuit 203, and the output circuit 218. The phase comparator 238 performs phase comparison between the delayed dummy clock Z from the dummy circuit 242 and the reference clock X, generates a phase difference signal, and supplies the phase difference signal to the delay control circuit 244. The delay control circuit 244 controls the delay amount of the dummy delay circuit 240 in such a direction that the phase difference disappears based on the phase difference signal. Thereby, the dummy clock Z is delayed so that the rise of the delayed dummy clock Z coincides with the rise of the reference clock X, that is, the delayed dummy clock Z is delayed from the reference clock X by k cycles of the external clock signal. The delay amount of the delay circuit 240 is variably controlled.
[0011]
By the way, the delay circuit 215 supplied with the divided clock delayed by the delay circuit 205 and the delay circuit 235 supplied with the divided clock from the 1/2 divider circuit 203 have the same configuration as the dummy delay circuit 240. The delay control circuit 244 controls the delay amount to be the same as that of the dummy delay circuit 240, and the divided clock (0 degree clock) delayed 360 degrees from the delay circuit 235 is supplied to the output circuit 218 as a real clock. The frequency-divided clock (180-degree clock) delayed by 540 degrees from the delay circuit 215 is supplied to the output circuit 218 as an inverted real clock. The output circuit 218 buffers the data on the data bus in synchronization with the real clock and the inverted real clock and outputs the data from the data output pad 220.
[0012]
[Problems to be solved by the invention]
When the inverted real clock is generated by the inverter in the output circuit 118 using the conventional circuit of FIG. 1, the inverted real clock rises with a delay of one stage of the inverter. There is a problem that the signals are not different in phase by 180 degrees.
[0013]
The conventional circuit of FIG. 2 has a 180-degree DLL block 204 and a 0-degree DLL block 234, and has delay circuits 205, 215, 235, and dummy delay circuits 211, 240, so an increase in chip area is inevitable. . Further, the inverted real clock passes through the delay circuit more than the real clock, and there is a problem that it is more susceptible to power supply noise.
[0014]
The present invention has been made in view of the above points, and it is possible to prevent an increase in chip area, to be hardly affected by power supply noise, and to generate a clock and an inverted clock whose rising phase is accurately shifted by 180 degrees. An object of the present invention is to provide a semiconductor integrated circuit device that can be generated.
[0015]
[Means for Solving the Problems]
  The invention according to claim 1 divides the input clock signal by 1/2 to generate a first and second divided clock signals whose phases are shifted from each other by 180 degrees;A frequency divider that divides the first frequency-divided clock signal by a predetermined frequency division ratio and outputs a dummy clock and a reference clock that is an inverted signal thereof; a dummy delay circuit that delays the dummy clock; and a predetermined frequency A dummy circuit that delays the dummy clock output from the dummy delay circuit, a phase comparator that performs phase comparison between the dummy clock output from the dummy circuit and the reference clock, and A delay control circuit which is supplied with a phase difference to be output and controls a delay amount of the dummy delay circuit so as to eliminate the phase difference, and is controlled to be the same delay amount as the dummy delay circuit by the control of the delay control circuit; A first delay circuit that delays and outputs a divided clock signal; and the second delay clock is controlled by the delay control circuit to have the same delay amount as the dummy delay circuit. More becomes second delay circuit for outputting by delaying the issue,A DLL circuit that outputs each of the first and second divided clock signals by delaying the input clock signal by a predetermined phase.And have.
[0016]
  In this way, the input clock signal is divided by 1/2 to generate the first and second divided clock signals whose rising phases are shifted from each other by 180 degrees, and each of the input clock signals is predetermined with respect to the input clock signal by the DLL circuit. Since the output is delayed by the phase, only one DLL circuit is required, the increase in chip area can be prevented, and the number of delay circuits through which the first and second frequency-divided clock signals pass is small. It becomes difficult to receive.
The dummy clock obtained by dividing the first frequency-divided clock signal is delayed by the dummy delay circuit and the dummy circuit, and the phase comparison between the dummy clock and the reference clock is performed. In order to control the delay amount of the second delay circuit, the first and second divided clock signals whose rising phases are shifted by 180 degrees can be delayed by a predetermined phase with respect to the input clock signal.
[0017]
  Invention of Claim 2Then
  The 1/2 divider includes a first gate unit that gates an output complementary signal of a slave latch unit using the input clock signal;
  A master latch unit that receives and latches the output signal of the first gate unit;
  A second gate unit for gating the output complementary signal of the master latch unit with an inverted signal of the input clock signal;
  A slave latch unit that receives and latches the output signal of the second gate unit;
  The output complementary signal of the master latch unit is output as the first and second divided clock signals.
[0018]
In this way, the output complementary signal of the slave latch unit is gated by the input clock signal and latched by the master latch unit, and the output complementary signal of the master latch unit is gated by the inverted signal of the input clock signal and latched by the slave latch unit. Since the output complementary signal of the master latch unit is output, the rising phases of the first and second divided clock signals can be accurately shifted by 180 degrees.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3 shows a block diagram of an embodiment of the DLL circuit of the present invention. In the figure, an external clock signal input from the outside via the clock input pad 10 is supplied to the 1/2 frequency divider 30 through the input circuit 20 functioning as a buffer. The 1/2 divider 30 divides the external clock signal by 1/2, and the divided clock (first divided clock) and the inverted divided clock (second divided) whose phases are accurately shifted by 180 degrees from each other. Clock). The inverted divided clock is supplied to the delay circuit (second delay circuit) 41 of the 0 degree DLL block 40, and the divided clock is supplied to the delay circuit (first delay circuit) 42 and the divider 43 of the 0 degree DLL block 40. Is done.
[0022]
The frequency divider 43 of the 0-degree DLL block 40 divides the frequency-divided clock by, for example, a division ratio of 1/8, and is a dummy having a high level H for one cycle of the external clock signal and a low level L for seven cycles. A clock Z and a reference clock X having a high level H for seven cycles at a low level L for one cycle of the external clock signal obtained by inverting the clock Z are generated.
4A is supplied to the phase comparator 44, and the dummy clock Z as shown in FIG. 4B is delayed through the dummy delay circuit 45 and the dummy circuit 46. This is supplied to the phase comparator 44. The dummy circuit 46 is the same circuit as the input circuit 20, the ½ divider circuit 30 and the output circuit 50, and has the same delay amount. The phase comparator 44 performs phase comparison between the delayed dummy clock dZ from the dummy circuit 46 and the reference clock X from the phase comparator 44 as shown in FIG. This is supplied to the circuit 47. The delay control circuit 47 controls the delay amount of the dummy delay circuit 45 in such a direction that the phase difference disappears based on the phase difference signal. As a result, as shown in FIGS. 4A and 4B, the rise of the delayed dummy clock dZ coincides with the rise of the reference clock X, that is, the delayed dummy clock dZ is compared with the reference clock X. Thus, the delay amount of the dummy delay circuit 45 is variably controlled so as to be delayed by k periods (here, k = 2) of the external clock signal.
[0023]
By the way, the delay circuit 41 supplied with the inverted frequency-divided clock from the 1/2 frequency divider 30 and the delay circuit 42 supplied with the frequency-divided clock from the 1/2 frequency divider 30 are the same as the dummy delay circuit 45. The delay control circuit 47 is controlled to have the same delay amount as that of the dummy delay circuit 45, and is divided by a divided clock (0 degree clock) as shown in FIG. ) Is supplied to the output circuit 50 as a real clock, and a divided clock (180-degree clock) as shown in FIG. 4E delayed by 180 degrees from the delay circuit 41 is supplied to the output circuit 50 as an inverted real clock. The output circuit 50 buffers the data on the data bus in synchronization with the real clock and the inverted real clock and outputs the data from the data output pad 52. That is, data output from the output circuit 50 is synchronized with an external input clock signal applied to the clock input pad 10.
[0024]
In this way, the input clock signal is divided by 1/2 to generate the first and second divided clock signals whose rising phases are shifted from each other by 180 degrees, and each of the input clock signals is predetermined with respect to the input clock signal by the DLL circuit. Since the output is delayed by the phase, only one DLL circuit is required, the increase in chip area can be prevented, and the number of delay circuits through which the first and second frequency-divided clock signals pass is small. It becomes difficult to receive.
[0025]
FIG. 5 is a circuit diagram showing a configuration example of the 1/2 frequency divider 30 shown in FIG. 3, and FIG. 6 is a diagram showing signal waveforms at each node of the frequency divider 30. As shown in FIG. 9, the ½ frequency divider 30 includes NAND gates 61 to 68 and an inverter 69. The signal IN (external clock signal from the input circuit 10) is supplied to the NAND gates 61 and 62 of the first gate unit and is inverted by the inverter 69 to the NAND gates 65 and 66 of the second gate unit. Supplied.
[0026]
The NAND gates 61 and 62 are respectively supplied with the outputs of the NAND gates 68 and 67 of the slave latch unit, and the outputs of the NAND gates 61 and 62 are supplied to the NAND gates 63 and 64 of the master latch unit. Outputs of the NAND gates 64 and 63 are supplied to the NAND gates 63 and 64, respectively. Output complementary signals of the NAND gates 63 and 64 are supplied to the NAND gates 65 and 66, respectively. The NAND gates 67 and 68 are supplied with outputs of the NAND gates 65 and 66, respectively, and output complementary signals of the NAND gates 67 and 68 are supplied to the NAND gates 68 and 67, respectively.
[0027]
The output terminals of the NAND gates 61 to 68 correspond to the nodes no2 to no9. When the node no5 is extracted as a frequency-divided clock, the node no4 extracts an inverted frequency-divided clock whose phase is shifted by 180 degrees with respect to the frequency-divided clock. This frequency-divided clock is supplied to the delay circuit 42 and the frequency divider 43 shown in FIG. 3, and the inverted frequency-divided clock is supplied to the delay circuit 41.
[0028]
In this way, the output complementary signal of the slave latch unit is gated by the input clock signal and latched by the master latch unit, and the output complementary signal of the master latch unit is gated by the inverted signal of the input clock signal and latched by the slave latch unit. Since the output complementary signal of the master latch unit is output, the rising phases of the first and second divided clock signals can be accurately shifted by 180 degrees.
[0029]
FIG. 7 is a circuit diagram showing a configuration example of the frequency divider 43 shown in FIG. 3, and FIG. 8 is a diagram showing signal waveforms at each node of the frequency divider 43 in FIG. As shown in FIG. 7, the frequency divider 43 includes three-stage counters 301 to 303 including a plurality of NAND gates and inverters, and divides the signal S1 (frequency-divided clock from the 1/2 frequency divider 30). Thus, signals S2 and S3 are generated. In FIG. 8, reference numeral A is an output signal of the first counter 301, B is an output signal of the second counter 302, and each signal waveform is as shown in FIG. The frequency divider 43 is not limited to a three-stage counter composed of a plurality of NAND gates and inverters, and can be configured as a combination of various logic gates.
[0030]
As shown in FIG. 8, the frequency divider 43 divides the input clock signal S1 by 8, and the signal for which the period of one clock cycle of the external clock signal is at the high level H and the clock level of the seven clock cycles is at the low level L. S2 is generated. Further, the frequency divider 43 generates a signal S3 that is complementary to the signal S2.
FIG. 9 is a diagram illustrating the phase relationship between the signals S0 to S3. As shown in the figure, the phase comparison circuit 31 performs phase comparison once every eight periods. The signal S0 is synchronized with the signal S1 with a delay of one cycle. Thereby, the output clock signal in the output circuit 50 is phase-synchronized with the external clock signal one clock cycle before.
[0031]
Note that by changing the period a of the signal S2 of the frequency divider 43, it is possible to adjust how many clocks before the output clock signal is generated from the external clock signal. For example, by setting the period a of the signal S2 to a length corresponding to 3 clocks, an output clock signal synchronized with the external clock signal 3 clocks before can be generated. In addition, by changing the period a + b of the signal S2, it is possible to adjust how many periods the phase comparison is performed.
[0032]
When the sum of the minimum delay time of the input circuit 20, the delay circuit 41, the delay time of the clock wiring and the delay time of the output circuit 50 is shorter than the time of two cycles of the external clock signal (2 clock cycles), 2 An internal clock signal in phase synchronization can be generated from an external clock before the clock cycle.
FIG. 10 is a diagram for explaining a configuration example of the delay circuits 41 and 42 and the dummy delay circuit 45 having the same configuration. 1A shows the configuration of a delay circuit (unit delay circuit) for one bit, FIG. 1B is a timing diagram showing the operation of this unit delay circuit, and FIG. 1C shows the unit delay circuit. The configuration and operation when multiple stages are connected are shown.
[0033]
As shown in FIG. 10A, the unit delay circuit includes two NAND gates 401 and 402 and an inverter 403. The operation of the unit delay circuit will be described with reference to FIG. 10B. The input φE is an activation signal (enable signal), and the unit delay circuit operates at the high level H. FIG. 10B shows a state in which the enable signal φE is at the high level H and the signal can be accessed. In FIG. 10B, IN represents an input signal to the unit delay circuit, φN represents a signal from an adjacent right unit delay circuit among the delay circuits connected in a plurality of stages, and OUT represents a unit delay. The output signals of the circuit are shown, and 4a-1 and 4a-2 show the waveforms of the corresponding nodes in FIG. Therefore, OUT corresponds to the signal φN of the unit delay circuit adjacent on the left side.
[0034]
When the signal φN is at the low level L, the output signal OUT is always at the low level L. When the signal φN is at the high level H and the signal φE is at the low level, the output signal OUT is at the high level. When the signal φN is at a high level and the signal φE is at a high level, the output signal OUT is at a high level H if the input signal IN is at a low level L, and is at a low level L if IN is at a high level.
[0035]
According to the circuit of FIG. 10A, when the input signal IN rises while the enable signal φE is at the high level H, the input signal propagates to the path indicated by the arrow, but when the enable signal φE is at the low level L, The input signal IN is prevented from propagating to the output OUT along the path indicated by the arrow.
FIG. 10C shows an example in which the unit delay circuits shown in FIG. 10A are cascaded in a plurality of stages, and corresponds to the actual delay circuit 33 and the dummy delay circuit 34. Although only three stages are shown in FIG. 10 (c), in reality, multiple stages are connected so as to obtain a desired delay amount. The enable signal φE has a plurality of signal lines such as φE-1, φE-2, and φE-3 for each circuit element, and these signals are controlled by the delay control circuit 32.
[0036]
In FIG. 10C, the central unit delay circuit is activated, and the enable signal φE-2 is at the high level H. In this case, when the input signal IN changes from the low level L to the high level H, the enable signals φE-1 and φE-3 of the left unit delay circuit and the right unit delay circuit are at the low level. The input signal IN is stopped by the NAND gates 401-1 and 401-3.
[0037]
On the other hand, since the enable signal φE-2 of the activated central unit delay circuit is at the high level H, the input signal IN passes through the NAND gate 401-2. Since the output signal OUT of the right unit delay circuit is at the high level H, the low level L signal is propagated through the NAND gate 402-2 that is the input signal IN as well. As described above, when the output signal OUT on the right side, that is, the enable signal φN is at the low level L, the output signal OUT is always at the low level L. Therefore, the low level L signal is output from the NAND gate and the unit delay circuit on the left side. The signals are sequentially transmitted to the inverter and taken out as a final output signal.
[0038]
In this way, the input signal IN is transmitted through the activated unit delay circuit so as to be turned back into a final output signal. That is, the amount of delay can be controlled by which part of the enable signal φE is set to the high level H. The delay amount (unit delay amount) for one bit is determined by the total signal propagation time of the NAND gate and the inverter, this time becomes the delay unit time of the DLL circuit, and the entire delay time passes through the unit delay amount. The amount multiplied by the number of steps to be performed.
[0039]
FIG. 11 is a circuit diagram showing one configuration of delay control circuit 47 shown in FIG. The delay control circuit 47 has a configuration in which unit delay control circuits 430-2 having the same unit delay circuit as described above are connected by the number of unit delay circuits of the delay circuits 41 and 42 and the dummy delay circuit 45. Becomes an enable signal .phi.E which is a remarkable delay circuit. The unit delay control circuit 430-2 includes transistors 435-2, 437-2, 438-2, 439-2 connected in series to both ends of a flip-flop composed of a NAND gate 432-2 and an inverter 433-2, and It has a NOR gate 431-2. The gate of the transistor 438-2 is connected to the node 5a-2 of the previous unit delay control circuit, and the gate of the transistor 439-2 is connected to the node 5a-5 of the subsequent unit delay control circuit to Have come to receive. On the other hand, set signals φSE and φSO when counting up and reset signals φRE and φRO when counting down are connected to the other transistor connected in series every other bit.
[0040]
As shown in FIG. 11, in the central unit delay control circuit 430-2, the set signal φSO is supplied to the gate of the transistor 435-2, the reset signal φRO is supplied to the transistor 437-2, and the transistor 437-2 is supplied. A reset signal φRO is supplied, and a set signal φSE and a reset signal φRE are supplied to the gates of the corresponding transistors in the circuits on both sides of the front stage and the rear stage of the unit delay control circuit 430-2, respectively. The NOR gate 431-2 is configured to receive the signals of the node 5 a-1 of the left (previous stage) circuit and the node 5 a-4 of the circuit 430-2. Note that φR is a signal for resetting the unit delay control circuit, and temporarily becomes a low level L after power-on, and thereafter is fixed at a high level H.
[0041]
FIG. 12 is a timing chart for explaining the operation of delay control circuit 47 shown in FIG.
As shown in FIG. 12, first, the reset signal φR temporarily becomes a low level L, the nodes 5a-1, 5a-3, 5a-5 are at the high level H, and 5a-2, 5a-4, 5a-6. Is set to low level L. When counting up, the count-up signals (set signals) φSE and φSO repeat high level H and low level L alternately.
[0042]
When the set signal φSE changes from the low level L to the high level H, the node 5a-1 is grounded to become the low level L, and the node 5a-2 changes to the high level H. In response to the change of the node 5a-2 to the high level H, the output signal (enable signal) φE-1 changes from the high level H to the low level L. Since this state is latched by the flip-flop, the enable signal φE-1 remains at the low level L even if the set signal φSE returns to the low level L. Then, in response to the change of the node 5a-1 to the low level L, the enable signal (output signal) φE-2 changes from the low level L to the high level H. Since the node 5a-2 is changed to the high level H, the transistor 438-2 is turned on, and when the set signal φSO is changed from the low level L to the high level H, the node 5a-3 is installed and becomes the low level L. The node 5a-4 changes to the high level H. Furthermore, in response to the change of the node 5a-4 to the high level H, the enable signal φE-2 changes from the high level H to the low level L. Since this state is latched by the flip-flop, the enable signal φE-2 remains at the low level L even when the set signal φSO returns to the low level L.
[0043]
Then, in response to the change of the node 5a-3 to the low level L, the enable signal φE-3 changes from the low level L to the high level H. In FIG. 8, the set signals φSE and φSO are only output one pulse at a time, but the unit delay control circuit is connected in multiple stages, and the set signals φSE and φSO are alternately switched between the high level H and the low level L. Is repeated, the position of the stage where the output signal (enable signal) φE becomes the high level H is sequentially shifted to the right. Therefore, when it is necessary to increase the delay amount based on the comparison result of the phase comparison circuit 31, the pulses of the set signals φSE and φSO may be alternately input.
[0044]
If the count-up signals (set signals) φSE and φSO and the count-down signals (reset signals) φRE and φRO are not output, that is, a low level L state is maintained, the enable signal φE becomes a high level H level. The position is fixed. Therefore, when the delay amount needs to be maintained based on the comparison result of the phase comparison circuit 31, the pulses of the signals φSE, φSO, φRE, and φRO are not input.
[0045]
When counting down, if the pulses of the reset signals φRE and φRO are alternately input, the position of the stage where the output φE becomes the high level H is sequentially shifted to the left, contrary to the count up.
As described above, in the delay control circuit 47 shown in FIG. 11, it is possible to move the position of the stage where the enable signal φE becomes the high level H one by one by inputting a pulse. If the delay circuit shown in FIG. 10C is controlled by the enable signal φE, the delay amount can be controlled by one unit (per unit delay time).
[0046]
Next, the configuration of the phase comparator 44 shown in FIG. 3 will be described. The phase comparator 44 includes a phase comparator shown in FIG. 13 and an amplifier circuit unit shown in FIG. First, the phase comparison unit shown in FIG. 13 will be described with reference to FIG.
In FIG. 14, reference signs φout and φext indicate an output signal (S0) and an external clock signal (S3) to be compared by the phase comparison circuit, and the phase of the signal φout is determined with reference to the signal φext. Further, φa to φe indicate output signals connected to the amplifier circuit section shown in FIG.
[0047]
As shown in FIG. 13, the phase comparator 44 of the phase comparator 44 includes flip-flop circuits 421 and 422 composed of two NAND gates, latch circuits 425 and 426 for latching the state, and an activation signal for the latch circuit. , A delay circuit 423 that delays the external clock signal φext by a unit delay amount, and a delay circuit 430 that delays the signal φout by a unit delay amount. The flip-flop circuit 421 performs phase comparison in the range of -td, and the flip-flop circuit 422 performs phase comparison in the range of + td.
[0048]
FIG. 14A shows a case where the phase of the comparison target signal φout advances beyond the comparison reference signal φext by more than td, that is, the signal φout changes from the low level L to the high level H before the signal φext. Yes. When both the signal φout and the signal φext are at the low level L, the nodes 6a-2, 6a-3, 6a-4, and 6a-5 of the flip-flop circuits 421 and 422 are all at the high level H.
[0049]
When the signal φout changes from the low level L to the high level H, the node 6a-4 changes from the high level H to the low level L, and the node 6a-0 is delayed by one delay (td) from the low level L to the high level H. As a result, the node 6a-2 changes from the high level H to the low level L. Thereafter, the signal φext changes from the low level L to the high level H, and the node 6a-1 changes from the low level L to the high level H with a delay of one delay, but the potentials at both ends of the flip-flop are already determined. No change will occur. As a result, the node 6a-2 maintains the low level L, the node 6a-3 maintains the high level H, the node 6a-4 maintains the low level, and the node 6a-5 maintains the high level.
[0050]
On the other hand, in response to the change of the signal φext from the low level to the high level H, the output signal φa of the circuit 424 changes from the low level L to the high level H, and temporarily goes to the high level H at the node 6a-6. A pulse is applied. Since the node 6a-6 serves as an input to the NAND gates of the latch circuits 425 and 426, the NAND gate is temporarily activated, and the potential states at both ends of the flip-flop circuits 421 and 422 are changed. 426. Eventually, the output signal φb becomes high level H, the output signal φc becomes low level L, the output signal φd becomes high level H, and the output signal φe becomes low level L.
[0051]
Next, FIG. 14B shows a case where the phase of the comparison target signal φout and the comparison reference signal φext are substantially the same (within ± td), and the signal φout changes from the low level L to the high level H almost simultaneously with the signal φext. ing. When the signal φout changes from the low level L to the high level H within the time difference between the rising time of the signal φout and the rising time of the node 6a-1, first, the signal φext changes from the low level L to the high level H. The node 6a-3 of 421 changes from the low level L to the high level H. In the flip-flop 422, since the node 6a-1 remains at the low level L, the node 6a-4 changes from the high level H to the low level L. Thereafter, the node 6a-1 changes from the high level H to the low level L, but since the state of the flip-flop 422 has already been determined, no change occurs. Thereafter, since the node 6a-6 temporarily becomes the high level H, this state is stored in the latch circuit. As a result, the output signal φb is the low level, the output signal φc is the high level H, and the output signal φd is the high level. H, and the output signal φe becomes low level.
[0052]
FIG. 14C shows a case where the phase of the comparison target signal φout is delayed by more than td from the comparison reference signal φext, and φout changes from the low level L to the high level H after φext. In this case, changes occur in the two flip-flop circuits 421 and 422 due to φext, and 6a-3 and 6a-5 change from the high level H to the low level L. Finally, φb becomes a low level, φc becomes a high level H, φd becomes a low level L, and φe becomes a high level H.
[0053]
In this way, with the rise time of the signal (comparison reference signal) φext as a reference, the rise time of the signal (comparison target signal) φout has become the high level H before that, has been almost at the same time, or delayed to the high level H It becomes possible to detect whether or not. These detection results are latched as the values of the output signals φb, φc, φd, and φe, and it is possible to decide whether to count up or count down the delay control circuit 47 based on the values.
[0054]
Next, a configuration example of the amplifier circuit unit of the phase comparator 44 will be described with reference to FIG. FIG. 16 is a timing chart for explaining the operation of the JK flip-flop shown in FIG.
As shown in FIG. 15, the amplification circuit unit of the phase standard circuit 31 includes two parts, a JK flip-flop 427 and an amplification unit 428 including a NAND gate and an inverter. The JK flip-flop 427 receives the output signal φa from the phase comparison unit of FIG. 13 and the potentials of the nodes 7a-9 and 7a-11 depending on whether the signal φa is low level L or high level H. Is configured to alternately repeat the low level L and the high level H. The amplifying unit 428 receives and amplifies the output signal of the JK flip-flop 427 and the signals φb and φd.
[0055]
First, the operation of the JK flip-flop 427 will be described with reference to the timing chart of FIG. When the signal φa changes from the high level H to the low level L at the time T1, the nodes 7a-1 and 7a-10 change from the low level L to the high level H. On the other hand, the nodes 7a-5, 7a-6, and 7a-7 change according to the change of the node 7a-1, but the signal 7a-8 is at the low level L, so the node 7a-8 does not change. Eventually, the output (node) 7a-9 does not change, and only the output 7a-11 changes from the low level L to the high level H. Next, when φa changes from the low level L to the high level H at time T2, the node 7a-8 changes from the high level H to the low level L and 7a-10 changes to 7a-, contrary to the movement at time T1. Since 7 does not change, the output 7a-9 changes from the low level L to the high level H, and the output 7a-11 does not change. As described above, the JK flip-flop circuit 427 causes the outputs 7a-9 and 7a-11 to alternately repeat the high level H and the low level L in accordance with the movement of the signal φa.
[0056]
FIG. 17 is a timing diagram (when counting up) showing the operation of the amplifier circuit section when counting up, FIG. 18 is a timing diagram showing the operation when maintaining the count of the amplifier circuit section, and FIG. 19 is an amplifier circuit. It is a timing diagram which shows the operation | movement at the time of countdown of a part. With reference to these drawings, the operation of the amplifying unit 428 shown in FIG. 15 will be described.
[0057]
FIG. 17 shows a case where the comparison target signal φout first changes from the low level L to the high level H with respect to the rising edge of the comparison reference signal φext. In this case, the input signal from the phase comparator has a signal φb at a high level H, a signal φc at a low level L, a signal φd at a high level H, and a signal φe at a low level L. Eventually, the node 7a-12 becomes high level H, the node 7a-13 is fixed at low level L, and the set signals φSO and φSE change according to the state of the JK flip-flop, but the reset signals φRO and φRE are 7a. Since -13 is low level L, it does not change.
[0058]
FIG. 18 shows a case where the comparison target signal φout changes from the low level L to the high level H almost simultaneously with the comparison reference signal φext. In this case, the input signal from the phase comparison unit is such that the signal φb is low level L, the signal φc is high level, the signal φd is high level, and the signal φe is low level. Eventually, the nodes 7a-12 and 7a-13 are fixed at the low level L, the reset signals φSE and φSO are not affected by the output of the JK flip-flop, and the signals φSO, φSE, φRO and φRE are at the low level L. Will remain fixed.
[0059]
FIG. 19 shows a case where the comparison target signal φout changes from the low level L to the high level H with a delay from the rising of the comparison reference signal φext. In this case, the input signal from the phase comparison unit has a signal φb at a low level L, a signal φc at a high level H, a signal φd at a low level L, and a signal φe at a high level H. Eventually, the node 7a-12 is fixed to the low level L, the node 7a-13 is fixed to the high level H, and the reset signals φRO and φRE change according to the state of the JK flip-flop 427, but the set signals φSO and φSE Does not change because the node 7a-13 is at the low level L.
[0060]
FIG. 15 also shows a logic circuit 431 that generates a reset signal from the signals φb and φe. If φout exceeds the range of ± td with respect to φext, the reset signal is at H, and if within the range, the reset signal is L.
20 is a diagram showing a configuration of a synchronous DRAM (SDRAM) as an example to which a semiconductor integrated circuit device (DLL) according to the present invention is applied. FIG. 21 is a diagram for explaining the operation of the SDRAM of FIG. It is a timing chart.
[0061]
An SDRAM as an example of a semiconductor integrated circuit device to which the present invention is applied adopts, for example, a pipeline system, and is configured to have a 16M.2 bank.8 bit width.
As shown in FIG. 20, in addition to the DRAM cores 108a and 108b of general-purpose DRAM, the SDRAM includes a clock buffer 101, a command decoder 102, an address buffer / register & bank address select (address buffer) 103, an I / O data buffer / A register 104, control signal latches 105a and 105b, a mode register 106, and column address counters 107a and 107b are provided. Here, the / CS, / RAS, / CAS, and / WE terminals are different from the conventional operation, and the operation mode is determined by inputting various commands in combination. Various commands are decoded by the command decoder, and each circuit is controlled according to the operation mode. The / CS, / RAS, / CAS, and / WE signals are also input to the control signal latches 105a and 105b, and their states are latched until the next command is input.
[0062]
The address signal is amplified by the address buffer 103 and used as a load address for each bank, and is also used as an initial value for the column address counters 107a and 107b.
The clock buffer 101 includes an internal clock generation circuit 121 and an output timing control circuit 122. The internal clock generation circuit 121 generates a normal internal clock signal from the external clock signal CLK, and the output timing control circuit 122 applies accurate delay control (phase control) by applying the DLL circuit as described above. For generating the clock signal.
[0063]
The I / O data buffer / register 104 includes a data input buffer 13 and a data output buffer (output circuit) 51, and signals read from the DRAM cores 108 a and 108 b are amplified to a predetermined level by the data output buffer 51. The data is output via the pads DQ0 to DQ7 at a timing according to the clock signal from the output timing control circuit 122. As for the input data, the data input from the pads DQ0 to DQ7 is taken in via the data input buffer 13. Here, the clock wiring 41 corresponds to the wiring from the output timing control circuit 122 to each data output buffer 51.
[0064]
The reading operation of the SDRAM will be described with reference to FIG.
First, the external clock signal CLK is a signal supplied from a system in which the SDRAM is used. In synchronization with the rising edge of the CLK, various commands, address signals, input data are fetched, or output data is output. To work.
[0065]
When reading data from the SRAM, an active (ACT) command is input to the command terminal from a combination of command signals (/ CS, / RAS, / CAS, / WE signal), and a row address signal is input to the address terminal. When this command and row address are input, the SDRAM is activated, selects a word line corresponding to the row address, outputs cell information on the word line to the bit line, and amplifies it by a sense amplifier.
[0066]
Further, a read command (Read) and a column address are input after the operation time (tRCD) of the portion related to the row address. According to the column address, the selected sense amplifier data is output to the data bus line, amplified by the data bus amplifier, further amplified by the output buffer, and output to the output terminal (DQ). These series of operations are exactly the same as those of a general-purpose DRAM. In the case of an SDRAM, a circuit related to a column address operates as a pipeline, and read data is output exclusively for each cycle. . As a result, the data transfer rate becomes the cycle of the external clock signal CLK.
[0067]
There are three types of access time in the SDRAM, all of which are defined with reference to the rising point of the external clock signal CLK. In FIG. 21, tRAC indicates a row address access time, tCAC indicates a column address access time, and tAC indicates a clock access time.
FIG. 22 is a block diagram schematically showing a main configuration of the SDRAM of FIG. 20, for explaining the pipeline operation in the SDRAM, and shows a case where three stages of pipes are provided as an example. .
[0068]
The processing circuit related to the column address in the SDRAM is divided into a plurality of stages along the flow of processing, and the divided circuit of each stage is called a pipe.
As described with reference to FIG. 20, the clock buffer 101 includes the internal clock generation circuit 121 and the output timing control circuit 122, and the output of the internal clock generation circuit 121 (ordinary internal clock Hisao Niio) is pipe-1 and pipe. -2 and the output of the output timing control circuit 122 (phase-controlled internal clock signal) is supplied to the output circuit 50 (data output buffer) of the pipe-3.
[0069]
Each pipe is controlled according to the supplied internal clock signal, and a switch for controlling the transmission timing of the signal between the pipes is provided between the pipes. These switches are also connected to the clock buffer 101 (internal clock generation circuit 121). ) Is controlled by the internal clock signal generated in (1).
In the example shown in FIG. 22, in the pipe-1, the address signal is amplified by the column address buffer 116 and sent to the column decoder 118, and the information of the sense amplifier circuit 117 corresponding to the address address selected by the column decoder 118 is shown. Until the data bus amplifier 119 amplifies the information on the data bus. In addition, only the data bus control circuit 120 is provided in the pipe-2, and the pipe-3 includes the I / O buffer 104 (the output circuit 50). The data input buffer 13 in the I / O buffer 104 is omitted in FIG.
[0070]
If the circuits in each pipe also complete the operation within the clock cycle time, data is relayed out by opening and closing a switch between the pipes in synchronization with the clock signal. As a result, processing in each pipe is performed in parallel, and data is continuously output to the output terminal in synchronization with the clock signal.
[0071]
FIG. 23 is a diagram for explaining a configuration example of the output circuit (data output buffer) 50 in the semiconductor integrated circuit device according to the present invention. As shown in FIGS. 22 and 23, Data1 and Data2 in FIG. 23 correspond to the storage data read from the cell array 115 and output through the sense amplifier 117, the data bus amplifier 119, and the data bus control circuit 120. Data1 and Data2 are both at the low level L when the output data is at the high level H, and are at the high level H when the output data is at the low level L. It is also possible to take a high impedance state (hijet state) in which the output data is neither high level H nor low level L. In this case, in the data bus control circuit 120, Data1 is high level H and Data2 is low. Converted to level. Similarly to Data 1 and Data 2, Data 3 and Data 4 are signals corresponding to storage data read from the cell array 115 and output via the sense amplifier 117, the data bus amplifier 119, and the data bus control circuit 120. Data2 is both at the low level L when the output data is at the high level H, and is at the high level H when the output data is at the low level L.
[0072]
The signal φ0 corresponds to the output signal (real clock) of the output timing control circuit 122 (delay circuit 42 in FIG. 3) and functions as an enable signal for the output circuit.
When the clock signal φ0 rises to the high level H, information on Data1 and Data2 appears on the data output pads 52 (DQ0 to DQ7). For example, assuming that the high level H is output to the data output pad 52, the clock signal φ0 changes from the low level L to the high level H, the node 8a-1A becomes the low level L, and the node 8a-2A becomes the high level. At H, the transfer gate is turned on, and Data1 and Data2 are transmitted to the nodes 8a-3 and 8a-6. As a result, when the node 8a-5 is at the low level L and the node 8a-8 is at the high level H, the output P-channel transistor 81 is turned on and the N-channel transistor 82 is turned off, so that the data output pad 52 An output of high level H appears in. When the clock signal φ0 becomes low level L, the transfer gate is turned off and the output state up to that time is maintained.
[0073]
The signal φ18 corresponds to the output signal (inverted real clock) of the output timing control circuit 122 (delay circuit 41 in FIG. 3), and functions as an enable signal for the output circuit. The phase is 180 degrees different.
When the clock signal φ18 rises to the high level H, information on Data3 and Data4 appears on the data output pads 52 (DQ0 to DQ7). For example, assuming that the high level H is output to the data output pad 52, the clock signal φ18 changes from the low level L to the high level H, the node 8a-1B becomes the low level L, and the node 8a-2B becomes the high level. At H, the transfer gate is turned on, and Data3 and Data4 are transmitted to the nodes 8a-3 and 8a-6. As a result, when the node 8a-5 is at the low level L and the node 8a-8 is at the high level H, the output P-channel transistor 81 is turned on and the N-channel transistor 82 is turned off, so that the data output pad 52 An output of high level H appears in. When the clock signal φ18 becomes low level L, the transfer gate is turned off and the output state up to that time is maintained.
[0074]
That is, the information of Data1 and Data2 is latched and output from the data output pad 52 when the clock signal φ0 rises, and then the information of Data3 and Data4 is latched and output from the data output pad 52 when the clock signal φ18 rises. This is repeated alternately.
The present invention is not limited to the above embodiments, and various modifications are possible. For example, a logic element that functions as a delay element constituting a delay circuit is not limited to a NAND gate or an inverter, and can be configured using a logic element such as NOR or EOR.
[0075]
In the above description, the semiconductor integrated circuit device of the present invention has been described as an SDRAM. However, the present invention is not limited to an SDRAM, and any semiconductor integrated circuit device that outputs an output signal in synchronization with an externally input signal. It can be applied to anything.
[0076]
【The invention's effect】
  As mentioned above,According to the present invention, the input clock signal is divided by 1/2 to generate first and second divided clock signals whose rising phases are shifted from each other by 180 degrees, and each of them is generated by the DLL circuit with respect to the input clock signal. Since the output is delayed by a predetermined phase, only one DLL circuit is required, an increase in the chip area can be prevented, and the number of delay circuits through which the first and second divided clock signals pass is small. It becomes difficult to be affected.
In addition, the dummy clock obtained by dividing the second frequency-divided clock signal is delayed by the dummy delay circuit and the dummy circuit, and the phase comparison between the dummy clock and the reference clock is performed. In order to control the delay amount of the second delay circuit, the first and second divided clock signals whose rising phases are shifted by 180 degrees can be delayed by a predetermined phase with respect to the input clock signal.
[0079]
  Also,The output complementary signal of the slave latch unit is gated by the input clock signal and latched by the master latch unit, and the output complementary signal of the master latch unit is gated by the inverted signal of the input clock signal and latched by the slave latch unit. Since the output complementary signal is output, the rising phase of the first and second divided clock signals can be accurately shifted by 180 degrees.
[Brief description of the drawings]
FIG. 1 is a block diagram of an example of a conventional DLL circuit.
FIG. 2 is a block diagram of another example of a conventional DLL circuit.
FIG. 3 is a block diagram of one embodiment of a semiconductor integrated circuit device of the present invention.
4 is a diagram showing signal waveforms at various parts of the semiconductor integrated circuit device of FIG. 3;
5 is a circuit diagram showing an example of a 1/2 frequency divider in the semiconductor integrated circuit device of FIG. 3;
6 is a diagram illustrating a signal waveform of each node of the 1/2 frequency divider in FIG. 5. FIG.
7 is a circuit diagram showing an example of a frequency divider in the semiconductor integrated circuit device of FIG. 3;
8 is a diagram showing signal waveforms at each node of the frequency divider shown in FIG. 7;
9 is a timing chart for explaining the operation of the semiconductor integrated circuit device using the frequency divider of FIG.
FIG. 10 is a diagram for explaining a configuration example of a delay circuit in the semiconductor integrated circuit device of the present invention.
FIG. 11 is a diagram for explaining a configuration example of a delay control circuit 47 in the semiconductor integrated circuit device of the present invention.
12 is a timing chart for explaining the operation of the delay control circuit of FIG. 11; FIG.
FIG. 13 is a diagram for explaining a configuration example of a phase comparison unit of a phase comparator 44 in the semiconductor integrated circuit device of the present invention.
FIG. 14 is a timing diagram for explaining the operation of the phase comparison unit of FIG. 13;
FIG. 15 is a diagram for explaining a configuration example of an amplifier circuit section of a phase comparator 44 in the semiconductor integrated circuit device of the present invention.
16 is a timing chart for explaining the operation of the JK flip-flop in the amplifier circuit section of FIG.
FIG. 17 is a timing diagram (during count-up) for explaining the operation of the amplifier circuit unit of FIG. 15;
18 is a timing chart (during count maintenance) for explaining the operation of the amplifier circuit section of FIG. 15;
FIG. 19 is a timing chart (during countdown) for explaining the operation of the amplifier circuit section of FIG. 15;
FIG. 20 is a diagram showing a configuration of a synchronous DRAM as an example to which a semiconductor integrated circuit device according to the present invention is applied;
FIG. 21 is a timing diagram for explaining the operation of the synchronous DRAM of FIG. 20;
22 is a block diagram schematically showing a main configuration of the synchronous DRAM of FIG. 20;
FIG. 23 is a diagram for explaining a configuration example of an output circuit (data output buffer) in the semiconductor integrated circuit device according to the present invention;
[Explanation of symbols]
10 Clock input pad
20 Input circuit
30 1/2 divider
400 degree DLL block
41, 42 delay circuit
43 divider
44 Phase comparator
45 Dummy delay circuit
46 Dummy circuit
47 Delay control circuit
50 output circuit
52 Data output pad
61-68 NAND gate
69 Inverter

Claims (5)

A 1/2 divider that divides the input clock signal by 1/2 to generate first and second divided clock signals that are 180 degrees out of phase with each other;
A frequency divider that divides the first frequency-divided clock signal by a predetermined frequency division ratio and outputs a dummy clock and a reference clock that is an inverted signal thereof; a dummy delay circuit that delays the dummy clock; and a predetermined frequency A dummy circuit that delays the dummy clock output from the dummy delay circuit, a phase comparator that performs phase comparison between the dummy clock output from the dummy circuit and the reference clock, and A delay control circuit which is supplied with a phase difference to be output and controls a delay amount of the dummy delay circuit so as to eliminate the phase difference, and is controlled to be the same delay amount as the dummy delay circuit by the control of the delay control circuit; A first delay circuit that delays and outputs a divided clock signal; and the second delay clock is controlled by the delay control circuit to have the same delay amount as the dummy delay circuit. More becomes second delay circuit and outputting the delayed items, the first, and a DLL circuit that outputs delayed by a predetermined phase each second divided clock signal to the input clock signal
A semiconductor integrated circuit device comprising: The semiconductor integrated circuit device according to claim 1.
The 1/2 divider includes a first gate unit that gates an output complementary signal of a slave latch unit using the input clock signal;
A master latch unit that receives and latches the output signal of the first gate unit;
A second gate unit for gating the output complementary signal of the master latch unit with an inverted signal of the input clock signal;
A slave latch unit that receives and latches the output signal of the second gate unit;
A semiconductor integrated circuit device, wherein the output complementary signal of the master latch unit is output as the first and second divided clock signals. The semiconductor integrated circuit device according to claim 1.
The 1/2 divider is
Having a master latch part and a slave latch part,
The master latch unit latches the output of the slave latch unit in synchronization with an input clock signal and outputs the first and second divided clock signals,
The slave latch unit latches the output of the master latch unit in synchronization with an inverted signal of the input clock signal.
The semiconductor integrated circuit device, characterized in that. The semiconductor integrated circuit device according to any one of claims 1 to 3,
A semiconductor integrated circuit device comprising: an output circuit that outputs data on a data bus in synchronization with the first divided clock signal or the second divided clock signal . The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device, wherein the first delay circuit and the second delay circuit have the same configuration as the dummy delay circuit .

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