JP2007243141A - Built-in capacitor for multilayer wiring board and multilayer wiring board fabricated therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a built-in capacitor designed for multilayer wiring board wiring boards which ensure flexibility in capacitors, particularly in thin capacitors which are to be incorporated into the insulating resin layer of the build-up layers, provides protection against damage due to a certain degree of stress and simplifies a process for incorporating the capacitor in the insulating resin layer of the build-up layers and a multilayer wiring board fabricated therewith. <P>SOLUTION: This capacitor is a built-in capacitor 1 intended for use by a multilayer wiring board and its metal-contained volume to the total volume of the capacitor 1 is 45 vol% or more but 95 vol% or less. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a capacitor built in a multilayer wiring board and a multilayer wiring board incorporating the capacitor.

  In recent years, due to the demand for higher functionality and lighter, thinner and smaller electronic devices, electronic components such as ICs (Integrated Circuits) and LSIs (Large Scale Integrations) are rapidly becoming densely integrated. Increasingly faster. Along with this, wiring boards for mounting electronic components are required to have higher density wiring and multi-terminals than ever before, and as a wiring board, insulating resin layers and conductor layers are alternately placed on the board core. A multilayer wiring board laminated on is often used.

  By the way, in an IC that operates at a high speed, if a large number of elements are simultaneously switched at a high speed, all the necessary high-frequency current is supplied from the power supply. Will hinder high-speed operation. Therefore, in order to stably supply the electric charge necessary for the operation to the IC, a capacitor is provided on the multilayer wiring board, and a local power supply is provided in the vicinity of the IC to temporarily supply the capacitor to the capacitor. Charges are accumulated in a DC manner, and the IC stably supplies charges necessary for operation from this capacitor.

Therefore, a technique for incorporating a capacitor in a multilayer wiring board near the IC has been proposed. Here, as a location of the capacitor in this technique, the capacitor can be built in the substrate core that forms the core of the multilayer wiring board as in the technique described in Patent Document 1 by the present applicant. Further, since the wiring resistance and inductance can be further reduced when the capacitor is as close as possible to the IC, a capacitor disposed inside the insulating resin layer of the build-up layer formed on the substrate core is also disclosed. . For example, the technique described in Patent Document 2 discloses a technique in which a laminate in which dielectric layers and inner layer electrodes (inner electrode layers) are alternately stacked on a metal foil is formed. According to this, it becomes a thin capacitor and has a shape suitable for being incorporated in the insulating resin layer of the buildup layer.
JP-A-2005-39243 JP 2004-228190 A

  However, recently, there have been cases where cracks and the like occur in thin capacitors built in the insulating resin layer of the buildup layer. Such thin capacitors are generally manufactured using a powder process (sheet lamination process), etc., so the capacitor itself is very fragile, and the built-in package is reliable for thermal cycle tests and thermal shock tests. There is a problem of lacking. Further, since the capacitor itself is fragile, it is difficult to handle, and there is a risk that the capacitor may be broken when performing a process of incorporating the build-up layer into the insulating resin layer (such as a mounting process on a substrate or an insulating resin layer laminating process). Therefore, the capacitor built in the insulating resin layer of the build-up layer needs to have flexibility that does not break even when a certain amount of stress is applied.

  The present invention has been made in view of the above circumstances, and ensures flexibility of the capacitor itself, particularly in a thin capacitor built in an insulating resin layer of a build-up layer, and does not break even when a certain amount of stress is applied. It is an object of the present invention to provide a multilayer wiring board built-in capacitor that can easily incorporate the up layer into the insulating resin layer and a multilayer wiring board in which the capacitor is built.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, the multilayer wiring board built-in capacitor of the present invention is:
A capacitor for built-in multilayer wiring board,
The volume of the metal-containing layer contained in the capacitor is in the range of 45 vol% or more and 95 vol% or less with respect to the total volume of the capacitor itself.

  Usually, a capacitor built in an insulating resin layer of a build-up layer of a multilayer wiring board is formed by laminating a plurality of dielectric layers and internal electrode layers in order to increase the capacitance. It was brittle. For this reason, when it is incorporated in the insulating resin layer of the build-up layer of the multilayer wiring board, there have been cases in which cracking or the like occurs when mechanical or thermal stress caused by warping or deformation of the multilayer wiring board is applied. Therefore, like the present invention, by increasing the volume ratio of the metal-containing layer with respect to the total volume of the capacitor itself (in other words, by decreasing the volume ratio of the dielectric layer), specifically, the metal-containing layer By setting the volume of the layer in the range of 45 vol% or more and 95 vol% or less, flexibility can be imparted to the capacitor. As a result, when it is built in the insulating resin layer of the build-up layer of a multilayer wiring board, it can withstand mechanical and thermal stresses caused by warping or deformation of the multilayer wiring board and prevent the occurrence of cracks, etc. Sex can be secured. When the volume of the metal-containing layer is lower than 45 vol%, the dielectric layer becomes more brittle and the effect of improving flexibility is reduced. On the other hand, if it is higher than 95 vol%, it is difficult to laminate the dielectric layer, and sufficient electrostatic capacity cannot be secured.

  In the capacitor for built-in multilayer wiring board according to the present invention, the ratio of the metal component in the metal-containing layer can be 50 vol% or more. For example, a capacitor is provided with a dielectric layer made of a high dielectric constant ceramic or the like in order to electrically insulate each internal electrode layer, and adhesion between the dielectric layer and a metal-containing layer such as an internal electrode layer In order to improve the above, a ceramic material (co-material) having the same composition used for the dielectric layer can be contained in the metal-containing layer such as the internal electrode layer. As in the present invention, by setting the ratio of the metal component in the metal-containing layer to 50 vol% or more, as the metal content in the metal-containing layer increases, the elastic behavior increases and the flexibility of the capacitor is improved. Can do. On the other hand, if the metal content is lower than 50 vol%, the brittleness of the metal-containing layer by the ceramic material increases, and also the conductivity decreases such as an increase in resistance after firing and the flexibility of the capacitor itself decreases, thereby ensuring reliability. Can not.

  The multilayer wiring board built-in capacitor of the present invention can be formed with a thickness of 200 μm or less. By setting the thickness of the capacitor to 200 μm or less as in the present invention, it can be satisfactorily incorporated in the insulating resin layer of the build-up layer of the multilayer wiring board. When it becomes thicker than 200 μm, it becomes difficult to form the insulating resin layer of the build-up layer of a multilayer wiring board containing a capacitor flat, for example. In addition, in order to form it flat, it is necessary to form a thick insulating resin layer, and the multilayer wiring board itself is also formed to be thick, which goes against the demand for lightness, thinness, and miniaturization.

  In the multilayer wiring board built-in capacitor of the present invention, when a predetermined jig is pressed from the thickness direction, the straight line length in the surface direction is W, and the bending distance in the thickness direction is d. It is possible to bend in the thickness direction when / W is 0.01 or more. Further, the deformation is possible within a curvature range in which the curvature radius is 700 mm or less. If the capacitor for built-in multilayer wiring board outside the scope of the present invention is bent with a jig having a curvature radius of 700 mm or more, the capacitor for built-in multilayer wiring board will be cracked. Since the capacitor itself has such flexibility as in the present invention, mechanical stress and thermal history due to the process of incorporating the build-up layer of the multilayer wiring board into the insulating resin layer, deformation of the multilayer wiring board, etc. Even if added, a reliable capacitor that can withstand the stress can be obtained. As a result, a reliable multilayer wiring board can be obtained.

  The multilayer wiring board of the present invention can incorporate a capacitor for incorporating a multilayer wiring board having the above-described effects. As in the present invention, since the flexible and sufficient secured capacitor is built in the multilayer wiring board, sufficient reliability can be secured also in the multilayer wiring board.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a longitudinal sectional view of a multilayer wiring board built-in capacitor 1 according to the present invention, FIG. 2 is a plan view (bottom view) of the multilayer wiring board built-in capacitor 1 according to the present invention, and FIG. The cross-sectional view of the capacitor | condenser 1 for a multilayer wiring board which concerns is typically shown. In the present embodiment, the first main surface of the plate-like member is a surface appearing on the upper side in the drawing, and the second main surface is a surface appearing on the lower side in the drawing.

  As shown in FIGS. 1 and 2, a capacitor 1 with a built-in multilayer wiring board (hereinafter also simply referred to as a capacitor) is formed in a plate shape having a square shape or a rectangular shape in plan view, and has chamfered portions at four corners. 1a is formed. By forming the chamfered portion 1a, the capacitor 1 can alleviate the impact during handling, and when the capacitor 1 is built in a multilayer wiring board 100 (see FIG. 4) described later, a gap with the insulating resin layer is generated. Can be prevented. As a result, the gap is eliminated and the adhesion is improved.

  The capacitor 1 includes a dielectric layer 3 made of a high dielectric constant ceramic or the like such as barium titanate (BaTiO3: hereinafter abbreviated as BT), and first and second internal electrode layers made of a conductive material such as nickel. The capacitor body 2 formed by stacking 4 and 5 is provided at the core. Further, the first and second via conductors 6, 7 formed so as to penetrate in the thickness direction from the first main surface 2 a to the second main surface 2 b of the capacitor body 2, and the first and second via conductors 6, 7. And the first and second external electrode layers 8 and 9 formed on the first main surface 2a and the second main surface 2b and electrically insulated from the first and second external electrode layers 8 and 9, respectively. And first and second dummy electrode layers 10 and 11 formed in a predetermined pattern on the first main surface 2a and the second main surface 2b. These metal-containing layers can be formed of a conductive material such as nickel, and can contain a ceramic material (co-material) having the same composition as the ceramic material forming the dielectric layer 3. By including such a ceramic material in the metal-containing layer (conductive material), the adhesion with the dielectric layer 3 can be improved. In the present invention, the metal-containing layer refers to the first and second internal electrode layers 4 and 5, the first and second via conductors 6 and 7, the first and second external electrode layers 8 and 9, and the first and second 2 corresponds to the dummy electrode layers 10 and 11, respectively, and the volume of the metal-containing layer corresponds to the sum of all these volumes.

  The capacitor body 2 is formed such that a dielectric layer 3 is formed on the outermost surface of both the front and back surfaces, and the first internal electrode layer 4 and the second internal electrode layer 5 are opposed to each other with the dielectric layer 3 interposed therebetween. .

  The first internal electrode layer 4 and the second internal electrode layer 5 are electrically insulated by the dielectric layer 3, and each first internal electrode layer 4 is electrically connected by the first via conductor 6. Similarly, the second internal electrode layers 5 are electrically connected by the second via conductors 7 respectively. Further, the first and second via conductors 6 and 7 are alternately arranged in a lattice point shape (array shape) along the planar direction of the capacitor body 2.

  The first and second external electrode layers 8 and 9 are used, for example, as power supply electrodes, ground connection electrodes, or signal transmission electrodes, and are connected to each other via the first and second via conductors 6 and 7. As shown in FIG. 2, they are electrically connected, and are arranged in a grid (array) pattern. In the present embodiment, the first and second external electrode layers 8 and 9 have a circular shape. However, the first and second external electrode layers 8 and 9 may have an elliptical shape, a polygonal shape, or the like.

  The first and second dummy electrode layers 10 and 11 are formed in a planar shape on the first main surface 2 a and the second main surface 2 b of the capacitor body 2, and from the first and second external electrode layers 8 and 9. It is formed so as to surround the first and second external electrode layers 8 and 9 in a separated state. The first external electrode layer 8 and the first dummy electrode layer 10 formed on the first main surface 2a and the second external electrode layer 9 and the second dummy electrode layer 11 formed on the second main surface 2b are capacitors. The main body 2 is symmetrically formed. Thereby, the curvature etc. which are easy to occur by the difference of the thermal expansion coefficient with the dielectric material layer 3 and each electrode layer at the time of simultaneous baking can be prevented and suppressed, for example.

  A Cu plating layer may be formed with a predetermined thickness on the surfaces of the first and second external electrode layers 8 and 9 and the first and second dummy electrode layers 10 and 11 by electrolytic Cu plating or electroless Cu plating. . In that case, the surface of the Cu plating layer is roughened using a known method such as microetching or blackening to form a roughened surface, whereby a multilayer wiring substrate 100 (see FIG. 4) described later is used. ), The adhesion to the insulating resin layer is improved by the anchor effect.

  Next, the relationship between the first and second internal electrode layers 4 and 5 and the first and second via conductors 6 and 7 will be described in detail. As shown in FIG. 3A, the first internal electrode layer 4 has a first via conductor 6 that is electrically connected and a second via conductor 7 that is electrically insulated penetrate in the thickness direction. A clearance hole 4a is formed in a region through which the second via conductor 7 passes. Thereby, electrical insulation between the first internal electrode layer 4 and the second via conductor 7 is achieved. Similarly, as shown in FIG. 3B, the second internal electrode layer 5 has a thickness of a first via conductor 6 electrically insulated and a second via conductor 7 electrically connected. A clearance hole 5a is formed in a region penetrating in the direction and penetrating the first via conductor 6. Thereby, electrical insulation between the second internal electrode layer 5 and the first via conductor 6 is achieved. The first and second internal electrode layers 4 and 5 are alternately stacked with the dielectric layer 3 interposed therebetween to constitute the capacitor 1.

  The capacitor 1 having the above structure is formed so that the total volume of the metal-containing layer satisfies the range of 45 vol% or more and 95 vol% or less with respect to the total volume of the capacitor 1 by appropriately adjusting the conditions of each element. Yes. Each element includes the volume (size, thickness) of the capacitor 1 itself, the thickness of the dielectric layer 3 and the first and second internal electrode layers 4 and 5, the diameter and the number of the first and second via conductors 6 and 7. , The area and thickness of the first and second external electrode layers 8 and 9 and the area and thickness of the first and second dummy electrode layers 10 and 11. The volume of the metal-containing layer is the volume of the inner electrode layer + the volume of the surface electrode layer + the volume of the via conductor + the volume of the dummy electrode layer. In addition, when the Cu plating layer is formed on the surface of the surface electrode layer and the dummy electrode layer, the volume of the Cu plating layer is also included in the metal-containing layer. Furthermore, the metal-containing layer is formed so that the ratio of the metal component is 50 vol% or more. As a result, the capacitor 1 has a large elastic behavior and has sufficient flexibility.

Here, as a calculation method of the total volume occupied by the metal-containing layer with respect to the total volume of the capacitor, it can be calculated by converting from the density (volume and mass) of the capacitor. That is, since each density is specified by the material used, the volume ratio of the dielectric layer and the metal-containing layer can be calculated. The density range of the capacitor in which the total volume of the metal-containing layer is in the range of 45 vol% or more and 95 vol% or less varies depending on the material used. For example, barium titanate is used as the dielectric layer, and nickel is used as the metal-containing layer. When used, the appropriate density range is 6.6 to 8.8 g / cm ³ . A method for calculating the volume of the metal-containing layer by observing the cross section of the capacitor may be employed as a method for calculating the volume of the metal-containing layer.

  In this embodiment, a ceramic dielectric such as barium titanate is described as the dielectric layer, but in addition to this, dielectric ceramics such as strontium titanate and lead titanate can be preferably used. it can. Further examples include a resin dielectric layer and a dielectric layer made of a ceramic-resin composite material.

  Examples of the metal material used for the metal-containing layer include molybdenum, tungsten, titanium, copper, and silver in addition to nickel.

  Next, the multilayer wiring board 100 incorporating the capacitor 1 having the above structure will be described. FIG. 4 schematically shows a cross-sectional structure of the multilayer wiring board 100. The multilayer wiring board 100 includes first and second main surfaces MP1 of a substrate core 12 made of a heat resistant resin plate (for example, bismaleimide-triazine resin plate), a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin), or the like. , MP2 are formed with first and second core conductor layers M1, M11 that form wiring metal layers in a predetermined pattern, respectively. These first and second core conductor layers M1 and M11 are formed as surface conductor patterns covering the first and second main surfaces MP1 and MP2 of the substrate core 12, and are used as power supply layers or ground layers. On the other hand, a through-hole is drilled in the substrate core 12 by a drill or the like, and a through-hole conductor 30 that connects the first and second core conductor layers M1 and M11 to each other is formed in the through-hole.

  Further, on the surface layers of the first and second core conductor layers M1 and M11, a plurality of insulating resin layers 16 (V1 to V4) and 26 (V11 to V13) made of a thermosetting resin composition or the like are respectively provided. Is formed. Furthermore, between the insulating resin layers 16 (V1 to V4) and 26 (V11 to V13), conductor layers M2 to M5 and M12 to M14 having metal wirings are formed by Cu plating or the like. The first and second core conductor layers M1 and M11 and the conductor layers M2 and M12 are connected to each other by via conductors 34 and 35, respectively. Similarly, the conductor layers M2 to M5 and the conductor layers M12 to M14 are connected to each other by via conductors 34 and 35, respectively. The conductor layers M4 and M14 formed on the surfaces of the insulating resin layers 16 (V4) and 26 (V13) located on the outermost layer have metal terminal pads 25 and 27, respectively. The via conductors 34 and 35 are so-called filled vias formed by filling a via hole drilled in the insulating resin layers 16 (V4) and 26 (V13) with Cu plating or the like. The via conductors 34 and 35 have via pads provided on the bottom side so as to be electrically connected to the via conductors 34 and 35, and via lands projecting outward from the peripheral edges of the via conductors 34 and 35 on the side opposite to the via pads. So-called conformal vias may be used.

  The multilayer wiring substrate 100 has the capacitor 1 built in the central portion of the insulating resin layer 16 (V2) formed on the substrate core 12. The capacitor 1 is disposed within the thickness of the insulating resin layer 16 (V2), and is in close contact with the insulating resin layer 16 where the first and second external electrode layers 8 and 9 and the first and second dummy electrode layers 10 and 11 overlap. Is formed. Since the dummy electrode layers 10 and 11 are formed on the first and second main surfaces 2a and 2b of the capacitor body 2, both the front and back surfaces of the capacitor 1 are flat, and as a result, the insulating resin layer 16 (V2) is formed. It can be made flat and a stable build-up layer can be formed.

  On the first main surface MP1 of the substrate core 12, the core conductor layer M1, the conductor layers M2 to M5, and the insulating resin layer 16 (V1 to V4) form the first wiring laminated portion L1. Further, on the second main surface MP2 of the substrate core 12, the core conductor layer M11, the conductor layers M12 to M14, and the insulating resin layer 26 (V11 to V13) form the second wiring laminated portion L2. In either case, the insulating resin layers and the conductor layers are alternately laminated so that the first and second main surfaces CP1 and CP2 are formed of the insulating resin layer 16, and the first and second main surfaces CP1 and CP2 are formed. A plurality of metal terminal pads 25 and 27 are formed on the surfaces CP1 and CP2, respectively. The metal terminal pad 25 on the first wiring laminated portion L1 side constitutes a solder land for flip-chip connection of an integrated circuit chip or the like. Further, the metal terminal pad 27 on the second wiring laminated portion L2 side is a back surface land (PGA pad, BGA) for connecting the multilayer wiring board 100 itself to a mother board or the like by a pin grid array (PGA) or a ball grid array (BGA). Pad).

  The metal terminal pads 25 constituting the solder lands are arranged in the form of lattice dots (array shape) at the central portion of the first main surface CP1 of the multilayer wiring board 100, and the chip mounting portion together with the solder bumps 21 formed thereon is provided. Forming. In addition, the metal terminal pads 27 constituting the back surface land are also arranged in a lattice point shape (array shape) on the second main surface CP2. Solder resist layers 18 and 28 (SR1, SR11) made of a photosensitive or thermosetting resin composition are formed on the outermost conductor layers M4 and M14, respectively. In either case, in order to expose the metal terminal pads 25 constituting the solder lands or the metal terminal pads 27 constituting the back surface lands, the exposed holes 18a and 28a are formed on the metal terminal pads 25 and 27 in a one-to-one correspondence. ing. The solder bump 21 of the solder resist layer 18 formed on the first wiring laminated portion L1 side is made of, for example, solder containing substantially no Pb such as Sn—Ag, Sn—Cu, Sn—Ag—Cu, Sn—Sb. Can be created. On the other hand, the metal terminal pad 27 on the second wiring laminated portion L2 side is formed so as to be exposed in the exposure hole 28a of the solder resist layer 28. In the multilayer wiring substrate 100, the signal transmission path is from the metal terminal pad 25 formed on the first main surface MP1 side (first wiring laminated portion L1 side) of the substrate core 12 to the second main surface MP2 side (second It is formed so as to reach the metal terminal pad 27 formed on the wiring laminated portion L2 side).

  In the multilayer wiring board 100 described above, the first and second wiring laminated portions L1 and L2 are respectively formed on the first and second main surfaces MP1 and MP2 of the substrate core 12 by a known buildup method or the like. Can be manufactured. Before performing the build-up process for forming the first and second wiring laminated portions L1 and L2, a through hole is provided in the substrate core 12 in advance, and the through hole conductor 30 is formed in the through hole by Cu plating or the like. . Hereinafter, it demonstrates concretely with the manufacturing process of the capacitor | condenser 1. FIG.

  First, a method for manufacturing the multilayer wiring board built-in capacitor 1 of the present invention will be described with reference to FIGS. As shown in FIG. 5 (5-1), a dielectric sheet 41 made of barium titanate before firing that becomes the dielectric layer 3 after firing is prepared, and the first internal electrode is fired by screen printing or the like on its surface. A conductor layer 42 made of nickel or the like to be the layer 4 is formed to produce a plurality of first ceramic green sheets 40a. At this time, in the conductor layer 42, a clearance hole 42a before firing, which becomes the clearance hole 4a after firing, is formed in a predetermined pattern.

  Similarly, as shown in FIG. 5 (5-2), a dielectric sheet 43 made of barium titanate before firing, which becomes the dielectric layer 3 after firing, is prepared, and after firing by screen printing or the like on the surface thereof. 2 Conductor layer 44 to be internal electrode layer 5 is formed to produce a plurality of second ceramic green sheets 40b. At this time, in the conductor layer 44, a clearance hole 44a before firing, which becomes the clearance hole 5a after firing, is formed in a predetermined pattern. Then, the second ceramic green sheet 40b is laminated on the first ceramic green sheet 40a.

  Subsequently, as shown in FIG. 5 (5-3), a predetermined number of the first ceramic green sheets 40a and the second ceramic green sheets 40b that are produced are stacked alternately, and finally the conductor. A dielectric sheet 40c having no layer is laminated. Thereafter, the laminate is pressed under a predetermined condition to produce a green laminate 45 that becomes the capacitor body 2 after firing.

  Next, as shown in FIG. 6 (6-1), the green laminated body 45 is formed by a method such as a laser at a position corresponding to the clearance holes 42a and 44a formed in the first and second ceramic green sheets 40a and 40b. Via holes 46h and 47h penetrating in the thickness direction are drilled.

  Next, as shown in FIG. 6 (6-2), a conductive paste made of nickel or the like is press-fitted into the drilled via holes 46h and 47h by screen printing or the like, and the first and second via conductors 6 are fired after firing. , 7 are formed. First and second via conductors 46, 47 are formed. Furthermore, the first and second outer electrode layers 8 and 9 and the first and second dummy electrode layers 10 and 11 after firing on the first and second main surfaces 45a and 45b of the green laminate 45 are formed. External conductor layers 48 and 49 and first and second dummy conductor layers 50 and 51 are formed. Specifically, the first and second external electrode layers 48 and 49 and the conductor layers to be the first and second dummy electrode layers 50 and 51 are formed by screen printing or the like using a conductive paste made of nickel or the like. Thereafter, degreasing and firing are performed under predetermined conditions to produce a capacitor 1 in which each element is formed under predetermined conditions (see FIG. 1). The first and second external electrode layers 8 and 9, the first and second external conductor layers 48 and 49 that become the first and second dummy electrode layers 10 and 11, and the first and second dummy conductor layers 50 are also provided. , 51 may be formed by metallization after degreasing and baking under predetermined conditions. In addition, only the first and second dummy conductors 50 and 51 to be the first and second dummy electrode layers 10 and 11 may be formed by metallization after degreasing and firing under predetermined conditions.

  The capacitor 1 can be disposed inside the first wiring multilayer portion L1, for example, by the following procedure. First, the core conductor layer M1 and the insulating resin layer 16 (V1) are formed on the substrate core 12, and the first and second external electrode layers are formed on the insulating resin layer 16 (V1) formed on the substrate core 12. The capacitor main body 2 on which 8, 9 and the first and second dummy electrode layers 10, 11 are formed is disposed. Thereafter, the insulating resin layer 16 (V2) is disposed on the capacitor body 2, and these are pressed while being heated. Thereby, the insulating resin layer 16 (V2) on the capacitor body 2 flows to the side of the capacitor body 2, and the capacitor body 2 is arranged within the thickness of the insulating resin layer 16 (V2). Thereafter, via holes 46h and 47h are formed immediately above the conductor layer M2 so as to penetrate the capacitor body 2, the first and second external electrode layers 6 and 7, and the insulating resin layer 16 (V2). A via conductor 34 connected to the conductor layer in 47h is formed to complete the capacitor 1. In this case, the via conductor 34 can be formed by using, for example, via paste or plating that becomes the via conductor 34 after thermosetting. Further, thereafter, an insulating resin layer 16 (V3) is formed on the capacitor 1.

  Thereafter, the first wiring laminated portion L1, the solder resist layer 18 and the like made of the insulating resin layer 16 and the conductor layer can be laminated by a known build-up method, and the multilayer wiring board 100 can be manufactured ( (See FIG. 4).

  Next, another embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 7 is a perspective view of another example of the capacitor 61 according to the present invention, and FIG. 8 schematically shows a longitudinal sectional view of another example of the capacitor 61 according to the present invention.

  As shown in FIGS. 7 and 8, the capacitor 61 includes first and second metal foils (internal electrode layers) 62 made of a conductive material such as nickel and high dielectric constant ceramics such as barium titanate. Dielectric layers 63, 63 and first and second conductor layers (internal electrode layers) 64, 64 made of a conductive material such as nickel, and first and second dielectric layers on both front and back surfaces of the metal foil 62 63 and 63 and the first and second conductor layers 64 and 64 are laminated in this order, and the metal foil 62 and the first and second conductor layers 64 and 64 are formed in an electrically insulated state. The capacitor 61 is formed in a plate shape having a square shape or a rectangular shape in plan view. Further, the capacitor 61 is provided with a plurality of communication holes 65 having a circular shape in plan view and communicating in the thickness direction in a predetermined pattern, and has a plurality of different diameters. Each communication hole 65 is formed so that its diameter increases stepwise from the metal foil 62 toward the first and second dielectric layers 63 and 63 and the first and second conductor layers 64 and 64. The first and second dielectric layers 63 and 63 and the first and second conductor layers 64 and 64 are formed symmetrically with the metal foil 62 interposed therebetween. The first and second dielectric layers 63 and 63 and the first and second conductor layers 64 and 64 may be formed only on one surface of the metal foil 62, but symmetrically on both the front and back surfaces of the metal foil 62. By forming, for example, it is possible to suppress a warp that is likely to occur due to a difference in thermal expansion coefficient between the metal foil 62 and the first and second dielectric layers 63 and 63 during simultaneous firing.

  The capacitor 61 having the above-described structure in the present embodiment is configured so that the total volume of the metal-containing layer satisfies the range of 45 vol% or more and 95 vol% or less with respect to the total volume of the capacitor 61 by appropriately adjusting the conditions of each element. Can be formed. Here, each element refers to the volume (size, thickness) of the capacitor 61, the thickness of the metal foil 62, the thickness of the first and second dielectric layers 63, 63, and the first and second conductor layers 64, 64. Of the thickness. The volume of the metal-containing layer is the volume of the metal foil 62 + the volume of the first and second conductor layers 64 and 64. Furthermore, the metal-containing layer can be formed so that the ratio of the metal component is 50 vol% or more. As a result, the capacitor main body 61 has a large elastic behavior and has sufficient flexibility. In the present embodiment, as will be described later, the capacitor 61 is integrated (formed) integrally by disposing the capacitor 61 on the insulating resin layer 16 (V2) of the multilayer wiring board 100 (see FIG. 4), for example. Can do.

  Next, another method for manufacturing the capacitor 61 according to the present invention will be described with reference to FIG. First, as shown in FIG. 9 (9-1), for example, a metal foil 62 made of nickel or the like having a thickness of 10 to 40 μm and a 150 mm square is prepared, and through holes 62a are formed in a predetermined pattern by etching or the like. .

  Subsequently, before firing, the first and second dielectric layers 63 and 63 are formed on the front and back surfaces of the metal foil 62 having the through-holes 62a with a 150 mm square thickness of 0.3 μm to 10 μm. The barium titanate green sheets are laminated and pressure-bonded under predetermined conditions. The barium titanate green sheet is obtained by forming a thin film of barium titanate slurry on a carrier sheet 63s, 63s such as polyester by a known doctor blade method and drying the thin film. After laminating barium titanate green sheets on both front and back surfaces of the metal foil 62, the carrier sheets 63s and 63s are peeled off by pressure bonding under predetermined conditions.

  Further, as shown in FIG. 9 (9-2), the first and second dielectric layers 63, 63 are formed with a 150 mm square thickness of 0.3 μm to 20 μm. A nickel green sheet before firing to be the two conductor layers 64 and 64 is laminated. The nickel green sheet is obtained by forming a thin film of nickel slurry on a carrier sheet 64s, 64s such as polyester by a known doctor blade method and drying the thin film. After a nickel green sheet is laminated on the surface of the barium titanate green sheet, the carrier sheets 64s and 64s are peeled off by pressure bonding under predetermined conditions (see FIG. 9 (9-3)). In addition, 50 vol% or less of ceramic powder such as barium titanate contained in the first and second dielectric layers 63 and 63 may be mixed in the slurry forming the nickel green sheet. By mixing the same components as the first and second dielectric layers 63 and 63 into the first and second conductor layers 64 and 64, the first and second dielectric layers 63 and 63 and the first and second conductor layers are mixed. Adhesiveness can be further improved when 64 and 64 are fired simultaneously. When the ceramic powder is mixed in an amount of more than 50 vol%, there is a possibility that a decrease in conductivity such as an increase in resistance after firing or a decrease in flexibility may occur. Here, the first and second dielectric layers 63 and 63 and the first and second conductor layers 64 and 64 may be laminated by pressing them under a predetermined condition after being laminated.

  Next, as shown in FIG. 9 (9-4), the first and second dielectric layers 63 and 63 and the first and second conductor layers 64 and 64 are positioned at positions corresponding to the through holes 62 a of the metal foil 62. Through holes 63a and 63a and through holes 64a and 64a penetrating in the thickness direction are drilled from both sides by a method such as laser.

  Thereafter, the obtained laminate is degreased and fired under predetermined conditions, and is cut into, for example, a 15 mm square by a cutting machine (not shown) to produce a capacitor 61 having communication holes 65 formed in a predetermined pattern.

  Next, the obtained capacitor 61 is installed (mounted) at a predetermined position in the first wiring laminated portion L1 of the multilayer wiring board 100 formed by a known build-up method or the like.

  Thereafter, the first wiring laminated portion L1 made of the insulating resin layer and the conductor layer, the solder resist layer 18 and the like can be laminated by a known build-up method, and the multilayer wiring board 100 (see FIG. 4) is manufactured. can do. The capacitor 1 built in the multilayer wiring board 100 in FIG. 4 is the capacitor 1 in which the dielectric layers and the internal electrode layers in the above-described embodiment are alternately stacked. The capacitor 61 in this embodiment is the same as the capacitor 61 in this embodiment. Although the structure is different, for example, the capacitor 61 can be built in the multilayer wiring board 100 by the following procedure.

  The capacitor 61 can be disposed inside the first wiring laminated portion L1. First, the capacitor 61 is disposed on the insulating resin layer 16 (V2) formed on the substrate core 12. Thereafter, the insulating resin layer 16 (V2) is further disposed on the capacitor 61, and these are pressurized while being heated. Thereby, the insulating resin layer 16 (V2) on the capacitor 61 flows to the side of the capacitor 61, and the capacitor 61 is disposed within the thickness of the insulating resin layer 16. Thereafter, a via hole that penetrates the insulating resin layer 16 (V1, V2) and the capacitor 61 is formed immediately above the conductor layer M1, and a via conductor 34 connected to the conductor layer in the via hole is formed. 61 is electrically connected to complete. The via conductor 34 in this case can be formed by using, for example, via paste or plating that becomes the via conductor 34 after thermosetting. Thereafter, an insulating resin layer 16 (V3) is formed on the capacitor 61.

  In order to confirm the effect of the present invention, samples of Examples 1 to 3 and Comparative Example 1 were prepared, and the following experiment was performed.

Example 1
A capacitor having the structure of the via array type terminal shown in the capacitor 1 (see FIG. 1) described above was manufactured by providing the external dimensions of 15 mm × 15 mm, the thickness of 83.5 μm, and chamfered portions at the four corners. First, a 2 μm thick internal layer in which a dielectric layer made of barium titanate having a thickness of 4.5 μm and nickel is mixed so that the volume ratio of barium titanate is 6: 4 by a commonly used sheet lamination method. The electrode layers were alternately laminated so that seven dielectric layers and six internal electrode layers were formed such that the dielectric layers were located on the outermost layers of the front and back surfaces. Next, 500 via conductors having a diameter of 100 μm penetrating in the thickness direction are formed in a predetermined pattern by the above-described process, and an external electrode layer and a dummy electrode layer having a thickness of 20 μm and a diameter of 200 μm are formed on the front and back surfaces of the laminate. Formed. The volume ratio of the metal-containing layer at this time was 54 vol% (45 vol% or more and 95 vol% or less) of the entire capacitor volume (dielectric layer volume + metal containing layer volume).

(Example 2)
In the same manner as in Example 1, a capacitor having a via array type terminal structure was manufactured with external dimensions of 15 mm × 15 mm, thickness of 83.5 μm, and chamfered portions at four corners. First, a 2 μm thick internal layer in which a dielectric layer made of barium titanate having a thickness of 4.5 μm and nickel is mixed so that the volume ratio of barium titanate is 9: 1 by a commonly used sheet lamination method. The electrode layers were alternately laminated so that seven dielectric layers and six internal electrode layers were formed such that the dielectric layers were located on the outermost layers of the front and back surfaces. Next, 500 via conductors having a diameter of 100 μm penetrating in the thickness direction are formed in a predetermined pattern by the above-described process, and an external electrode layer and a dummy electrode layer having a thickness of 20 μm and a diameter of 200 μm are formed on the front and back surfaces of the laminate. Formed. The volume ratio of the metal-containing layer at this time was 54 vol% (45 vol% or more and 95 vol% or less) of the entire capacitor volume (dielectric layer volume + metal containing layer volume).

(Example 3)
A capacitor having a via array type terminal structure shown in the capacitor 61 (see FIG. 7) described above was manufactured with an external dimension of 15 mm × 15 mm and a thickness of 60 μm. First, a nickel foil having a thickness of 30 μm in which through holes having a diameter of 70 μm or more and 200 μm or less are formed by etching is prepared, and a dielectric layer made of barium titanate having a thickness of 5 μm is laminated on the front and back surfaces of the nickel foil, and further, A conductor layer having a thickness of 10 μm in which nickel was mixed so that the volume ratio of barium titanate to 6: 4 was laminated on the upper layer. 500 vias with a diameter of 150 μm penetrating in the thickness direction across two layers of the dielectric layer and the conductor layer were formed in a predetermined pattern. Thereafter, the obtained laminate was fired under predetermined conditions to produce a capacitor body. The volume ratio of the metal-containing layer at this time was 84 vol% (45 vol% or more and 95 vol% or less) of the entire capacitor volume (dielectric layer volume + metal containing layer volume).

(Comparative Example 1)
As a comparative example, as shown in FIG. 10, as in Example 1, a capacitor having a via array type terminal structure was manufactured with an external dimension of 15 mm × 15 mm and a thickness of 79.5 μm. First, a 2 μm thick internal layer in which a dielectric layer made of barium titanate having a thickness of 4.5 μm and nickel is mixed so that the volume ratio of barium titanate is 6: 4 by a commonly used sheet lamination method. The electrode layers were laminated so that seven dielectric layers and four internal electrode layers were alternately arranged at the center, and the dielectric layers were positioned on the outermost layers on both the front and back surfaces. Next, 500 via conductors having a diameter of 100 μm penetrating in the thickness direction were formed in a predetermined pattern by the above-described process, and an external electrode layer having a thickness of 20 μm and a diameter of 200 μm was formed on the front and back surfaces of the laminate. The volume ratio of the metal-containing layer at this time was 26 vol% (below 45 vol%) of the entire capacitor volume (dielectric layer volume + metal-containing layer volume). In FIG. 10, parts having the same functions as those of the above-described embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  The following experiments were performed and evaluated for Examples 1 to 3 and Comparative Examples prepared under the above conditions.

(1) Bending test In order to measure the bending strength of each sample obtained, as shown in the conceptual diagram showing the measuring method in FIG. 11, the pressing surface 60a formed with curved surfaces (curvatures) of various radii of curvature R Several kinds of jigs 60 having the above-mentioned are produced and pressed until the surface of each sample is in a state along the pressing surface 60a, the radius of curvature R of the pressed jig 60 and the linear length in the surface direction of the sample. The bending distance d in the thickness direction with respect to W was recorded and measured. It should be noted that the possible bending radius R and the possible bending distance d were determined based on whether or not they were subsequently broken.

(2) Load-bearing test When laminating the resin insulation layer, pressurization was performed with a press to determine whether or not the capacitor had cracks, and then the electrical characteristics (capacitor capacity, withstand voltage) were evaluated. .

(3) Reliability test The produced capacitor built-in substrate is immersed in a -55 ° C liquid tank and + 125 ° C liquid tank alternately for 1000 cycles to conduct a thermal shock test, and the capacitance value and resistance value before and after the test are measured. did. There was no change in capacitance and resistance before and after the test.

  Next, Table 1 shows the test results in Examples 1 to 3 and Comparative Example 1.

  As a result of the experiment, as shown in Table 1, in Example 1, when the jig 60 having a radius of curvature R of the pressing surface 60a is pressed to 550 mm, the linear distance W in the surface direction of the sample is thicker than 15 mm. It was possible to bend the bending distance d in the vertical direction to 0.2 mm. Moreover, even after bending, no cracks were generated in the capacitor itself, and no deterioration in electrical characteristics was observed. Using this capacitor, when the load resistance test was performed with the press pressure when laminating the insulating resin layer, there was no cracking in the capacitor, and the electrical characteristics (capacitor capacity, withstand voltage) also changed before and after the load resistance test. There was no. Although this capacitor was placed and embedded between insulating resin layers in the build-up process of the multilayer wiring board, it was possible to incorporate the capacitor without cracks. In addition, there was no problem in reliability evaluation such as a thermal shock test.

  In Example 2, when the jig 60 whose radius of curvature R of the pressing surface 60a is 400 mm is pressed, the linear distance W in the surface direction of the sample is 15 mm and the bending distance d in the thickness direction is up to 0.3 mm. It was possible to bend. Moreover, even after bending, no cracks were generated in the capacitor itself, and no deterioration in electrical characteristics was observed. Using this capacitor, when the load resistance test was performed with the press pressure when laminating the insulating resin layer, there was no cracking in the capacitor, and the electrical characteristics (capacitor capacity, withstand voltage) also changed before and after the load resistance test. There was no. Although this capacitor was placed and embedded between insulating resin layers in the build-up process of the multilayer wiring board, it was possible to incorporate the capacitor without cracks. In addition, there was no problem in reliability evaluation such as a thermal shock test.

  In Example 3, when the jig 60 whose radius of curvature R of the pressing surface 60a is 21.5 mm is pressed, the linear distance W in the surface direction of the sample is 15 mm and the bending distance d in the thickness direction is up to 5 mm. It was possible to bend. Moreover, even after bending, no cracks were generated in the capacitor itself, and no deterioration in electrical characteristics was observed. Using this capacitor, when the load resistance test was performed with the press pressure when laminating the insulating resin layer, there was no cracking in the capacitor, and the electrical characteristics (capacitor capacity, withstand voltage) also changed before and after the load resistance test. There was no. Although this capacitor was placed and embedded between insulating resin layers in the build-up process of the multilayer wiring board, it was possible to incorporate the capacitor without cracks. In addition, there was no problem in reliability evaluation such as a thermal shock test.

  In Comparative Example 1, when the jig 60 having a radius of curvature R of the pressing surface 60a of 2250 mm is pressed, the linear distance W in the surface direction of the sample is 15 mm and the bending distance d in the thickness direction is 0.05 mm. It could only be bent. In addition, after bending, the capacitor itself was found to have cracks and a decrease in electrical characteristics. Using this capacitor, a load resistance test was performed at the pressing pressure when laminating the insulating resin layer. As a result, cracks were generated in the capacitor, and the electrical characteristics (capacitor capacity, withstand voltage) were also reduced.

  As described above, it was possible to obtain a reliable capacitor in Examples 1 to 3. That is, flexibility could be imparted by setting the volume of the metal-containing layer contained in the capacitor in the range of 45 vol% or more and 95 vol% or less with respect to the total volume of the capacitor itself. Specifically, it has a bending strength that enables elastic deformation within a range where the radius of curvature of the capacitor is 700 mm or less (20 mm or more and 550 mm or less). This makes it possible to withstand mechanical and thermal stresses caused by warping or deformation of the multilayer wiring board when it is built in the multilayer wiring board, and to prevent the occurrence of cracks, etc. Was able to secure. On the other hand, in Comparative Example 1, the volume ratio of the metal-containing layer was insufficient and did not have flexibility, and cracks occurred with almost no bending.

  In the present invention, the present invention is not limited to the above embodiment, and is not limited to being built in the insulating resin layer of the build-up layer, but may be embedded in a substrate core forming the core of the multilayer wiring board. It is possible to provide various modified examples within the scope of the present invention according to the purpose and application.

1 is a longitudinal sectional view of a capacitor for incorporating a multilayer wiring board according to the present invention. The top view (bottom view) of the capacitor for a multilayer wiring board according to the present invention. 1 is a cross-sectional view of a multilayer wiring board built-in capacitor according to the present invention. 1 is a cross-sectional view of a multilayer wiring board according to the present invention. The manufacturing process figure of the capacitor for multilayer wiring board built-in concerning this invention. Manufacturing process figure following FIG. The perspective view of the capacitor for multilayer wiring board built-in of another example. The longitudinal cross-sectional view of the capacitor for a multilayer wiring board of another example. Another example of a method for manufacturing a capacitor for built-in multilayer wiring board. The longitudinal cross-sectional view of the capacitor for multilayer wiring board built-in of a comparative example. The conceptual diagram which shows the measuring method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,61 Multilayer wiring board built-in capacitor 2, Capacitor body 3,63 Dielectric layer 4, 5, 62, 64 Internal electrode layer 6, 7, Via conductor 8, 9 External electrode layer 10, 11 Dummy electrode layer 12 Substrate core 16, 26 Insulating resin layer 18, 28 Solder resist layer 25, 27 Metal terminal pad 30 Through hole 34, 35 Via conductor 100 Multilayer wiring board

Claims (6)

A capacitor for built-in multilayer wiring board,
The multilayer wiring board built-in capacitor, wherein the volume of the metal-containing layer contained in the capacitor is in the range of 45 vol% to 95 vol% with respect to the total volume of the capacitor itself.   The capacitor for a built-in multilayer wiring board according to claim 1, wherein the ratio of the metal component in the metal-containing layer is 50 vol% or more.   The multilayer wiring board built-in capacitor according to claim 1, wherein the capacitor is formed with a thickness of 200 μm or less.   When a predetermined jig is pressed from the thickness direction, the straight line length in the surface direction is W, and the bending distance in the thickness direction is d. 4. The multilayer wiring board built-in capacitor according to any one of claims 1 to 3, wherein the capacitor is capable of being bent into a bent shape.   The multilayer wiring board built-in according to any one of claims 1 to 4, wherein when a predetermined jig is pressed from the thickness direction, it can be elastically deformed within a curvature range in which a radius of curvature is 700 mm or less. Capacitor.   A multilayer wiring board comprising the multilayer wiring board built-in capacitor according to any one of claims 1 to 5.

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