JP2007242946A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which simultaneously form a polysilicon gate electrode and an NiSi full-silicide gate electrode on a high permittivity gate insulating film. <P>SOLUTION: A high permittivity gate insulating film 106 and a polysilicon gate electrode 108 are formed on a p-well 103, and a high permittivity gate insulating film 107 and a polysilicon gate electrode 109 are formed on an n-well 104. Next, an interlayer film 116 is formed so that the surfaces of the polysilicon gate electrodes 108, 109 may be exposed. Further, an Ni film 117 is formed for covering the surfaces of the interlayer film 116 and the polysilicon gate electrodes 108, 109. Subsequently, an Si film 118 is formed on a portion including a region opposite to the polysilicon gate electrode 108, and not including a region opposite to the polysilicon gate electrode 109 of the surface of the Ni film 117. Further, the electrodes 108, 109 are silicidized by heat treatment, and then the film on the interlayer film 116 is removed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device having a high dielectric constant gate insulating film (high-k gate insulating film) and a silicide gate electrode.

  As a MISFET (Metal Insulator Semiconductor Field Effect Transistor) used in a semiconductor integrated circuit, a MOS (Metal Oxide Semiconductor) FET is known. In the MOSFET, the gate insulating film is formed of a silicon oxide film, and the gate electrode is formed of polysilicon.

  Along with the high integration of integrated circuits and the like, FETs have been miniaturized, and the area of the gate insulating film tends to be small. The gate insulating film needs to be formed thinner as the area becomes smaller. This is because it is necessary to sufficiently increase the dielectric constant of the gate insulating film in order to operate the FET at a high frequency.

  When the thickness of the gate insulating film is reduced, the influence of depletion of polysilicon forming the gate electrode cannot be ignored. This is because the thinner the gate insulating film, the larger the electric field applied to the gate electrode, and hence the larger the depletion layer generated in the gate electrode. As a result, the gate insulating film becomes substantially thick (see paragraphs 0002 to 0003 of Patent Document 1 below). In order to prevent the generation of a depletion layer, it is desirable to employ a metal gate electrode. As a technique for forming the metal gate electrode, for example, a full silicidation technique is known. The full silicide gate electrode can be formed by depositing a metal film on the polysilicon film and then thermally diffusing it at a relatively low temperature (see paragraph 0025 of Patent Document 2 below). This technique has an advantage that a conventional MOSFET process technique can be used as it is. Therefore, by adopting a full silicide gate electrode, a MOSFET having a sufficiently thin gate oxide film can be provided at low cost.

  Further, when the thickness of the gate insulating film is reduced, there is a disadvantage that the leakage current increases due to the quantum tunnel effect. As a technique for solving such a drawback, a technique using a high dielectric constant gate insulating film has already been proposed (see paragraphs 0002 to 0003 of Patent Document 2 below). The high dielectric constant gate insulating film is also referred to as a high-k gate insulating film, and means an insulating film having a dielectric constant k higher than that of the silicon oxide film. By employing a high dielectric constant gate insulating film, the film thickness can be increased while ensuring a dielectric constant equal to or higher than that of the silicon oxide film, and thus the quantum tunnel effect can be suppressed. As high dielectric constant gate insulating films, hafnium (Hf), zirconium (Zr) -based oxide films, and the like are known.

  Thus, in order to realize a highly integrated and high-performance integrated circuit, it is desirable to employ a full silicide gate electrode, and it is desirable to employ a high dielectric constant gate insulating film.

  However, when the full silicide gate electrode is formed on the high dielectric constant gate insulating film, there is a disadvantage that the operation threshold voltage of the FET shifts. For example, in the case of an n-type FET employing an HfAlO film as a high dielectric constant gate insulating film, the threshold voltage when using a full silicide gate electrode is 0.4 compared to when using a polycide gate electrode. Increases by about bolt. Furthermore, when a full silicide gate electrode is formed on a high dielectric constant gate insulating film, it becomes difficult to control the threshold voltage of the FET by doping impurities into the gate electrode.

  On the other hand, it is possible to adjust the threshold voltage by appropriately selecting the composition of the full silicide gate electrode. That is, by individually selecting the composition of the silicide that forms the gate electrode of the p-type FET and the composition of the silicide that forms the gate electrode of the n-type FET, it is possible to optimize both the threshold voltages of these FETs. it can. In addition, the threshold voltage can be adjusted by adopting a polycide gate electrode for one of the p-type FET and the n-type FET.

In order to form a full silicide gate electrode having a desired composition, the thicknesses of the polysilicon film and the metal film may be adjusted. For example, when the film thickness ratio TNi / TSi between the polysilicon film and the metal film (here nickel film) is 0.67 or less, NiSi is formed by silicidation, but TNi / TSi is 1.33 or more. In this case, Ni ₃ Si is formed (see FIGS. 1 and 2 of Non-Patent Document 1 below). For this reason, conventionally, after forming a uniform polysilicon film or metal film in the p-type FET formation region and the n-type FET formation region, the film thickness is adjusted by selectively etching the film in one region. I was going.

  However, it is difficult to adjust the thickness of the polysilicon film with high accuracy by etching, and there is a drawback that the performance of the MOSFET is likely to deteriorate due to etching damage and contamination.

Further, in the above-described full silicidation process, when a wide gate electrode and a narrow gate electrode are mixed, the metal (Ni, Pt, etc.) tends to be rich as the gate width is narrow. Therefore, there are cases where full silicide gate electrodes having different compositions are formed despite the same film thickness (see Non-Patent Document 2 below). For this reason, there is a drawback that gate electrodes having different threshold voltages are formed according to the width of the gate electrode.
JP 2006-24594 A JP 2005-243678 A Kensuke Takahashi et al., 'Dual Workfunction Ni-Silicide / HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45nm-node LSTP and LOP Devices' Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International. 13 -15 Dec. 2004 JAKittl et al., 'Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths' 2005 Symposium on VLSI Technology Digest of Technical Papers

  An object of the present invention is to provide a method of manufacturing a semiconductor device that can manufacture a high-performance and high-reliability FET by using a high dielectric constant gate insulating film and a full silicide gate electrode.

  According to the method for manufacturing a semiconductor device of the present invention, first and second high dielectric constant gate insulating films and first and second silicon dielectric layers on the surface of a semiconductor substrate and the first and second high dielectric constant gate insulating films are formed. A first step of forming a gate electrode; a second step of forming an interlayer film on the surface of the semiconductor substrate so that the surfaces of the first and second silicon gate electrodes are exposed; A third step of forming a first film of a metal for forming a silicide so as to cover the surface of the two silicon gate electrode; a second step including a region of the surface of the first film facing the first silicon gate electrode; A compound forming material for forming a compound with the silicide forming metal is supplied to a portion not including the region facing the silicon gate electrode, and the first and second silicon gate electrodes are silicided. Process.

  According to the present invention, since the compound forming material is supplied only to the first silicon gate electrode by the heat treatment in the fourth step, the amount of metal contributing to silicidation is set to the first polysilicide gate electrode side. It can be made different on the second polysilicide gate electrode side. Therefore, according to the present invention, the polycide gate electrode and the full silicide gate electrode having a desired composition can be formed without impairing the performance and reliability of the FET.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the size, shape, and arrangement relationship of each component are shown only schematically to the extent that the present invention can be understood, and the numerical conditions described below are merely examples. .

First Embodiment Hereinafter, a method for fabricating a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

  In this embodiment, a gate electrode in which polysilicon and polycide are stacked is formed on a high dielectric constant gate insulating film of an n-type FET, and NiSi full is formed on a high dielectric constant gate insulating film of a p-type FET. It is an example of the manufacturing method which forms a silicide gate electrode.

  1 and 2 are process cross-sectional views for explaining a method for manufacturing a semiconductor device according to this embodiment.

  (1) First, an element isolation region (STI: Shallow Trench Isolation) 102 is formed on the surface of the semiconductor substrate 101 using a normal process technique, and a p-well 103 (that is, an n-type FET formation region is formed by introducing impurities, etc. ) And an n-well 104 (that is, a p-type FET formation region) is formed (see FIG. 1A).

  (2) Next, a high dielectric constant film (high-k film) 105 a of about 1.6 to 3 nm, for example, is formed on the entire surface of the semiconductor substrate 101. As a material for forming the high dielectric constant film 105a, for example, HfAlO can be adopted, but it is not particularly limited. Further, a polysilicon film 105b of, eg, 100 nm is formed on the surface of the high dielectric constant film 105a using a normal deposition technique or the like (see FIG. 1B).

  (3) Then, after forming a mask pattern (not shown) using a normal photolithography method or the like, the high dielectric constant film 105a and the polysilicon film 105b are patterned using a dry etching method or the like, whereby a high dielectric constant gate is formed. Insulating films 106 and 107 and polysilicon gate electrodes 108 and 109 are formed (see FIG. 1C).

  (4) The p-well 103 is doped with an n-type threshold control impurity to form a sidewall 110 covering the side surfaces of the high dielectric constant gate insulating film 106 and the polysilicon gate electrode 108, and further, an n-type high concentration impurity is added. Dope. As a result, the n-type extension region 111 and the n-type high-concentration impurity region 112 are formed, and the polysilicon gate electrode 108 is doped with impurities. However, the n-type threshold control impurity may not be doped or may be counter-doped. Similarly, a sidewall 113 covering the side surfaces of the high dielectric constant gate insulating film 107 and the polysilicon gate electrode 109, a p-type extension region 114, and a p-type high-concentration impurity region 115 are formed in the n-well 104. At the same time, the polysilicon gate electrode 109 is doped with impurities (see FIG. 1D). However, when doping a p-type high-concentration impurity, in order to prevent boron penetration, a hard mask may be formed on the polysilicon gate electrode 109 and the electrode 109 may not be doped.

  (5) Subsequently, an insulating film of about 200 to 500 nm, for example, is deposited on the entire surface of the semiconductor substrate 101, and polysilicon gate electrodes 108 and 109 are further formed by using chemical mechanical polishing (CMP) or the like. To expose the surface. Thus, an interlayer film 116 is formed (see FIG. 2A).

  (6) Thereafter, a Ni film 117 is formed so as to cover the surface of the interlayer film 116 and the polysilicon gate electrodes 108 and 109 by using a normal thin film forming method. Further, a Si film 118 is formed on a portion of the surface of the Ni film 117 that includes a region facing the polysilicon gate electrode 108 and does not include a region facing the polysilicon gate electrode 109. In this embodiment, the Si film 118 is formed only on the p well 103, and the Si film 118 is not formed on the n well 104 (see FIG. 2B).

  In this embodiment, the polysilicon gate electrodes 109 and 109, the Ni film 117, and the Si film 118 are fully silicided in the step (7) described below. The polysilicon gate electrode 108 is selected to be silicided leaving the vicinity of the interface with the high dielectric constant gate insulating film 106. Here, the thickness of the polysilicon gate electrodes 108 and 109 is 100 nm, the thickness of the Ni film 117 is 80 nm, and the thickness of the Si film 118 is 100 nm.

  (7) The polysilicon gate electrodes 108 and 109 are silicided by heating the semiconductor substrate 101 at, for example, 400 to 500 ° C. for an appropriate time (see FIG. 2C).

  In this heat treatment, the Ni film 117 on the p-well 103 reacts with both the polysilicon gate electrode 108 and the Si film 118. For this reason, the Ni film 117 cannot supply enough nickel to silicide all of the polysilicon gate electrode 108. Therefore, in the polysilicon forming the gate electrode 108, only the upper layer portion (portion on the Ni film 117 side) is silicided, and the lower layer portion (portion near the interface with the high dielectric constant gate insulating film 106) is not silicided. As a result, the gate electrode of the p-well 103 has a two-layer structure of the polysilicon layer 119a and the silicide layer 119b.

  On the other hand, the Ni film 117 on the n-well 104 reacts only with the polysilicon gate electrode 109. For this reason, all the polysilicon forming the gate electrode 109 becomes silicide. As a result, the NiSi full silicide gate electrode 120 is formed in the n-well 104.

  (8) Thereafter, the alloy layer on the interlayer film 116 is removed by using, for example, a chemical mechanical polishing method. Thus, the gate electrodes 119 and 120 are completed (see FIG. 2D).

  As described above, in this embodiment, the thicknesses of the Ni film 117 and the Si film 118 are set so that the polysilicon gate electrode 109 is completely silicided and the polysilicon gate electrode 108 is highly dielectricated in the step (7). It is selected so as to be silicided while leaving the vicinity of the interface with the rate gate insulating film 106. Thus, the NiSi full silicide gate electrode 120 and the polysilicon gate electrode 119a can be simultaneously formed without reducing the thickness of the polysilicon film 105b and the Ni film 117 by etching.

  Therefore, according to this embodiment, it is possible to adjust the threshold voltages of the n-type FET and the p-type FET at a low manufacturing cost without impairing the performance of the FET. According to the study by the inventors of the present invention, for example, when a NiSi full silicide gate electrode is formed on both an n-type FET and a p-type FET, the threshold voltage of the n-type FET +0.8 volts and the threshold voltage of the p-type FET In this embodiment, the threshold voltage of the n-type FET was +0.45 volts and the threshold voltage of the p-type FET was -0.45 volts.

  In this embodiment, the full silicide gate electrode is formed of NiSi. However, it can be formed of other metal and silicon. For example, platinum, titanium, cobalt, tungsten, or the like can be used as a metal for silicidation. That is, even when these metal films are used instead of the Ni film 117, the manufacturing method according to this embodiment can be applied.

In addition, in this embodiment, silicon is adopted as a material to be formed on the surface of the Ni film 117 (that is, a material for forming the film 118). However, the material is not particularly limited to silicon as long as it is a material that reacts with the film 117. For example, titanium, germanium, or the like can be used as a material for forming the film 118.
In this embodiment, the silicon gate electrode is formed of polysilicon, but may be formed of amorphous silicon.

Second Embodiment Next, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.

In this embodiment, a NiSi full silicide gate electrode is formed on the high dielectric constant gate insulating film of the n-type FET, and a Ni ₃ Si full silicide gate is formed on the high dielectric constant gate insulating film of the p-type FET. It is an example of the manufacturing method which forms an electrode.

  FIG. 3 is a process sectional view for explaining a main part of the manufacturing process of the semiconductor device according to this embodiment.

  (1) First, similarly to the steps (1) to (5) of the first embodiment (see FIGS. 1A to 2A), the respective parts 102 to 116 are formed on the semiconductor substrate 101. .

  (2) Next, the Ni film 301 is formed so as to cover the surface of the interlayer film 116 and the polysilicon gate electrodes 108 and 109 by using a normal thin film forming method. Further, a Si film 302 is formed on a portion of the surface of the Ni film 301 including a region facing the polysilicon gate electrode 108 and not including a region facing the polysilicon gate electrode 109 (FIG. 3A). )reference).

  As described above, the composition when silicide is formed from Ni and Si depends on the film thickness ratio between the Ni film and the Si film (see Non-Patent Document 1). In contrast, the composition of the silicide electrode formed in this embodiment varies depending on the thickness of the polysilicon gate electrodes 108 and 109, the thickness of the Ni film 301, and the thickness of the Si film 302. In this embodiment, the polysilicon gate electrodes 108 and 109 have a thickness of 100 nm, the Ni film 301 has a thickness of 140 nm, and the Si film 302 has a thickness of 100 nm.

  (3) The polysilicon gate electrodes 108 and 109 are silicided by heating the semiconductor substrate 101 at, for example, 400 to 500 ° C. for an appropriate time (see FIG. 3B).

Thus, the gate electrode 108 becomes a NiSi full silicide gate electrode 303 and the gate electrode 109 becomes a Ni ₃ Si full silicide gate electrode 304.

  (4) Thereafter, the film on the interlayer film 116 is removed using, for example, a chemical mechanical polishing method. Thus, the gate electrodes 303 and 304 are completed (see FIG. 3C).

Thus, in this embodiment, the NiSi full silicide gate electrode 303 and the Ni ₃ Si full silicide gate electrode 304 can be formed simultaneously.

  Therefore, according to this embodiment, it is possible to adjust the threshold voltages of the n-type FET and the p-type FET at a low manufacturing cost without impairing the performance of the FET.

  The point that the gate electrode can be silicided with other metals such as platinum, titanium, cobalt, and tungsten, and the point that the film 302 can be formed with titanium, germanium, or the like is the same as in the first embodiment. When a Pt film is used instead of the Ni film 301, for example, if the polysilicon gate electrodes 108 and 109 have a thickness of 50 nm, the Pt film 301 has a thickness of 200 nm, and the Si film 302 has a thickness of 150 nm, A PtSi full silicide gate electrode 303 and a PtSix (x <1) full silicide gate electrode 304 can be formed simultaneously.

Third Embodiment Next, a method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG.

  This embodiment is an example of a method using ion implantation instead of the film 118.

  FIG. 4 is a process cross-sectional view for explaining the main part of the manufacturing process of the semiconductor device according to this embodiment.

  (1) First, similarly to the steps (1) to (5) of the first embodiment (see FIGS. 1A to 2A), the respective parts 102 to 116 are formed on the semiconductor substrate 101. .

  (2) Next, a Ni film 401 is formed so as to cover the surfaces of the interlayer film 116 and the polysilicon gate electrodes 108 and 109 by using a normal thin film forming method (see FIG. 4A).

(3) Subsequently, a resist film is formed on the surface of the Ni film 401, and further patterned by using a normal photolithography method or the like to expose a region facing the polysilicon gate electrode 108 and to form polysilicon. A resist pattern 402 is formed to cover a region facing the gate electrode 109. Then, Si ions are implanted into the Ni film 401 in the region facing the polysilicon gate electrode 108 by ion implantation using the resist pattern 402 as a mask (see FIG. 4B). The dose amount for ion implantation is, for example, 1 × 10 ^{16 to} 5 × 10 ¹⁶ cm ⁻² .

  In this embodiment, the thickness of the polysilicon gate electrodes 108 and 109, the thickness of the Ni film 401 and the amount of ion implantation of Si are completely silicided in the step (4) described later. The polysilicon gate electrode 108 is selected to be silicided leaving the vicinity of the interface with the high dielectric constant gate insulating film 106.

  (4) After removing the resist pattern 402, the semiconductor substrate 101 is heated at, for example, 400 to 500 ° C. for an appropriate time, thereby siliciding the polysilicon gate electrodes 108 and 109 (see FIG. 4C). ).

  In this heat treatment, the Ni film 401 on the p-well 103 reacts with both the polysilicon gate electrode 108 and the implanted Si ions. Therefore, in the polysilicon forming the gate electrode 108, only the upper layer portion (the portion on the Ni film 401 side) is silicided, and the lower layer portion (the portion near the interface with the high dielectric constant gate insulating film 106) is not silicided. . Therefore, the gate electrode 403 of the p well 103 has a two-layer structure of the polysilicon layer 403a and the silicide layer 403b.

  On the other hand, the Ni film 401 on the n-well 104 reacts only with the polysilicon gate electrode 109. For this reason, all the polysilicon forming the gate electrode 109 becomes silicide. As a result, a NiSi full silicide gate electrode 404 is formed in the n-well 104.

  (5) Thereafter, the alloy film on the interlayer film 116 is removed by using, for example, a chemical mechanical polishing method. Thus, the gate electrodes 403 and 404 are completed (see FIG. 4D).

  As described above, according to this embodiment, the NiSi full silicide gate electrode 404 and the polysilicon gate electrode 403 can be simultaneously formed without reducing the thickness of the polysilicon film 105b and the Ni film 401 by etching. .

  Therefore, according to this embodiment, it is possible to adjust the threshold voltages of the n-type FET and the p-type FET at a low manufacturing cost without impairing the performance of the FET.

  The point that the gate electrode can be silicided with other metals such as platinum, titanium, cobalt, and tungsten and the point that the film 118 can be formed with titanium, germanium, or the like are the same as in the first embodiment.

Fourth Embodiment Next, a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS.

  This embodiment is an example of a manufacturing method for forming a full silicide gate electrode having the same composition regardless of the gate width.

  5 and 6 are process cross-sectional views for explaining the main part of the manufacturing process of the semiconductor device according to this embodiment.

  (1) First, an element isolation region 502 is formed on the surface of the semiconductor substrate 501 by using a normal process technique, and a p-well 503 is formed by introducing impurities (see FIG. 5A).

  (2) Next, as in the first embodiment, a high dielectric constant film 504 of about 1.6 to 3 nm, for example, is formed on the entire surface of the semiconductor substrate 501, and a polysilicon film 505 of, eg, 100 nm is further formed. (See FIG. 5B).

  (3) Thereafter, high dielectric constant gate insulating films 506 and 507 and polysilicon gate electrodes 508 and 509 are formed in the same manner as in the first embodiment (see FIG. 5C).

  In this embodiment, the gate width of the polysilicon gate electrode 508 is formed narrow (for example, 100 to 150 nm or less), and the gate width of the polysilicon gate electrode 509 is formed wide (for example, 100 to 150 nm or more).

  (4) In the same manner as in the first embodiment, sidewalls 510 and 511, n-type extension regions 512 and 513, n-type high concentration impurity regions 514 and 515, and an interlayer film 516 are formed (see FIG. 5D). ).

  (5) Thereafter, a Ni film 517 is formed so as to cover the surfaces of the interlayer film 516 and the polysilicon gate electrodes 508 and 509 by using a normal thin film forming method. Further, a Si film 518 is formed on a portion of the surface of the Ni film 517 including a region facing the polysilicon gate electrode 508 and not including a region facing the polysilicon gate electrode 509 (FIG. 6A). )reference).

  In this embodiment, full silicide gate electrodes having the same composition are formed regardless of whether the gate widths of the polysilicon gate electrodes 508 and 509, the Ni film 517, and the Si film 518 are wide or narrow. Selected to be.

  (6) The polysilicon gate electrodes 508 and 509 are silicided by heating the semiconductor substrate 501 at, for example, 400 to 500 ° C. for an appropriate time (see FIG. 6B).

  In this heat treatment, the Ni film 517 on the polysilicon gate electrode 508 reacts with both the polysilicon gate electrode 508 and the Si film 518. For this reason, the gate electrode 508 does not become richer in Ni than the gate electrode 509. Therefore, the gate electrodes 508 and 509 become full silicide gate electrodes 519 and 520 having the same composition.

  (7) Thereafter, the film on the interlayer film 516 is removed in the same manner as in the first embodiment. Thus, gate electrodes 519 and 520 are completed (see FIG. 6C).

  Thus, according to this embodiment, even when a wide gate electrode and a narrow gate electrode are mixed, the full silicide gate electrodes 519 and 520 having the same composition can be formed. Therefore, the threshold voltage can be made the same regardless of the width of the gate electrode.

  In addition, the point which can replace the Ni film | membrane 517 with other metal films, such as platinum, titanium, cobalt, and tungsten, and the point which can form the film | membrane 518 with other metals, such as titanium and germanium, are 1st Embodiment. It is the same.

  Further, the point that ion implantation may be performed instead of the film 518 is the same as in the third embodiment.

It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 4th Embodiment. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 4th Embodiment.

Explanation of symbols

101 Semiconductor substrate 102 Element isolation region 103 P well 104 N well 105a High dielectric constant film
105b Polysilicon film 106, 107 High dielectric constant gate insulating film 108, 109 Polysilicon gate electrode 110, 113 Side wall 111 n-type extension region 112 n-type high concentration impurity region 114 p-type extension region 115 p-type high concentration impurity region 116 Interlayer film 117 Ni film 118 Si film 119, 120 Gate electrode

Claims (9)

A first step of forming first and second high dielectric constant gate insulating films and first and second silicon gate electrodes on the first and second high dielectric constant gate insulating films on the surface of the semiconductor substrate; ,
A second step of forming an interlayer film on the surface of the semiconductor substrate such that the surfaces of the first and second silicon gate electrodes are exposed;
A third step of forming a first film of silicide-forming metal so as to cover the surface of the interlayer film and the first and second silicon gate electrodes;
A compound is formed between the surface of the first film and the silicide-forming metal in a portion including a region facing the first silicon gate electrode and not including a region facing the second silicon gate electrode. A fourth step of supplying the compound forming material and siliciding the first and second silicon gate electrodes;
A method for manufacturing a semiconductor device, comprising:   The fourth step includes applying the compound-forming material to a portion of the surface of the first film that includes a region that opposes the first silicon gate electrode and does not include a region that opposes the second silicon gate electrode. The method for manufacturing a semiconductor device according to claim 1, wherein the second film is formed and then heat treatment is performed. The first and second silicon gate electrodes are gate electrodes provided in field effect transistors of different conductivity types; and
The film thicknesses of the first and second silicon gate electrodes and the first and second films are such that the second silicon gate electrode is completely silicided in the fourth step and the first silicon gate electrode is Selected to be silicided leaving the vicinity of the interface with the first high dielectric constant gate insulating film;
The method of manufacturing a semiconductor device according to claim 2. The first and second silicon gate electrodes are gate electrodes provided in field effect transistors of different conductivity types; and
The thicknesses of the first and second silicon gate electrodes and the first and second films are selected such that the first and second silicon gate electrodes are silicide gate electrodes having different compositions from each other.
The method of manufacturing a semiconductor device according to claim 2. The first and second silicon gate electrodes are gate electrodes provided in a field effect transistor of the same conductivity type;
The gate width of the first silicon gate electrode is smaller than the gate width of the second silicon gate electrode; and
The film thicknesses of the first and second silicon gate electrodes and the first and second films are selected so that the first and second silicon gate electrodes are silicide gate electrodes having the same composition.
The method of manufacturing a semiconductor device according to claim 2.   In the fourth step, the compound-forming material is applied to a portion of the surface of the first film that includes a region that opposes the first silicon gate electrode and does not include a region that opposes the second silicon gate electrode. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a step of performing ion implantation and then heat treatment. The first and second silicon gate electrodes are gate electrodes provided in field effect transistors of different conductivity types; and
The thickness of the first and second silicon gate electrodes, the thickness of the first film, and the amount of the compound forming material implanted are determined so that the second silicon gate electrode is completely silicided in the fourth step. And the first silicon gate electrode is selected to be silicided leaving the vicinity of the interface with the first high dielectric constant gate insulating film.
The method of manufacturing a semiconductor device according to claim 6. The first and second silicon gate electrodes are gate electrodes provided in field effect transistors of different conductivity types; and
A silicide gate having a composition in which the first and second silicon gate electrodes are different from each other in terms of the thickness of the first and second silicon gate electrodes, the thickness of the first film, and the injection amount of the compound forming material. Selected to be an electrode,
The method of manufacturing a semiconductor device according to claim 6. The first and second silicon gate electrodes are gate electrodes provided in a field effect transistor of the same conductivity type;
The gate width of the first silicon gate electrode is smaller than the gate width of the second silicon gate electrode; and
A silicide gate electrode having the same composition as the first and second silicon gate electrodes, wherein the thicknesses of the first and second silicon gate electrodes, the thickness of the first film, and the injection amount of the compound forming material are the same. Selected to be
The method of manufacturing a semiconductor device according to claim 6.