JP2007242067A - Nonvolatile semiconductor memory device and electric charge injection method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electric charge injection method, wherein the memory transistor is hardly disturbed. <P>SOLUTION: The method includes: a first step in which one of first and second bit lines BLj, BLk is set to have a voltage higher than that of another bit line when the electric charge is injected and both bit lines are set to have the same potential when the electric charge is not injected; and a second step for applying a gate voltage to a selected word line for injecting the electric charge, wherein the first and second steps to be performed in predetermined order are executed N times while changing the memory transistor selected in a group of N pieces of transistors. At this time, when the electric charge is injected to nearly a half (N/2 or integer nearest to N/2) of the transistors in the group, the voltage of the first bit line BLj is set higher than the voltage of the second bit line BLk in the first step, and when the electric charge is injected to nearly a half of remainder, the magnitude relation of voltages of the first and second bit lines BLj, BLk is reversed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a charge injection method for a nonvolatile semiconductor memory device, such as a so-called trap gate type, having a memory transistor in which charge storage means in a gate insulating film is discretized, and the nonvolatile semiconductor memory device.

In the memory transistor of the nonvolatile semiconductor memory device, in addition to the FG type having an FG (Floating Gate) as charge storage means for holding charges, the charge storage means (charge trap) is in the plane facing the channel and in the film thickness direction. For example, there is a MONOS (Metal-Oxide-Nitride-Oxide Semiconductor) type.
In the FG type, the charge storage means is made of a single conductive layer and is not discretized, but the charge storage means such as the MONOS type is a charge trap that is discretized and distributed in the insulating film. Therefore, the MONOS type or the like is hereinafter referred to as a dispersed-charge storage type.

  In an FG type memory transistor, a floating gate made of polysilicon or the like is stacked on a semiconductor region (channel forming region) where a channel of the memory transistor is formed via a thin insulating film, and further, for example, ONO is formed on the floating gate. A control gate is laminated via an inter-gate insulating film made of an (Oxide-Nitride-Oxide) film.

  On the other hand, in the MONOS type memory transistor, on the channel formation region, for example, a bottom oxide film made of a silicon oxide film or a silicon nitride oxide film, a charge storage film made of a nitride film or a nitride oxide film, or a silicon oxide film is made. A top oxide film is sequentially laminated, and a gate electrode is formed on the top insulating film. The FG type memory transistor and the MONOS type memory transistor are described in Patent Document 1.

FIG. 8 shows a circuit of a non-volatile semiconductor memory device composed of memory transistors having charge storage means.
The memory cell of the nonvolatile semiconductor memory device 101 shown in FIG. 8 includes memory transistors M11 to M44 arranged in a matrix.
In each memory transistor row of memory transistors M11 to M14, M21 to M24, M31 to M34, and M41 to M44 in the row direction, one word line WLi (i = 1, 2, 3, 4) is connected to each gate. ing.
In each memory transistor column of memory transistors M11 to M41, M12 to M42, M13 to M43, and M14 to M44 in the column direction, the first bit line BLk (k = 2, 4, 6, 8) connected to each drain And a bit line BL formed of a pair of second bit lines BLj (j = 1, 3, 5, 7) connected to each source. A row control circuit 301 is connected to the word line WL, and a column control circuit 401 is connected to the bit line BL.

FIG. 9 shows a cross-sectional view of an example of a memory transistor constituting the nonvolatile semiconductor memory device shown in FIG.
In the memory transistor 201 shown in FIG. 9, a first source / drain region 601 and a second source / drain region 701 are formed in a semiconductor substrate 501. Here, a region between the first source / drain region 601 and the second source / drain region 701 in the semiconductor substrate 501 is a channel formation region 801. Further, a stacked insulating film 901 is formed above the channel formation region 801, and a gate electrode G is formed on the stacked insulating film 901.

  The laminated insulating film 901 is composed of three insulating films having an ONO (Oxide-Nitride-Oxide) structure, that is, a silicon oxide film 901a, a silicon nitride film 901b, and a silicon oxide film 901c. The memory transistor 201 having such an insulating film is referred to as a MONOS type.

Next, bias conditions and operations in the case where the memory transistor 201 is an N-channel type and electrons are injected into the stacked insulating film 901 by a channel hot electron (CHE) injection method will be described.
As the bias condition, for example, the first source / drain region 601 is held at a common voltage (ground voltage), and a positive drain voltage, for example, 5 [V] is applied to the second source / drain region 701. A predetermined positive gate voltage, for example, 10 [V] is applied to the gate electrode G. On the other hand, when no charge is injected, the gate voltage (10 [V]) is not applied, or the first and second source / drain regions 601 and 701 are set to the same potential without applying the drain voltage.
In the laminated insulating film 901, many charge traps are formed mainly in the bulk of the silicon nitride film 901b and in the region centering on the boundary where the silicon nitride film 901b is in contact with the silicon oxide film 901c.

When a high gate voltage (10 [V]) is applied to the gate electrode G with the drain voltage (5 [V]) applied, a channel is formed in the channel formation region 801 and supplied from the first source / drain region 601. The electrons are accelerated in the channel, and some of them gain high energy near the second source / drain region 701 to generate hot electrons. A part of the hot electrons is attracted to the gate electrode G side by an electric field generated by applying a gate voltage, and is injected into the charge trap in the stacked insulating film 901 and held there.
On the other hand, when the gate voltage is not applied, or when the same potential is applied without applying the drain voltage to the first and second source / drain regions 601 and 701, no charge is injected.

Since the stacked insulating film 901 is formed above the channel formation region 801, the first source / drain region 601 and the first source / drain region 601 sandwiching the channel formation region 801 of the memory transistor 201 depend on the amount of charge accumulated in the stacked insulating film 901. The threshold voltage at which the drain current begins to flow between the two source / drain regions 701 varies. When a large amount of charge is accumulated in the stacked insulating film 901, the threshold voltage is relatively high, and when the charge is not injected or when the amount is small, the threshold voltage is relatively low.
This difference in threshold voltage corresponds to a data storage state of “1” or “0”.

In the discrete charge storage type memory transistor, the electron injection by the CHE injection method is limited to the local region near the drain, and the distribution of the electrons once stored is slightly changed by thermal diffusion, compared with the FG type. Very low electrical conductivity. Therefore, when the bias is applied, the direction of the drain voltage applied to the first and second source / drain regions 601 and 701 is opposite to the above, that is, the second source / drain region 701 is grounded, and the first source / drain region 601 is grounded. When a drain voltage (for example, 5 [V]) is applied to, electrons can be locally injected into the other end side of the laminated insulating film 901.
For this reason, in the discrete charge storage type memory transistor, 2-bit data can be stored by two charge injections in which the functions of the source and drain for the two source / drain regions are switched.

The operation of reading data from the N-channel type memory transistor is performed by a so-called reverse read method or forward read method.
In the reverse read method, a drain voltage is applied to the two source / drain regions 601 and 701 in a direction opposite to the direction of the voltage between the source and drain during charge injection, and a positive voltage is applied to the gate electrode G. On the other hand, in the forward read method, a drain voltage is applied to the two source / drain regions 601 and 701 in the same direction as the direction of the voltage between the source and drain during charge injection, and a positive voltage is applied to the gate electrode G.

Here, an example of a read operation by the reverse read method will be described.
First, 0 V is applied to the bit line BL on the side where charges are accumulated, and a voltage of 3 to 5 V, for example, is applied to the bit line BL on the opposite side. Then, a predetermined voltage (for example, about 3 to 5 [V]) is applied to the word line WL connected to the gate electrode G of the memory transistor of the memory cell from which data is to be read. At this time, generally, when charge is accumulated at the source side end of the laminated insulating film 901, since the threshold voltage is high, no current flows between the bit lines BL. Bit information corresponding to 1 ″ can be read. Further, when no charge is accumulated in the laminated insulating film 901, the threshold voltage is relatively low and a current flows between the bit lines BL. Therefore, bit information corresponding to a non-charge accumulation state, for example, logic “0” is displayed. Read out.

JP 2003-078051 A

In the nonvolatile semiconductor memory device, the bit line BL is commonly connected to each source and drain of the memory transistors arranged in the column direction of the nonvolatile semiconductor memory device. Therefore, in a predetermined transistor row for charge injection, a high voltage of, for example, about 3 to 5 V is provided between the source and drain of the memory transistor selected during the charge injection operation (between the first and second source / drain regions 601 and 701). When a voltage is applied, the voltage is also applied between the source and drain of a non-selected memory transistor that does not perform a write operation in the same column.
Therefore, when charge is stored in the charge storage means of the non-selected memory transistor, voltage stress is applied in such a direction that the charge is gradually extracted by the electric field applied between the source or drain and the gate. The

When the number of memory transistors in the column direction in which the sources and drains are electrically connected in common is N, this voltage stress is applied at most (N−1) times.
More specifically, the operation of sequentially selecting the N memory transistors to inject or not inject charge is repeated N times. At this time, a certain memory transistor is not selected at the time of (N-1) operations except for the case where the memory transistor is selected, but other memory transistors at all of the (N-1) times of non-selection. Assuming that charge injection is performed, the non-selected memory transistor is subjected to voltage stress in the direction of pulling out the accumulated charge only (N−1) times.
Therefore, when charge is accumulated, the memory transistor is subjected to a so-called disturbance in which the accumulated charge is extracted to the source or drain side, and in the worst case, the stored data is attenuated to such an extent that it cannot be read out. There is.

Due to the disturb, there is a high possibility that an error occurs in reading bit information, and therefore, the number of memory transistors that can be arranged in the row direction is limited. For this reason, there is a limit to the integration of the memory transistors constituting the nonvolatile semiconductor memory device.
SUMMARY OF THE INVENTION Problems to be solved by the present invention are a charge injection method for a nonvolatile semiconductor memory device that makes it difficult for a memory transistor to be disturbed and enables high integration of the memory transistor, and a nonvolatile semiconductor memory device having a structure suitable for the method. And to provide.

  In the non-volatile semiconductor memory device charge injection method according to the present invention, in the memory cell array, one of the source and the drain is electrically connected in common by the first bit line, and the other of the source and the drain is electrically connected by the second bit line. One memory transistor is selected from a transistor group consisting of a plurality of N memory transistors commonly connected to each other, and charges are injected into the discrete charge storage means in the gate insulating film of the selected memory transistor. A charge injection method of a nonvolatile semiconductor memory device for changing a data storage state of a transistor, wherein when charge injection is performed on the selected memory transistor, the first memory cell electrically connected to the selected memory transistor One voltage of the 1 bit line and the second bit line is made higher than the other voltage, and the selection When charge injection is not performed on the selected memory transistor, the first step of setting the first bit line and the second bit line to the same potential, and when charge injection is performed on the selected memory transistor A second step of applying a gate voltage for charge injection to a selected word line to which the gate of the selected memory transistor is connected when at least charge injection is performed. When executing the second step in a predetermined order N times while changing the memory transistor to be selected in the transistor group, approximately half of the transistor group (N / 2 or N / 2 is the most). When injecting charges into memory transistors of a close integer), in the first step, the voltage of the first bit line is set higher than the voltage of the second bit line. Comb, when performing the charge injection into the memory transistor of the remaining substantially half of the voltage of the first bit line in the first step lower than the voltage of the second bit line.

According to the above method, when the operation (first and second step operations) of performing or not performing charge injection to the transistor group including N memory transistors is repeated N times, the charge injection is performed as charge storage means. In the distribution, for example, in the case of the N channel type, the distribution is performed on a local portion on the bit line side to which a higher voltage is applied. When charge injection is performed on approximately half of the memory transistors, the voltage of the first bit line is set higher than the voltage of the second bit line in the first step, and when charge injection is performed on the remaining approximately half of the memory transistors. In the first step, the voltage of the first bit line is made lower than the voltage of the second bit line.
Therefore, when operating about half of the memory transistors with the voltage of the first bit line being higher than the voltage of the second bit line, the voltage stress in the direction that pulls out the accumulated charge to the remaining half of the memory transistors is alleviated. The Similarly, during the operation for the remaining approximately half of the memory transistors performed by setting the voltage of the second bit line higher than the voltage of the first bit line, the voltage stress of the other approximately half of the memory transistors is directed to extract the stored charge. Is alleviated.
Therefore, the number of times each memory transistor is disturbed is reduced to almost half.

  A nonvolatile semiconductor memory device according to the present invention includes a memory cell array, and a memory transistor in each cell of the memory cell array includes a channel formation region of a semiconductor substrate, a gate electrode, the gate electrode, and the channel formation region. A plurality of N memories formed between the gate insulating film including the charge storage means discretely formed and the semiconductor substrate on both sides of the channel formation region and arranged in one direction in the memory cell array; Two source / drain regions electrically connected independently from each other in a transistor group consisting of transistors and a part of the channel formation region, and the impurity concentration of the semiconductor in the channel formation region other than the region A high concentration channel region having a high impurity concentration, the high concentration channel region, In the transistor group, approximately half (N / 2 or an integer closest to N / 2) of memory transistors are formed in contact with one of the two source / drain regions, and in the remaining approximately half of the memory transistors, It is formed in contact with the other of the two source / drain regions.

  When the high-concentration channel region exists, the concentration of the lateral electric field in the channel increases, and the probability of generating high-energy charges in the vicinity thereof increases. Therefore, the present nonvolatile semiconductor memory device has a structure suitable for application of the charge injection method in which the direction of the voltage applied between the two source / drain regions is reversed between the above-mentioned approximately half and the remaining approximately half. .

According to the charge injection method for a nonvolatile semiconductor memory device of the present invention, it is possible to alleviate disturbance to the memory transistor in the nonvolatile semiconductor memory device. Therefore, the nonvolatile semiconductor memory device of the present invention can prevent erroneous reading even if the number of memory transistors arranged in the column direction is increased to increase the degree of integration. As a result, that is, by applying the present charge injection method, the memory transistor can be highly integrated.
According to the present invention, a nonvolatile semiconductor memory device having a structure suitable for the charge injection method can be provided. In addition, since this device can increase charge injection efficiency due to its structure, it can operate correctly even if it is miniaturized (highly integrated) and has a low voltage.

  Embodiments of the present invention will be described below with reference to the drawings.

The present invention can be widely applied to nonvolatile semiconductor memory devices in which charge storage means are discretized. As such a device, in addition to the MONOS type and the MNOS type, there is a so-called nanocrystal type in which, for example, conductive fine particles are discretely contained in the insulation, that is, insulated from each other. Thus, the charge accumulating means only needs to be discretized, and the material, shape, and formation method are not limited.
The present invention is applicable to both P-type and N-type channel conductivity types.
Further, in the cell array configuration, the present invention can be widely applied if bit lines are provided in pairs for each column of transistors and each bit line is electrically independent. As a typical cell array configuration, there is a so-called NOR type in which a so-called source line and a bit line are separated, a so-called AND type. Here, the AND type means that, for example, each of the source line and the bit line is hierarchized by a lower impurity diffusion layer or the like and an upper wiring layer, and the connection and non-connection of both can be arbitrarily controlled via a selection transistor. An array configuration. The present invention can be applied to both the NOR type and the AND type. Although the details will be described later, in the present invention, the roles of the source and the drain in the two source / drain regions are not the same in the transistor array. Therefore, neither the source region nor the drain region is used. This is called a region. Further, the names of the first bit line and the second bit line are used without using the names of the source line and the bit line.

As is generally well known in the field of nonvolatile memory, data writing and erasing depends on the channel conductivity type, the type of charge to be injected (electron or hole), and the memory cell array configuration. Definition is different. Also, the injected charge at the time of writing may be either an electron or a hole.
When the electron injection is defined as writing, an erasing operation is an operation of drawing out electrons or an operation of injecting holes having a reverse polarity to cancel the charge amount of the accumulated electrons. Conversely, when the hole injection is defined as writing, the erasing operation is an operation of extracting a hole or an operation of injecting a reverse polarity electron to cancel the accumulated charge amount of the hole.
In some cases, “1” data write and “0” data write are defined. In this case, the substantial definition of the write state and the erase state is determined depending on whether the initial state is “1” or “0”.

The writing unit may be a word line unit or a finer unit, for example, an 8-bit unit corresponding to one word. In addition, the erase unit may be erased in batches, erased in block units, or in arbitrary units such as word line units or word units.
Further, the state in which the threshold voltage of the memory transistor is relatively low is set as the erased state, and the threshold voltage is increased only for the predetermined memory transistor. There is only a way to lower the threshold voltage.

The charge injection method according to the present invention focuses on a transistor group (for example, N transistors arranged in the column direction) in which two source / drain regions are connected to each other by electrically independent bit lines. Therefore, it does not matter whether the other configuration of the cell array, that is, whether the bit line is hierarchized and has a selection transistor, or the like. Further, the unit of writing and erasing and whether the initial state (erasing state) is set to a state where the threshold voltage is higher or lower are arbitrary.
Hereinafter, an embodiment of the present invention will be described by taking a nonvolatile memory device having a NOR type cell array composed of N channel type MONOS transistors and writing electron injection as an example. In the case of the P-channel type, the following explanation can be applied by analogy by appropriately reversing the conductivity type of the impurity region and the polarity of the voltage.

FIG. 1 is a circuit diagram of a nonvolatile semiconductor memory device 1 according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the memory transistor.
A nonvolatile semiconductor memory device 1 shown in FIG. 1 has memory transistors M11 to M44 arranged in a matrix.
The number of rows and columns of the memory transistor array is arbitrary. In FIG. 1, memory transistors M11 to M44 of 4 rows × 4 columns are shown for simplification.
In the following, the memory transistors M11 to M44 are indicated by the common code 2.

  The array of memory transistors 2 constituting the matrix has word lines WLi (i = 1, 2, 3, 4) that commonly connect the gates to each row in units of the memory transistors 2 arranged in the row direction. For each column of memory transistors 2 arranged in the column direction, a first bit line BLj (j = 1, 3, 5, 7) that commonly connects one of the two source / drain regions of each memory transistor, , And a second bit line BLk (k = 2, 4, 6, 8) that commonly connects the other. The row control circuit 3 is connected to the word line WLi, and the column control circuit 4 is connected to the bit line pair (first bit line BLj, second bit line BLk).

  A MONOS type memory transistor for realizing the non-volatility of the non-volatile semiconductor memory device 1 shown in FIG. 1 includes a gate insulating film (for example, ONO (Oxide-Nitride-Oxide) as a laminated insulating film including charge storage means (charge trap). ) Film). Information can be stored by injecting and accumulating charges in charge traps formed in the bulk of the nitride film in the gate insulating film and at the interface between the nitride film and the oxide film.

Specifically, as shown in FIG. 2, the memory transistor 2 includes a channel formation region 8 in which a channel is formed, and two source / drain regions, that is, a first source / drain region 6 and a second source / drain region. 7. These regions are impurity regions in the semiconductor substrate 5. In the N-channel type memory transistor 2, the N-type first source / drain region 6 and the second source / drain region so as to sandwich the P-type channel formation region 8. 7 is formed. The first source / drain region 6 and the second source / drain region 7 are determined to be a source or a drain depending on the conductivity type (P type or N type) of the channel and the direction of voltage application.
In the present invention, the term “semiconductor substrate” refers to a semiconductor substrate in a narrow sense cut out from silicon or other semiconductor wafers, an impurity region in which a channel such as a well in the semiconductor substrate is formed, a substrate of a semiconductor or other material. A so-called SOI layer formed on the surface via an insulating layer is included.

Of the channel formation region 8, the impurity concentration of the semiconductor in the region in contact with the second source / drain region 7 is higher than the impurity concentration of the semiconductor in the channel formation region other than that region.
This region is referred to as a high concentration channel region 10. The high-concentration channel region 10 has a role of increasing the concentration of the electric field in the channel direction in the adjacent channel formation region 8 portion.
In the memory transistor 2 in this figure, the high concentration channel region 10 is formed in a region in contact with the second source / drain region 7. However, as will be described later, there is also a memory transistor formed in a region in contact with the first source / drain region 6.

A laminated insulating film 9 is formed on the channel forming region 8, and a gate electrode G is formed on the laminated insulating film 9. The gate insulating film 9 includes three layers of insulating films, that is, a silicon oxide film 9a, a silicon nitride film 9b, and a silicon oxide film 9c. Therefore, the gate insulating film 9 has an ONO structure.
The silicon oxide film 9a may be a laminated film of a silicon oxide film and a silicon oxynitride film, and the silicon nitride film 9b may be a silicon oxynitride film or a metal oxide film.
On the side surfaces of the gate insulating film 9 and the gate electrode G, a sidewall insulating layer 11 made of, for example, a silicon oxide insulating film is formed.

The first and second source / drain regions 6 and 7 may have an extension structure in which a low concentration impurity region extends from the high concentration impurity region toward the center of the channel. In this case, the high concentration channel region 10 is formed between the low concentration extension portion and the channel formation region 8.
The word line WLi may be formed from the gate electrode G, or the gate electrode G may be connected to the upper conductive layer (word line WLi). When the gate electrode G is disposed relatively long, it is desirable to reduce the resistance by a method such as forming the gate electrode G into two layers of polysilicon and refractory metal silicide.
Although not shown in FIG. 2, each of the first and second source / drain regions 6 and 7 is electrically connected to the first bit line BLj and the second bit line BLk made of a wiring layer through contacts. It is connected to the.

In the present embodiment, the number of memory transistors in which the high-concentration channel region 10 is arranged on the first source / drain region 6 side in the entire memory cell array, in particular, the N transistor groups arranged in the column direction, and the high-concentration channel The number of memory transistors arranged in the region 10 on the second source / drain region 7 side is made substantially equal. The reason is to make the number of times of disturbance uniform in any memory transistor.
In addition, the specific arrangement is arbitrary except for this number of restrictions.

  Hereinafter, on the premise of the above configuration, each operation of data writing (electron injection), erasing, and reading for one memory transistor shown in FIG. 2 will be described. Next, the bit line voltage application and gate line voltage application sequences in two specific array configurations will be described.

<Write operation>
The row control circuit 3 and the column control circuit 4 in FIG. 1 decode the input address signal, and as a result, select the memory transistor 2 in FIG. 2 as a write target.
The column control circuit 4 holds the first source / drain region 6 (first bit line BLj) in which the high concentration channel region 10 is not formed at a relatively low voltage, for example, the ground voltage 0 [V]. A relatively high voltage, for example, 3 to 5 [V] is applied to the second source / drain region 7 (second bit line BLk) in which the concentration channel region 10 is formed (first step of the present invention). At this time, the semiconductor substrate 5 may be floating, but is preferably fixed at a predetermined potential such as 0 [V].
Further, a predetermined positive voltage, for example, 3 to 5 [V] is supplied from the row control circuit 3 of FIG. 1 to the gate electrode G (word line WLi) (second step of the present invention).
Although these voltage application procedures are arbitrary, if the load on the bit line side including the so-called impurity diffusion layer is larger than the load on the word line, it takes time to stabilize the potential of the bit line. It is desirable to set and then apply the word line voltage.

Under the above voltage application condition, an N-type inversion layer channel is formed on the surface portion of the P-type channel formation region 8, and electrons are supplied to the channel from the first source / drain region 6. The supplied electrons travel while being accelerated toward the drain (second source / drain region 7) by a lateral electric field in the channel. Then, the electric field is concentrated more rapidly in the electric field concentration region in the depletion layer near the high-concentration channel region 10, and a part becomes high-energy charges (hot electrons). Therefore, some hot electrons are injected into the laminated insulating film 9 beyond the energy barrier of the silicon oxide film 9a. Then, it is mainly captured and held in a charge trap in the bulk of the silicon nitride film 9b and in the vicinity of the boundary between the silicon nitride film 9b and the silicon oxide film 9c. As a result, electrons are stored in the laminated insulating film 9, but the electron-stored region is limited to the local portion of the laminated insulating film 9 near the drain corresponding to the hot electron generation region. . This electron injection method is called a channel hot electron (CHE) injection method.
Since the electrons injected into the charge traps in the laminated insulating film 9 have extremely low conductivity, the distribution of the electrons hardly changes even after the voltage application is released. For this reason, the storage state of, for example, “1” data is maintained as the nonvolatile memory state even after the voltage application is released.

Not performing charge injection into the memory transistor 2 in FIG. 2 is referred to as “0” data writing or maintaining an erased state (non-writing). For this purpose, one or both of the bit line voltage and the word line voltage is not applied during the write operation. The row control circuit 3 and the column control circuit 4 in FIG. 1 do not apply these voltages corresponding to the case where the memory transistor 2 should be unselected as a result of decoding the input address signal. Take control.
If no bit line voltage is applied, no lateral electric field is applied when forming the channel, so that electron injection is not performed. If no word line voltage is applied, the inversion layer is not induced even when the lateral electric field is applied, and thus a channel is not formed. Therefore, in either case, electron injection is not performed.

<Erase operation>
In FIG. 2, the intentional reduction of the amount of electrons injected into the drain (second source / drain region 7) side portion of the laminated insulating film 9 is called erasing.
In the erasing operation, electrons are extracted from the drain (second source / drain region 7) side, gate (gate electrode G) side, or the entire channel surface by FN tunneling, or charges (holes) having a reverse polarity are locally extracted to the drain side. Can be performed by injecting from.
The uppermost silicon oxide film 9c of the laminated insulating film 9 serves to prevent holes from being injected from the gate electrode G during an operation such as writing, so that the film thickness cannot be made too thin. For this reason, when extracting electrons, it is more desirable to extract electrons from the drain side or the entire channel surface.
On the other hand, in the erasing method in which holes are injected into the local part of the laminated insulating film 9 from the drain side, band-to-band tunneling is used. Hereinafter, the erasing operation using this interband tunneling will be described.

The row control circuit 3 and the column control circuit 4 in FIG. 1 decode the input address signal, and as a result, select the memory transistor 2 in FIG. 2 as an erasure target. As described above, the unit for batch erasing in the memory cell array may be the entire cell array, each block constituting the array, each word line, or a smaller unit. Here, it is assumed that the memory transistor 2 of FIG. 2 is included in any one of the erase units.
In the voltage setting at the time of erasing, the gate electrode G is set to the low voltage side, the second source / drain region 7 is set to the high voltage side, and a predetermined voltage sufficient to cause the band-to-band tunneling is applied. For example, the gate electrode G is grounded, and a predetermined positive voltage (several [V] to several tens [V]) is applied to the second source / drain region 7. Alternatively, the second source / drain region 7 is grounded and the negative predetermined voltage is applied to the gate electrode G. Alternatively, a positive voltage and a negative voltage whose absolute value is the predetermined voltage are generated by a power supply circuit (not shown), a positive voltage is applied to the second source / drain region 7, and a negative voltage is applied to the gate electrode G. To do.

  Under this voltage condition, electrons accumulate on the surface portion of the second source / drain region 7, more specifically, on the surface portion of the overlap region of the gate electrode G and the second source / drain region 7, which are not shown in FIG. A layer (accumulation layer) is formed, where the bending of the energy band becomes steep, and an interband tunneling current flows between the valence band and the conduction band. Electrons and hole pairs are generated due to the band-to-band tunneling current, of which holes become hot holes and are attracted to the gate electrode G having a lower voltage. Near the storage area). As a result, the amount of charge due to stored electrons is sufficiently reduced and data is erased.

<Read operation>
The operation of reading data from the memory transistor 2 shown in FIG. 2 is performed by a so-called reverse read method or forward read method.
In the reverse read method, a drain voltage is applied to the first and second source / drain regions 6 and 7 in the direction opposite to the direction of the voltage between the source and drain during charge injection, and a positive voltage is applied to the gate electrode G. On the other hand, in the forward read method, a drain voltage is applied to the first and second source / drain regions 6 and 7 in the same direction as the voltage between the source and drain during charge injection, and a positive voltage is applied to the gate electrode G. To do.

Here, as an example, a read operation by the reverse read method will be described.
The read operation is performed, for example, in units of word lines or in units of memory transistors connected to the word lines and storing predetermined bits (e.g., 8 bits). Here, the row control circuit 3 and the column control circuit 4 in FIG. 1 decode the input address signal, and as a result, select the memory transistor 2 in FIG. 2 as a read target.
In the voltage setting at the time of reading by the reverse read method, with respect to the memory transistor 2 in which the bit information “1” or “0” is written, the first source / drain region 6 side is the drain, and the second source / drain region 7 is. The side is the source. That is, with the second source / drain region 7 grounded, for example, a positive voltage, for example, a drain voltage of about 3-5 [V] is applied to the first source / drain region 6. In addition, a gate voltage that is located between the threshold voltage distribution of “1” data and the threshold voltage distribution of “0” data and has a sufficient read margin from both distributions is applied to the gate electrode G. To do. The gate voltage is supplied from the row control circuit 3 in FIG. 1, and the drain voltage is supplied from the column control circuit 4.
With this voltage setting, when the memory transistor 2 is writing “1” data, the memory transistor 2 is not turned on or sufficient current does not flow through the channel. On the other hand, when the memory transistor 2 is writing “0” data, the memory transistor 2 is turned on and a sufficient channel current flows.
The stored data can be read by detecting information corresponding to whether the channel current sufficiently flows or does not flow with a sense amplifier (not shown). Specifically, one of the first bit line BLj connected to the first source / drain region 6 and the second bit line BLk connected to the second source / drain region 7 is set in a floating state after voltage setting. The potential fluctuation is detected. As a detection method, a method in which a potential difference between both bit lines is detected and amplified by a sense amplifier, a method in which the sense amplifier compares a floating bit line potential change with a predetermined reference voltage, and a comparison result is amplified. There is.
In any case, the logic “1” or “0” of the stored data in the memory transistor 2 can be determined depending on whether the sense amplifier output is at the “H” level or the “L” level.

The basic operation has been described above with a focus on the single memory transistor 2.
However, as shown in FIG. 1, since the memory transistors M11 to M44 are connected to each other by a word line or a bit line, an influence that causes erroneous reading to other memory transistors that are not to be written particularly during writing (disturbance). May give.
Hereinafter, after describing the disturb at the time of writing, a configuration for relaxing the voltage and a voltage application sequence will be described.

<Disturb when writing>
As described above, one or both of the bit line voltage and the word line voltage is not applied to the other non-selected memory transistors during the write operation to the selected memory transistor.
However, bit lines and word lines are commonly connected as shown in FIG. For this reason, the stack is formed on the gate electrode G side when only the word line voltage is applied, and on the drain (second source / drain region 7 in this example) side when only the bit line voltage is applied. A voltage stress that pulls out stored electrons in the insulating film 9 is applied. In general, the voltage stress is applied so that the stored electrons are extracted to the gate electrode G side by this voltage stress, and the memory disturbance caused by the applied voltage is “gate disturb”, and the voltage stress is applied so that the stored electrons are extracted to the drain side. And the memory disturbance resulting from this is called “drain disturb”.
Since the time for applying a single voltage stress is short, even when the electron is not actually pulled out erroneously, the application of the voltage stress is repeated. Therefore, reducing the number of times voltage stress is applied or the accumulated time of voltage application is important for disturb mitigation.

  Therefore, in the present embodiment, in the transistor group composed of N memory transistors arranged in the column direction, charge injection is performed on approximately half of the memory transistors (N / 2 or an integer closest to N / 2), and the rest. Control is performed to change the magnitude relationship of the voltage or the direction of voltage application in the bit line pair (first and second bit lines) when charge injection is performed in approximately half of the memory transistors. Accordingly, an object of the present embodiment is to alleviate drain disturbance.

Next, a more specific voltage application sequence (charge injection method) for achieving this object will be described.
In the charge injection method of the present invention, basically, it is only necessary that the bit line pair is connected to the N memory transistors arranged in the column direction so that a voltage can be applied independently. Therefore, the high-concentration channel region 10 can be omitted in the cross-sectional view of FIG. 2, and in this case, the direction of application of the bit line voltage is not limited by the device structure.
However, when the high concentration channel region 10 is formed, the effect of providing the high concentration channel region 10 cannot be obtained unless the side where the high concentration channel region 10 is formed is used as a drain. Therefore, the bit line pressure application sequence differs depending on which side of the first and second source / drain regions 6 and 7 the high-concentration channel region 10 is formed and the arrangement in the cell array.

  Therefore, in the present embodiment, the high concentration channel region 10 is alternately provided on the first source / drain region 6 side and the second source / drain region 7 side (first example), and the high concentration channel region 10 is provided. In an example (second embodiment) in which the memory transistors arranged on the first source / drain region 6 side are continuously arranged and the memory transistors in which the high concentration channel region 10 is formed on the second source / drain region 7 side are arranged continuously. The voltage application sequence suitable for each will be described.

<First embodiment>
FIG. 3 is a circuit diagram showing a transistor group (column of a cell array) including N (= 4) memory transistors extracted from FIG.
In the four memory transistors M1 to M4 shown in FIG. 3, the side where the high concentration channel region 10 of FIG. 2 is formed is indicated by a point “H”. These four memory transistors M1 to M4 have their first source / drain regions 6 (FIG. 2) connected to the first bit line BLj (j = 1, 3, 5, 7) and their second source / drain regions. The region 7 (FIG. 2) is connected to the second bit line BLk (k = 2, 4, 6, 8). In the odd-numbered memory transistors M1 and M3, the high-concentration channel region 10 is formed on the second bit line BLk side. In the even-numbered memory transistors M2 and M4, the high-concentration channel region 10 is the first bit. It is formed on the line BLj side.

FIG. 4 is a timing chart showing a bit line voltage application sequence at the time of writing in which electrons are injected into all the memory transistors in the first embodiment. In FIG. 4, the horizontal axis indicates time, and the vertical axis indicates the voltage value VBL [V] of the bit line voltage supplied to the first bit line BLj and the second bit line BLk.
The operation starts at the time t1 on the horizontal axis, the time t1 to t2 is the writing period of the memory transistor M1, the time t2 to t3 is the writing period of the memory transistor M2, the time t3 to t4 is the writing period of the memory transistor M3, and the time t4 to t5 represent the writing period of the memory transistor M4.

  The voltage setting in each writing period is as described in the section <writing operation> for the memory transistor 2 of FIG.

That is, the column control circuit 4 in FIG. 1 selects a column including the first bit line BLj and the second bit line BLk. More specifically, when writing to the memory transistor M11 in FIG. 1, the bit line BL1 (j = 1) and the bit line BL2 (k = 2) are selected, and when writing to the memory transistor M12, the bit line BL3 (j = 3). And bit line BL4 (k = 4) are selected, bit line BL5 (j = 5) and bit line BL6 (k = 6) are selected when writing to the memory transistor M13, and bit line is selected when writing to the memory transistor M14. BL7 (j = 7) and bit line BL8 (k = 8) are selected. Then, the column control circuit 4 applies a bit line voltage to the selected bit line pair BLj, BLk. In writing to the first memory transistor M1 (M11, M12, M13, or M14) in the odd-numbered row, the first bit line BLj is set to the high level voltage VH (for example, 3-5 [ V]) and the second bit line BLk is set to a low level voltage (for example, the ground voltage GND) (first step of the present invention).
Further, the row control circuit 3 of FIG. 1 selects a row including the memory transistor M1 to be written first in the odd-numbered row, and a predetermined gate voltage (for example, the word line WL1 (i = 1)) is selected in the selected row. 3 to 5 [V]) is applied (second step of the present invention).
As a result, electrons are injected and stored in the local region on the drain side of the laminated insulating film 9 in which the high concentration channel region 10 is formed by the channel hot electron (CHE) injection method described in the section of <Write operation>.

When the time t2 in FIG. 4 is reached, the column control circuit 4 in FIG. 1 applies a bit line voltage to write the first memory transistor M2 (M21, M22, M23 or M24 in FIG. 1) in the next even row. Switch the direction of. Specifically, the high level voltage VH and the low level voltage (ground voltage GND) are inverted in the bit line pair BLj, BLk (time t2 to t3).
At time t2 in FIG. 4, the row control circuit 3 in FIG. 1 selects the second row (specifically WL2 (i = 2)), and the gate voltage is applied to the selected word line WL2. Is applied. As a result, electrons are injected and stored in the first memory transistor M2 in the even-numbered row by the CHE injection method. At this time, as indicated by a point “H” in FIG. 3, since the high concentration channel region 10 is formed on the first bit line BLj functioning as a drain, the high concentration channel region 10 plays its role, Injection efficiency is increased.

  The operation from the time t1 to the time t3 is defined as one cycle, and the second memory transistor M3 in the next odd row and the second (fourth in the whole) memory transistor M4 in the even row However, the writing is executed in the same manner. As shown in FIG. 3, the high concentration channel region 10 indicated by the point “H” is alternately formed with respect to the bit line pair BLj, BLk. 10 plays a role and improves the injection efficiency.

  If there are more rows, the above cycle operation is repeated as many times as necessary.

For convenience of explanation, FIG. 4 shows a case where electrons are injected into all the memory transistors M1 to M4. However, when writing “0” data (maintaining an erased state), the high level voltage VH is not applied. Both bit line pairs BLj and BLk are held at a low level voltage, that is, the ground voltage GND. Thereby, writing of bit data of “1” and “0” can be arbitrarily executed.
This bit information is input from the outside as write data, and is set to the bit line pair BLj, BLk from a write circuit not shown in FIG. In this case, the column control circuit 4 simply controls the bit line pair BLj, BLk of the selected column to be set in accordance with the write data and floats after setting the voltage. When BLj and BLk exist (for example, when writing in units of 8 bits), control is performed to fix the unselected bit line pair to the potential, for example, with the ground voltage GND. Note that a write circuit may be included in the column control circuit 4 of FIG.

<Second embodiment>
FIG. 5 is a circuit diagram of a focused transistor group in the second embodiment. This circuit diagram corresponds to FIG. 3 of the first embodiment.
In the second embodiment, the formation position of the high-concentration channel region 10 (FIG. 2) indicated by the point “H” is approximately half of the memory in which the transistor group is continuously arranged in the memory transistor arrangement direction (column direction). The transistor is different from the remaining half of the memory transistors that are continuously arranged. That is, in FIG. 5, in the memory transistors M1 and M2, the high concentration channel region 10 indicated by the point “H” is formed on the second bit line BLk side, and in the memory transistors M3 and M4, the high concentration channel region 10 is the first. It is formed on the bit line BLj side.
The device structure of the second embodiment is the same as that of the first embodiment except for the arrangement of the high concentration channel region 10.

FIG. 6 shows a timing chart of the write operation of the second embodiment.
This timing chart differs from the timing chart of the first embodiment (FIG. 4) in that the high level voltage is applied to the bit line pair BLj, BLk in each of the periods t2 to t3 and the periods t3 to t4 from the case of FIG. In other words, VH and the low level voltage (ground voltage GND) are inverted. This corresponds to the fact that the formation position of the high concentration channel region 10 in FIG. 5 is changed from that in FIG. 3, and the side where the high concentration channel region 10 is formed is used as the drain. Therefore, the basic sequence itself is the same as that of the first embodiment described above except that the voltages of the bit line pairs BLj and BLk are exchanged in each of the times t2 to t4 (t2 to t3, t3 to t4). It is.

  In the case of “0” data write, the bit line pair BLj, BLk is held at the same voltage (ground voltage GND) without applying the high level voltage VH, as in the first embodiment.

  In the first embodiment, when “0” data writing continues, the voltages of BLj and BLk may be kept at the ground voltage GND. However, when “1” data writing continues, the bit line changes every time the writing target changes. It is necessary to invert the voltage of the pair BLj and BLk. Also, when “0” data is written after “1” data is written, and conversely, when “1” data is written after “0” data is written, one of the bit line pairs BLj and BLk is set to the high level voltage VH. It is necessary to change the voltage between the ground voltage GND and the ground voltage GND. Therefore, when viewed as a whole, the number of charge / discharge cycles of the bit line tends to increase.

In the second embodiment, the bit line pair BLj, BLk is kept at the ground voltage GND as long as “0” data writing continues, and when “0” data writing is performed after “1” data writing, When writing “1” data after writing “0” data, basically, it is necessary to change the voltage of one of the bit line pair BLj, BLk between the high level voltage VH and the ground voltage GND. Common to the first embodiment.
However, in the second embodiment, even when “1” data writing continues, as long as the high-concentration channel region 10 is formed on the same side, it is not necessary to invert the voltages of the bit line pair BLj, BLk. In this respect, the first and second embodiments are different.
Therefore, the second embodiment has a higher probability of reducing the number of charge / discharge cycles of the bit line than the first embodiment. Decreasing the number of times of charging / discharging the bit line is preferable in that the time required for stabilizing the potential of the bit line can be saved and the writing time can be reduced.

Although two embodiments have been described above, the present invention is not limited to these two embodiments.
That is, the high-concentration channel regions 10 may be formed at the same location (on one side of the bit line pair BLj, BLk) every two, three, or even four or more. In addition, a high-concentration channel region 10 is formed on one side of the pair of bit lines BLj and BLk in about half of the N memory transistors existing in the same column, and a high-concentration channel region 10 is formed on the other side in the remaining half. If it is formed, other regular arrangements, and further arrangements without regularity are possible.

In erasing and reading, it is determined which voltage is applied to the bit line pair BLj, BLk depending on which side of the electron storage area the bit line pair BLj, BLk is. Since this point is clear from the description of the <erase operation> and <read operation> already described above, description thereof is omitted here.
At this time, the point that the second embodiment is more advantageous than the first embodiment according to the difference in the number of times of charging / discharging the bit line is the same for erasing and reading.

<Manufacturing method>
Finally, a method for manufacturing a memory transistor used in the nonvolatile semiconductor memory of the present invention will be described.
7A to 7B are cross-sectional views of the memory transistor 2 that is being manufactured.

First, a semiconductor substrate 5 made of silicon is prepared, and an element isolation insulating layer (not shown), a well, and ion implantation for adjusting a threshold voltage are performed as necessary. Then, three layers of insulating films 9 a, 9 b, 9 c to be the gate insulating film 9 shown in FIG. 7A are formed on the semiconductor substrate 5. First, the semiconductor substrate 5 is oxidized by a thermal oxidation method to form a silicon oxide film 9a of about 2 to 5 [nm], for example. A silicon nitride film 9b is deposited on the silicon oxide film 9a by 5 to 10 [nm], for example, by LP-CVD. This CVD uses, for example, a gas obtained by mixing dichlorosilane (DCS) and ammonia. Then, the surface of the silicon nitride film 9b is thermally oxidized to form a silicon oxide film 9c of 4 to 5 [nm], for example.
Next, a gate conductive film made of, for example, a polysilicon single-layer film or a multilayer film of polysilicon and metal silicide is formed on the three-layered insulating films 9a, 9b, and 9c. Thereafter, the gate conductive film and the underlying three insulating films 9a, 9b, and 9c are continuously processed with a predetermined gate electrode pattern. Thus, a stacked body of the stacked insulating film 9 and the gate electrode G is formed as shown in FIG.

In the step corresponding to FIG. 7B, P-type impurity ion implantation is performed for forming the high-concentration channel region 10 by oblique ion implantation using the formed multilayer insulating film 9 and gate electrode G as a self-alignment mask. I do.
At this time, it is necessary to form the high concentration channel region 10 on one side of the width of the stacked body in the channel direction. For this reason, it is necessary to cover the other side with a protective layer so that ions are not implanted by a resist or other material. This is because, as in the first embodiment and the second embodiment described above, when viewed from the whole memory cell array, the memory transistor in which the high concentration channel region 10 is formed in one of the channel directions of the stacked body and the high concentration in the other. If a method for forming the high concentration channel region 10 by oblique ion implantation is used in order to mix the memory transistor in which the channel region 10 is formed, the silicon wafer is rotated by rotation, revolution, or both, and obliquely tilted from all directions. This is because it is necessary to perform ion implantation.
In other words, when the high-concentration channel region 10 is formed only in one of the channel directions of the stacked body in the entire memory cell array, a method of performing oblique ion implantation with the wafer fixed can be adopted, in which case ion implantation is prevented. The protective layer 12 is not always necessary. However, when the formation positions of the high concentration channel region 10 are mixed as in the present embodiment, the formation of the protective layer 12 is essential.

Next, the protective layer 12 is removed, and if necessary, the N-type impurity ion implantation is substantially perpendicular to the substrate or the high concentration in order to form extension regions of the first and second source / drain regions 6 and 7. The oblique ion implantation is performed at an angle sufficiently shallower than the oblique ion implantation at the time of forming the channel region 10.
The order of the ion implantation for forming the extension region and the oblique ion implantation for forming the high concentration channel region 10 may be reversed.

Next, for example, a silicon oxide insulating film is deposited thickly so as to completely cover the stacked body, and this insulating film is etched (etched back) on the entire surface by using anisotropic etching. As a result, as shown in FIG. 7C, sidewall insulating layers 11 are formed on the side surfaces of the stacked body.
Subsequently, N-type impurities are ion-implanted at a relatively high concentration using the sidewall insulating layer 11 and the gate electrode G as a self-alignment mask.
Thereafter, when activation annealing is performed, the first and second source / drain regions 6 and 7 are formed in the semiconductor substrate 5 as shown in FIG.

  Thereafter, the memory transistor 2 is completed through deposition of an interlayer insulating film, contact opening, and formation of bit line pairs BLj and BLk.

According to the charge injection method of the present embodiment, in N memory transistors arranged in one direction (for example, the column direction) of the memory cell array, the number of times that drain disturbance is received when each memory transistor is not selected ( (Accumulated time) is almost halved, and erroneous reading of the memory transistor can be effectively prevented. This is more effective as the number N of memory transistors connected to the bit line pair increases with the future high integration.
In addition, with the reduction in voltage, miniaturization, and high-speed operation in the future, it is necessary to perform data recording of “1” and “0” with a smaller number of charges.
From the above, the disturb mitigation of the present embodiment is a technology that will greatly contribute to the improvement of the commercial value and performance of the nonvolatile memory device in the future.

  In addition, the device structure of this embodiment is advantageous in that the injection efficiency by the high-concentration channel region is improved in conformity with the charge injection method. Therefore, the combination of the device structure relating to the arrangement of the high-concentration channel region 10 and the charge injection method is a great solution for further higher integration, lower voltage, miniaturization, and higher speed operation. provide.

1 is a schematic configuration diagram of a nonvolatile semiconductor memory device according to an embodiment. It is sectional drawing of the MONOS type memory transistor of embodiment. 2 is an equivalent circuit diagram of a part of a cell array composed of memory transistors having the structure of the first embodiment. FIG. It is a timing chart which shows the bit line voltage application sequence of 1st Example. It is an equivalent circuit diagram of a part of a cell array composed of memory transistors having the structure of the second embodiment. It is a timing chart which shows the bit line voltage application sequence of 2nd Example. (A)-(C) are sectional drawings in the middle of the manufacture about the memory transistor of an embodiment. It is a schematic block diagram of a non-volatile semiconductor memory device. It is sectional drawing of a MONOS type | mold memory transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Nonvolatile semiconductor memory device, 2 ... Memory transistor 3 ... Row control circuit decoder, 4 ... Column control circuit, 5 ... Semiconductor substrate, 6 ... 1st source / drain region, 7 ... 2nd source / drain region, 8 ... Channel forming region, 9 ... charge storage means, 10 ... high concentration channel region, 11 ... side wall insulating layer, M11 to M44, M1 to M4 ... memory transistor, BLj ... first bit line, BLk ... second bit line, WLi ... Word line

Claims (8)

Transistor comprising a plurality of N memory transistors in which one of the source and drain is electrically connected in common by the first bit line and the other of the source and drain is electrically connected in common by the second bit line in the memory cell array The charge of the nonvolatile semiconductor memory device that selects one memory transistor from the group and injects the charge into the discrete charge storage means in the gate insulating film of the selected memory transistor to change the data storage state of the transistor An injection method,
When charge injection is performed on the selected memory transistor, one voltage of the first bit line and the second bit line electrically connected to the selected memory transistor is set higher than the other voltage, A first step of bringing the first bit line and the second bit line to the same potential when charge injection is not performed on the selected memory transistor;
A gate for charge injection is connected to a selected word line to which a gate of the selected memory transistor is connected when at least charge injection is performed between the case where charge is injected into the selected memory transistor and the case where charge is not performed. A second step of applying a voltage;
When executing the first and second steps in a predetermined order N times while changing the memory transistor selected in the transistor group, approximately half (N / 2 or N / 2 in the transistor group). In the first step, the voltage of the first bit line is set higher than the voltage of the second bit line, and the remaining half of the memory transistors are used. A method for injecting charge into a nonvolatile semiconductor memory device, wherein charge injection is performed by setting the voltage of the first bit line to be lower than the voltage of the second bit line in the first step. The method of claim 1, wherein the substantially half of the memory transistors are odd-numbered or even-numbered memory transistors in a memory transistor array of the transistor group. The approximately half of the memory transistors are memory transistors arranged continuously on one side of the memory transistor array of the transistor group, and the remaining approximately half of the memory transistors are continuous on the other side of the memory transistor array of the transistor group. The charge injection method for a nonvolatile semiconductor memory device according to claim 1, wherein the memory transistor is an arranged memory transistor. The memory transistor has a channel formation region sandwiched between two source / drain regions functioning as the source or the drain and in which a channel of the memory transistor is formed,
The channel formation region of the memory transistor has a high-concentration channel region having a semiconductor impurity concentration higher than that of other channel formation regions other than the region, in contact with one of the two source / drain regions. Have
The high-concentration channel region has a source / drain region side to which the first bit line is connected and a source / drain region side to which the second bit line is connected in the memory transistor arrangement direction in the transistor group. The charge injection method for a nonvolatile semiconductor memory device according to claim 1, wherein the charge injection method is alternately formed. The memory transistor has a channel formation region sandwiched between two source / drain regions functioning as the source or the drain and in which a channel of the memory transistor is formed,
The channel formation region of the memory transistor has a high-concentration channel region having a semiconductor impurity concentration higher than that of other channel formation regions other than the region, in contact with one of the two source / drain regions. Have
In the substantially half of the memory transistors continuously arranged on one side in the memory transistor array direction in the transistor group, the high-concentration channel region is formed on the source / drain region side to which the first bit line is connected. In the remaining approximately half of the remaining memory transistors arranged continuously on the other side in the memory transistor arrangement direction, the high-concentration channel region is formed on the source / drain region side to which the second bit line is connected. The charge injection method of the non-volatile semiconductor memory device according to claim 1 or 3. A memory cell array,
Memory transistors in each cell of the memory cell array are:
A channel formation region of a semiconductor substrate;
A gate electrode;
A gate insulating film formed between the gate electrode and the channel formation region and including discretized charge storage means;
Two transistors that are formed on the semiconductor substrate on both sides of the channel formation region and are electrically connected independently in a transistor group consisting of a plurality of N memory transistors arranged in one direction in the memory cell array. Source / drain regions;
A high-concentration channel region that is a partial region of the channel formation region and has an impurity concentration higher than that of a semiconductor in a channel formation region other than the region;
In the transistor group, the high-concentration channel region is formed in contact with one of the two source / drain regions in approximately half of the memory transistors (N / 2 or an integer closest to N / 2), and the remaining approximately In a half of the memory transistors, a non-volatile semiconductor memory device is formed in contact with the other of the two source / drain regions. The nonvolatile semiconductor memory device according to claim 6, wherein the high-concentration channel region is alternately formed on one side and the other side of the two source / drain regions in the memory transistor arrangement direction of the transistor group. In the transistor group, the high-concentration channel region is formed in contact with one of the two source / drain regions in the substantially half of the memory transistors on one side in the memory transistor arrangement direction, and on the other side in the memory transistor arrangement direction. The nonvolatile semiconductor memory device according to claim 6, wherein the remaining approximately half of the memory transistors are formed in contact with the other of the two source / drain regions.

Images