JP2007227834A - Semiconductor device, and method for manufacturing same - Google Patents
Semiconductor device, and method for manufacturing same Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 155
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 36
- 239000010703 silicon Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000000470 constituent Substances 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims description 71
- 239000011810 insulating material Substances 0.000 claims description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 35
- 238000005498 polishing Methods 0.000 claims description 29
- 239000011888 foil Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000012779 reinforcing material Substances 0.000 claims description 6
- 238000007517 polishing process Methods 0.000 claims description 2
- 239000002585 base Substances 0.000 description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 17
- 239000010410 layer Substances 0.000 description 17
- 239000011889 copper foil Substances 0.000 description 11
- 239000012790 adhesive layer Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000003566 sealing material Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000010030 laminating Methods 0.000 description 5
- 238000003475 lamination Methods 0.000 description 5
- 239000003513 alkali Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000004080 punching Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920006231 aramid fiber Polymers 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 235000019589 hardness Nutrition 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 238000007789 sealing Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
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Abstract
Description
本発明は、外部接続用電極を備えた半導体構成体を有機基板に内蔵し、再配線化した半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device in which a semiconductor structure having an external connection electrode is built in an organic substrate and rewired, and a method for manufacturing the same.
最近、電子機器の軽薄短小化が進み、機器に搭載される外部接続用電極を備えた半導体構成体を有機基板に内蔵し、細配線化した半導体装置が使用されている。ここに内蔵される半導体構成体は、一般に複数の外部接続用の接続パッドが形成されたベアの半導体装置の上面に封止材を設け、次いで、当該封止材の各接続パッドに対応する部分に開口部を形成し、次いで、当該開口部を介して各接続パッドに接続される再配線を形成し、次いで、各再配線の他の接続部に柱状の外部接続用電極を形成すると共に、絶縁樹脂で封止後、研磨にて外部接続用電極が露出するまで研磨し、次いで、露出した外部接続用電極にはんだを形成することによって製造されている（例えば、特許文献１参照）。 In recent years, electronic devices have become lighter, thinner, and smaller, and semiconductor devices in which a semiconductor structure having an external connection electrode mounted on a device is built in an organic substrate and thinned are used. The semiconductor structure incorporated therein is generally provided with a sealing material on the upper surface of a bare semiconductor device in which a plurality of connection pads for external connection are formed, and then a portion corresponding to each connection pad of the sealing material Forming an opening, and then forming a rewiring connected to each connection pad through the opening, then forming a columnar external connection electrode on the other connection of each rewiring, After sealing with an insulating resin, it is manufactured by polishing until the external connection electrode is exposed, and then forming solder on the exposed external connection electrode (see, for example, Patent Document 1).
また、従来の半導体装置は斯かる半導体構成体を用いて製造されるが、以下、従来の半導体装置の製造方法を図３乃至図４に示した製造工程図を用いて具体的に説明する。尚、当該図３乃至図４において同じ部位については、各々の図への符号付けを省略した。 A conventional semiconductor device is manufactured using such a semiconductor structure. Hereinafter, a conventional method for manufacturing a semiconductor device will be specifically described with reference to manufacturing process diagrams shown in FIGS. In addition, about the same site | part in the said FIG. 3 thru | or FIG. 4, the code | symbol to each figure was abbreviate | omitted.
まず、キャリア付き銅箔ベース材料（以下「ベース材料」と表記する）３７に、銅ポスト３２、封止材３３及びシリコン３４を備えた半導体構成体３１を、接着層３５を介してボンダ装置にて搭載（仮配置）すると共に、絶縁材（埋め込み材）３６をパンチングプレス機にてパンチングし、半導体構成体３１にはめ込む窓抜きをした後、積層冶具を用いて、図３（ａ）に示したように、半導体構成体３１を搭載したベース材料３７に絶縁材（埋め込み材）３６をレイアップし、真空積層プレス機にて積層プレスを行い、図３（ｂ）に示したような構造体を得る。 First, a semiconductor structure 31 including a copper post 32, a sealing material 33, and silicon 34 on a copper foil base material with carrier (hereinafter referred to as “base material”) 37 is bonded to a bonder device via an adhesive layer 35. 3 (a), the insulating material (embedding material) 36 is punched with a punching press machine, the window is inserted into the semiconductor structure 31, and is then used as shown in FIG. As shown in FIG. 3B, the insulating material (embedding material) 36 is laid up on the base material 37 on which the semiconductor structure 31 is mounted, and the lamination press is performed by a vacuum laminating press. Get.
次いで、前記積層プレスによって半導体構成体３１上にもフローした絶縁材（埋め込み材）３９（図３（ｂ）参照）を、研磨機にて表面研磨して図３（ｃ）に示したような構造体とした後、ベース材料３７のキャリアを剥ぎ、次いで、アルカリエッチャにて全面エッチング除去して図３（ｄ）に示したような半導体構成体内蔵基材４０を得る。 Next, the insulating material (embedding material) 39 (see FIG. 3B) that also flowed onto the semiconductor structure 31 by the laminating press is subjected to surface polishing with a polishing machine, as shown in FIG. After forming the structure, the carrier of the base material 37 is peeled off, and then the entire surface is etched away with an alkali etcher to obtain the semiconductor structure built-in substrate 40 as shown in FIG.
次いで、図４（ｇ）に示したように、前記半導体構成体内蔵基材４０の上下それぞれに絶縁層４１、導体層４２を形成した後、層間接続スルーホール４４形成、層間接続ビア４３形成、めっき（図示省略）形成、回路４５形成をして、図４（ｈ）に示したような半導体装置Ｐａ’を得る。 Next, as shown in FIG. 4G, after forming the insulating layer 41 and the conductor layer 42 on the upper and lower sides of the semiconductor structure-containing substrate 40, the interlayer connection through-hole 44, the interlayer connection via 43, Plating (not shown) and circuit 45 are formed to obtain a semiconductor device Pa ′ as shown in FIG.
しかしながら、有機基板の中に半導体構成体を内蔵すると、半導体構成体の一部であるシリコンと、有機基板の一部である絶縁材とが線膨張係数が異なるため、熱工程などでクラックが生じやすいという問題があった。 However, if the semiconductor structure is built in the organic substrate, the silicon that is a part of the semiconductor structure and the insulating material that is a part of the organic substrate have different linear expansion coefficients. There was a problem that it was easy.
それを避けるためには、外部接続用電極はある程度の高さが必要となり、これ以上半導体装置を薄くできないのが実状であった。 In order to avoid this, the external connection electrode needs to have a certain height, and the actual situation is that the semiconductor device cannot be made thinner.
そこで、シリコンからなる半導体装置を小さくして、マトリクス状の狭ピッチ配線を形成し、外部接続用電極を形成し、絶縁樹脂で封止し、個片化した半導体構成体を有機基板に埋め込み再配線することでマザーボードに精度よく実装できる配線ピッチが可能となる半導体装置が提案されている（例えば，特許文献２参照）。 Therefore, the semiconductor device made of silicon is reduced to form a matrix-like narrow pitch wiring, an external connection electrode is formed, sealed with an insulating resin, and the separated semiconductor structure is embedded in an organic substrate. A semiconductor device has been proposed in which a wiring pitch that can be accurately mounted on a mother board by wiring is possible (for example, see Patent Document 2).
しかしながら、半導体構成体の上層に複数層の絶縁層を重ね、再配線を繰り返すとどうしても総板厚が厚くなるため、特に、携帯電話機器などのモバイル製品に適用しようとしても、厚み制限で採用されないという問題が発生していた。 However, if multiple layers of insulating layers are stacked on top of the semiconductor structure and rewiring is repeated, the total plate thickness will inevitably increase. Therefore, even if it is applied to mobile products such as mobile phone devices, it is not adopted due to thickness restrictions. The problem that occurred.
一方、半導体構成体を薄くするとウエハーサイズの時点で反りが大きく発生するため、薄い半導体構成体を製造するのは困難である。また、薄い半導体構成体はハンドリングが難しく、割れ易いという難点がある。更に、薄い半導体構成体はマザーボード上への搭載も容易ではない。 On the other hand, if the semiconductor structure is thinned, warping is greatly generated at the time of the wafer size, so that it is difficult to manufacture a thin semiconductor structure. In addition, a thin semiconductor structure is difficult to handle and easily broken. Furthermore, a thin semiconductor structure is not easy to mount on a motherboard.
また仮に、半導体構成体を薄くする為に外部接続用電極側を研磨すると、電極表面頭出しの為の研磨と異なり電極に強いストレスが掛かる為、電極がシリコン本体から断線してしまうかまたは電極自体が破損してしまう恐れがあった。また逆に、シリコン側を研磨する場合、絶縁材（埋め込み材）に埋め込まれたままの状態で研磨を行うと、硬度の異なるシリコンと絶縁材を同時に研磨することとなり、研磨ムラが発生するという問題があった。
本発明は、上記不具合を解消すべくなされたもので、その課題とするところは、総板厚の薄い半導体装置及びその製造方法を提供することにある。 The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device having a thin total plate thickness and a manufacturing method thereof.
本発明者は上記課題を解決するために種々検討を重ねた結果、上面に複数の外部接続用電極を有する半導体構成体と、前記半導体構成体の側方に設けられた絶縁層とを有する半導体構成体内蔵基材の上下に、少なくとも１層の絶縁層と導体層が設けられた半導体装置において、前記半導体構成体の構成材たるシリコンを研磨して薄型化すれば、半導体構成体内蔵基材、従ってまた半導体装置の厚みを薄くできることを見い出し、本発明を完成したものである。 As a result of various studies to solve the above problems, the present inventor has found that a semiconductor structure having a plurality of external connection electrodes on the upper surface and an insulating layer provided on the side of the semiconductor structure. In a semiconductor device in which at least one insulating layer and a conductor layer are provided above and below a substrate with a built-in structure, if the silicon that is a component of the semiconductor structure is polished and thinned, the substrate with a built-in semiconductor structure Thus, it has been found that the thickness of the semiconductor device can be reduced, and the present invention has been completed.
すなわち、請求項１に係る本発明は、外部接続用電極を備えた半導体構成体を絶縁材に内蔵し、再配線化した半導体装置において、当該内蔵された半導体構成体の構成材たるシリコンが研磨処理により薄型化されていることを特徴とする半導体装置により上記課題を解決したものである。 That is, according to the first aspect of the present invention, in a semiconductor device in which a semiconductor structure having an external connection electrode is built in an insulating material and rewired, silicon constituting the built-in semiconductor structure is polished. The above-described problems are solved by a semiconductor device that is thinned by processing.
このように、本発明の半導体装置においては、内蔵されている半導体構成体が薄型化されているので、総板厚の薄い半導体装置となっている。 Thus, in the semiconductor device of the present invention, since the built-in semiconductor structure is thinned, the semiconductor device has a thin total plate thickness.
また、請求項２に係る本発明は、前記再配線化した半導体構成体が、複数の外部接続用電極を備えた半導体構成体と、当該半導体構成体の側方に配置された絶縁材と、当該半導体構成体及び絶縁材の上層に設けられた絶縁層と、当該半導体構成体の外部接続用電極から上層の絶縁層を介して形成された再配線を備えていることを特徴とする。 Further, the present invention according to claim 2, wherein the rewiring semiconductor structure comprises a semiconductor structure provided with a plurality of external connection electrodes, an insulating material disposed on the side of the semiconductor structure, An insulating layer provided on an upper layer of the semiconductor structure and the insulating material, and a rewiring formed from an external connection electrode of the semiconductor structure through an upper insulating layer.
これにより、従来の半導体装置の製造方法に用いる材料の他に新規の材料を追加することがない、総板厚の薄い半導体装置となっている。 As a result, the semiconductor device has a thin total plate thickness in which no new material is added in addition to the material used in the conventional method for manufacturing a semiconductor device.
また、請求項３に係る本発明は、前記側方の絶縁材が補強材を含むことを特徴とする。 The invention according to claim 3 is characterized in that the lateral insulating material includes a reinforcing material.
これにより、半導体装置に内蔵されている半導体構成体の構成材たるシリコンが研磨処理される際、半導体構成体が半導体装置から抜け落ちることがない、総板厚の薄い半導体装置となっている。 As a result, when silicon, which is a constituent material of the semiconductor structure incorporated in the semiconductor device, is polished, the semiconductor structure does not fall out of the semiconductor device.
また、請求項４に係る本発明は、外部接続用電極を備えた半導体構成体を絶縁材に内蔵せしめて半導体構成体内蔵基材を得る工程と、当該半導体構成体内蔵基材を半導体構成体の構成材たるシリコン側から研磨して薄型化する工程と、当該薄型化された半導体構成体基材に再配線を形成する工程とを有することを特徴とする半導体装置の製造方法により上記課題を解決したものである。 According to a fourth aspect of the present invention, there is provided a step of obtaining a semiconductor structure built-in base material by incorporating a semiconductor structure having an external connection electrode in an insulating material, and the semiconductor structure built-in base material as a semiconductor structure. The above-mentioned problem is achieved by a method of manufacturing a semiconductor device, comprising: a step of polishing and thinning from a silicon side which is a constituent material of the semiconductor device; and a step of forming rewiring on the thinned semiconductor structure substrate. It has been solved.
これにより、総板厚の薄い半導体装置を効率良く得ることができる。 Thereby, a semiconductor device with a thin total plate thickness can be obtained efficiently.
また、請求項５に係る本発明は、前記半導体装置の製造を、ベース材料に半導体構成体を搭載し、次いで、当該半導体構成体の側方に金属箔と絶縁材を配置し積層し、次いで、前記ベース材料を除去して半導体構成体内蔵基材とし、次いで、当該内蔵された半導体構成体の構成材たるシリコン側を研磨し、次いで、当該半導体構成体内蔵基材の上下に絶縁層を積層し、次いで、当該半導体構成体及び側方の絶縁材上に再配線を形成して行なうことを特徴とする。 Further, the present invention according to claim 5 is the manufacture of the semiconductor device, wherein a semiconductor structure is mounted on a base material, and then a metal foil and an insulating material are disposed and laminated on the side of the semiconductor structure, The base material is removed to form a semiconductor structure built-in base material, and then the silicon side as a constituent material of the built-in semiconductor structure is polished, and then insulating layers are formed above and below the semiconductor structure built-in base material. Lamination is performed, and then rewiring is performed on the semiconductor structure and the side insulating material.
これにより、絶縁材表面から半導体構成体のシリコンの一部が突出している半導体構成体内蔵基材が効率良く得られる。 Thereby, the base material with a built-in semiconductor structure in which a part of silicon of the semiconductor structure projects from the surface of the insulating material can be obtained efficiently.
また、請求項６に係る本発明は、前記の製造方法において、前記半導体構成体の構成材たるシリコンの一部を、絶縁材表面から突出せしめて半導体構成体内蔵基材を得ることを特徴とする。 Further, the present invention according to claim 6 is characterized in that, in the manufacturing method, a part of silicon as a constituent material of the semiconductor constituent body is protruded from the surface of the insulating material to obtain a semiconductor constituent built-in base material. To do.
これにより、半導体構成体内蔵基材をシリコン側から容易に研磨し得、しかも研磨ムラが発生することもない。 As a result, the semiconductor component built-in substrate can be easily polished from the silicon side, and polishing unevenness does not occur.
また、請求項７に係る本発明は、前記の製造方法において、前記半導体構成体の側方に配置された金属箔を、ベース材料と同時に除去することにより、半導体構成体の構成材たるシリコンの一部を絶縁材表面から突出せしめることを特徴とする。 According to a seventh aspect of the present invention, in the manufacturing method described above, the metal foil disposed on the side of the semiconductor structure is removed at the same time as the base material, so that silicon as a constituent material of the semiconductor structure is removed. A part is projected from the surface of the insulating material.
これにより、絶縁材表面から半導体構成体のシリコンの一部を突出させる際に、ベース材料を除去する工程と金属箔を除去する工程が同時に行えるため、絶縁材表面から半導体構成体のシリコンの一部が突出している半導体構成体内蔵基材が効率良く得られる。 As a result, when part of the silicon of the semiconductor structure is protruded from the surface of the insulating material, the step of removing the base material and the step of removing the metal foil can be performed simultaneously. The base material with a built-in semiconductor structure with protruding portions can be obtained efficiently.
また、請求項８に係る本発明は、前記の製造方法において、前記金属箔の厚みを適宜選択することにより、半導体構成体の構成材たるシリコン側からの研磨量を調整することを特徴とする。 Moreover, the present invention according to claim 8 is characterized in that, in the above manufacturing method, the polishing amount from the silicon side which is a constituent material of the semiconductor structure is adjusted by appropriately selecting the thickness of the metal foil. .
これにより、半導体構成体内蔵基材の、従ってまた半導体装置の薄型化と機械強度を両立するための適当な厚みが得られる。 As a result, an appropriate thickness can be obtained for the substrate with a built-in semiconductor structure, and thus for achieving both a reduction in thickness and mechanical strength of the semiconductor device.
また、請求項９に係る本発明は、前記の製造方法において、前記側方の絶縁材が補強材を含んでいることを特徴とする。 The present invention according to claim 9 is characterized in that, in the manufacturing method, the side insulating material includes a reinforcing material.
これにより、半導体装置に内蔵されている半導体構成体の構成材たるシリコンが研磨処理される際、半導体構成体が半導体装置から抜け落ちることがなく、確実に研磨処理ができる。 Thus, when silicon, which is a constituent material of the semiconductor structure incorporated in the semiconductor device, is polished, the semiconductor structure does not fall out of the semiconductor device, and the polishing process can be performed reliably.
本発明によれば、総板厚の薄い半導体装置を提供することができる。 According to the present invention, a semiconductor device having a thin total plate thickness can be provided.
以下本発明の実施の形態を、図１乃至図２に示した本発明の半導体装置の製造工程図を用いて説明する。尚、当該図１乃至図２において同じ部位については、各々の図への符号付けを省略した。 Embodiments of the present invention will be described below with reference to the manufacturing process diagrams of the semiconductor device of the present invention shown in FIGS. In addition, about the same site | part in the said FIG. 1-2, the code | symbol to each figure was abbreviate | omitted.
まず、ベース材料７に、銅ポスト２、封止材３及びシリコン４を備えた半導体構成体１を、接着層５を介してボンダ装置にて搭載すると共に、絶縁材（埋め込み材）６と銅箔８をパンチングプレス機にてパンチングし、半導体構成体１にはめ込む窓抜きをした後、積層冶具を用いて、図１（ａ）に示したように、半導体構成体１を搭載したベース材料７に銅箔８、絶縁材（埋め込み材）６の順にレイアップし、真空積層プレス機にて積層プレスを行い、図１（ｂ）に示すような構造体を得る。 First, the semiconductor structure 1 including the copper post 2, the sealing material 3, and the silicon 4 is mounted on the base material 7 by the bonder device via the adhesive layer 5, and the insulating material (embedding material) 6 and copper are mounted. After punching the foil 8 with a punching press machine and removing a window that fits into the semiconductor structure 1, the base material 7 on which the semiconductor structure 1 is mounted as shown in FIG. Then, the copper foil 8 and the insulating material (embedding material) 6 are laid up in this order, and a lamination press is performed with a vacuum lamination press to obtain a structure as shown in FIG.
尚、半導体装置に内蔵されている半導体構成体の構成材たるシリコンが研磨処理される際、半導体構成体が半導体装置から抜け落ちることがなく確実に研磨処理ができるように、前記絶縁材（埋め込み材）６には、補強材が含まれていることが望ましい。 The insulating material (embedding material) is used so that when silicon, which is a constituent material of a semiconductor structure incorporated in a semiconductor device, is polished, the semiconductor structure can be reliably polished without falling off the semiconductor device. ) 6 preferably includes a reinforcing material.
また、前記補強材が含まれている絶縁材（埋め込み材）６は、基材としての汎用性、利便性、信頼性等を考慮して、ガラスクロス、ガラス繊維、アラミド繊維にエポキシ樹脂を含浸させたもの、無機フィラーをエポキシ樹脂を含浸させたもの等、補強が施された一般基材であることが望ましい。 The insulating material (embedding material) 6 containing the reinforcing material is impregnated with epoxy resin in glass cloth, glass fiber, and aramid fiber in consideration of versatility, convenience, reliability, etc. as a base material. It is desirable to use a general base material that has been reinforced, such as an inorganic filler impregnated with an epoxy resin.
次いで、前記積層プレスによって半導体構成体１上にもフローした絶縁材（埋め込み材）９（図１（ｂ）参照）を、研磨機にて表面研磨して図１（ｃ）に示したような構造体を得る。次いで、ベース材料７のキャリアを剥ぎ、次いで、アルカリエッチャにて全面エッチング除去して図１（ｄ）に示したような構造体とした後、更にベース材料７上部にあった銅箔８も全面エッチング除去して、接着層５及びシリコン４の一部が絶縁材（埋め込み材）９の表面から突出した、図１（ｅ）に示したような構造体を得る。 Next, the insulating material (embedding material) 9 (see FIG. 1B) that has also flowed onto the semiconductor structure 1 by the laminating press is subjected to surface polishing with a polishing machine, as shown in FIG. Get a structure. Next, the carrier of the base material 7 is peeled off, and then the entire surface is removed by etching with an alkali etcher to obtain a structure as shown in FIG. The entire surface is removed by etching to obtain a structure as shown in FIG. 1E in which a part of the adhesive layer 5 and silicon 4 protrudes from the surface of the insulating material (embedding material) 9.
次いで、研磨機にて絶縁材（埋め込み材）９から突出している当該接着層５及びシリコン４を片面二軸表面研磨機やバックグラインダー等で表面研磨して図１（ｆ）に示したような半導体構成体内蔵基板１０を得る。 Next, the adhesive layer 5 and silicon 4 protruding from the insulating material (embedding material) 9 are polished by a polishing machine with a single-sided biaxial surface polishing machine, a back grinder, or the like, as shown in FIG. The semiconductor structure built-in substrate 10 is obtained.
このとき、バフ研磨をする場合の条件として、使用するバフはダブルコアのセラミックホイールで番手が＃１８０、コンベア速度が１．０〜２．０ｍ／ｍｉｎ、バフの回転数が１７００〜１９００ｒｐｍ、オシレーションが４２０〜５００回／分の範囲とすることが望ましい。 At this time, as a condition for buffing, the buff used is a double-core ceramic wheel with a count of # 180, a conveyor speed of 1.0 to 2.0 m / min, a buff speed of 1700 to 1900 rpm, and an oscillation. Is preferably in the range of 420 to 500 times / minute.
また、バフが被研磨対象物に掛ける研磨圧は、研磨前の被研磨対象物の表面を基準とした研磨機の初期設定に対し、バフが被研磨対象物の表面に掛ける圧力に必要な電流値で表現され、その値は１〜１０Ａが望ましい。１Ａ以下では被研磨対象物の表面にキズをつける程度に留まり厚みを変化させるほどの研磨は難しく、逆に１０Ａ以上では被研磨対象物周辺の対象外部分も研磨してしまう場合がある。特に、被研磨対象物のシリコンを１０〜１００μｍ程度研磨する場合には、電流値が５〜８Ａの範囲が望ましい。 The polishing pressure that the buff applies to the object to be polished is the current required for the pressure that the buff applies to the surface of the object to be polished relative to the initial setting of the polishing machine based on the surface of the object to be polished before polishing. It is expressed by a value, and the value is preferably 1 to 10A. If it is 1A or less, it is difficult to polish to such an extent that the surface of the object to be polished is scratched and the thickness is changed. On the other hand, if it is 10A or more, an untargeted part around the object to be polished may be polished. In particular, when polishing silicon of the object to be polished by about 10 to 100 μm, the current value is preferably in the range of 5 to 8A.
半導体構成体１の表裏面を除く四側面の少なくとも一部が埋め込み材９によって固定され、且つ、半導体構成体１の構成材たるシリコン４が絶縁材（埋め込み材）９から一部突起した状態において、研磨条件を前記とすることで、当該シリコン４側から破損することなく平坦に研磨でき、結果として、図１（ｆ）に示したように、従来より薄型化された半導体構成体内蔵基材１０が得られる。 In a state in which at least a part of the four side surfaces excluding the front and back surfaces of the semiconductor structure 1 is fixed by the embedding material 9 and the silicon 4 as the material of the semiconductor structure 1 is partially projected from the insulating material (embedding material) 9 By setting the polishing conditions as described above, the substrate can be polished flat without being damaged from the silicon 4 side. As a result, as shown in FIG. 10 is obtained.
次いで、図２（ｇ）に示したように、前記半導体構成体内蔵基材１０の上下それぞれに絶縁層１１、導体層１２を形成した後、図２（ｈ）に示したように、層間接続スルーホール１４形成、層間接続ビア１３形成、めっき（図示省略）形成、回路１５形成をして、従来より薄型化された半導体装置Ｐａを得る。 Next, as shown in FIG. 2 (g), after forming the insulating layer 11 and the conductor layer 12 on the upper and lower sides of the substrate 10 with a built-in semiconductor structure, as shown in FIG. 2 (h), the interlayer connection Through-hole 14 formation, interlayer connection via 13 formation, plating (not shown) formation, and circuit 15 formation are performed to obtain a semiconductor device Pa that is thinner than before.
実施例１
図１乃至図２に示した半導体装置Ｐａの製造工程図に倣って、本発明の実施例を説明する。
Example 1
An embodiment of the present invention will be described following the manufacturing process diagrams of the semiconductor device Pa shown in FIGS.
予め次の材料を用意した。
ベース材料７としては、キャリアとして用いる厚み７０μｍの銅箔に、半導体構成体１を搭載するベース材料となる厚み９μｍの銅箔が密着したもの。
銅箔８としては、厚み３５μｍの銅箔。
埋め込み材６としては、日立化成工業株式会社製反り防止コアＭＣＬ−Ｅ−６７９Ｆ−０．１ｔ（厚み仕様１００μｍ）の上下各々に、日立化成工業株式会社製プリプレグＧＥＡ−６７９Ｆ−０．０８ｔ（厚み仕様８０μｍ）を合わせたもの。
接着層付き半導体構成体１としては、幅と奥行きが５．７５mm角で厚みが４００μｍのもの。
The following materials were prepared in advance.
As the base material 7, a copper foil having a thickness of 9 μm as a base material on which the semiconductor structure 1 is mounted is adhered to a copper foil having a thickness of 70 μm used as a carrier.
The copper foil 8 is a 35 μm thick copper foil.
As the embedment material 6, a prepreg GEA-679F-0.08t (thickness) manufactured by Hitachi Chemical Co., Ltd. Combined specifications 80μm).
The semiconductor structure 1 with an adhesive layer has a width and depth of 5.75 mm square and a thickness of 400 μm.
まず、ベース材料７に、銅ポスト２、封止材３及びシリコン４を備えた半導体構成体１を、接着層５を介してボンダ装置にて搭載すると共に、絶縁材（埋め込み材）６と銅箔８をパンチングプレス機にてパンチングし、半導体構成体１にはめ込む窓抜きをした。絶縁材（埋め込み材）はプリプレグ、反り防止コア、プリプレグの順に重ねてパンチングした。窓抜きのクリアランスは片側０．２mmとした。 First, the semiconductor structure 1 including the copper post 2, the sealing material 3, and the silicon 4 is mounted on the base material 7 by the bonder device via the adhesive layer 5, and the insulating material (embedding material) 6 and copper are mounted. The foil 8 was punched with a punching press machine, and a window was inserted into the semiconductor structure 1. The insulating material (embedding material) was punched by overlapping the prepreg, the warp prevention core, and the prepreg in this order. The window opening clearance was 0.2 mm on one side.
次に、積層冶具を用いて、図１（ａ）に示すように、半導体構成体１を搭載したベース材料７に銅箔８、絶縁材（埋め込み材）６の順にレイアップし、真空積層プレス機にて積層プレスを行い、図１（ｂ）に示したような構造体を得た。 Next, as shown in FIG. 1A, a laminated jig is used to lay up the copper foil 8 and the insulating material (embedding material) 6 in this order on the base material 7 on which the semiconductor structure 1 is mounted, and vacuum lamination press A laminating press was performed with a machine to obtain a structure as shown in FIG.
次いで、前記積層プレスによって半導体構成体１上にもフローした絶縁材（埋め込み材）９を片面二軸研磨機にて表面研磨した。ここで、研磨の条件は、コンベア速度２．０m／min、バフ回転数１８００rpm、オシレーション４６０回／分とした。研磨後、図１（ｃ）に示したような構造体を得た。 Next, the insulating material (embedding material) 9 that also flowed onto the semiconductor structure 1 by the laminating press was subjected to surface polishing with a single-sided biaxial polishing machine. Here, the polishing conditions were a conveyor speed of 2.0 m / min, a buff rotation speed of 1800 rpm, and an oscillation of 460 times / min. After polishing, a structure as shown in FIG. 1C was obtained.
次いで、ベース材料７のキャリアを剥ぎ、短時間で全面エッチング可能なアルカリエッチャにてベース材料となる銅箔を全面エッチング除去した。ここで、エッチング条件は、コンベア速度０．８m／min、液温４５℃とした。エッチング後、図１（ｄ）に示したような構造体を得た。 Next, the carrier of the base material 7 was peeled off, and the copper foil as the base material was removed by etching with an alkali etcher that can be etched in a short time. Here, the etching conditions were a conveyor speed of 0.8 m / min and a liquid temperature of 45 ° C. After the etching, a structure as shown in FIG. 1 (d) was obtained.
続いて、更にベース材料７上部にあった銅箔８も、短時間で全面エッチング可能なアルカリエッチャにて全面エッチング除去した。ここで、エッチング条件は、コンベア速度０．８m／min、液温４５℃とし、全面エッチングされるまで流した。エッチング後、接着層５及びシリコン４の一部が絶縁材（埋め込み材）９の表面から突出した、図１（ｅ）に示した構造体を得た。 Subsequently, the copper foil 8 on the base material 7 was also removed by etching with an alkali etcher capable of etching the entire surface in a short time. Here, the etching conditions were a conveyor speed of 0.8 m / min, a liquid temperature of 45 ° C., and flowed until the entire surface was etched. After the etching, the structure shown in FIG. 1E was obtained in which a part of the adhesive layer 5 and silicon 4 protruded from the surface of the insulating material (embedding material) 9.
次いで、片面二軸研磨機で埋め込み材９から突出している当該接着層５及びシリコン４を表面研磨した。ここで、片側二軸研磨機の条件は、コンベア速度２．０m／min、バフ回転数１８００rpm、オシレーション４６０回／分で、バフは株式会社石井表記製のダブルコアを用いた。研磨後、図１（ｆ）に示したような従来より薄型化された半導体構成体内蔵基材１０を得た。 Next, the adhesive layer 5 and silicon 4 protruding from the embedding material 9 were subjected to surface polishing with a single-sided biaxial polishing machine. Here, the conditions of the single-sided biaxial polishing machine were a conveyor speed of 2.0 m / min, a buff rotation speed of 1800 rpm, and an oscillation of 460 times / min, and a double core made by Ishii Corporation was used as the buff. After the polishing, the base material 10 with a built-in semiconductor structure as shown in FIG.
次いで、図２（ｇ）に示したように、前記半導体構成体内蔵基材１０の上下それぞれに絶縁層１１、導体層１２を形成した後、図２（ｈ）に示したように、層間接続スルーホール１４形成、層間接続ビア１３形成、めっき（図示省略）形成、回路１５形成をして、総厚み７６５μｍの半導体装置Ｐａを得た。 Next, as shown in FIG. 2 (g), after forming the insulating layer 11 and the conductor layer 12 on the upper and lower sides of the substrate 10 with a built-in semiconductor structure, as shown in FIG. 2 (h), the interlayer connection Through-hole 14 formation, interlayer connection via 13 formation, plating (not shown) formation, and circuit 15 formation were performed to obtain a semiconductor device Pa having a total thickness of 765 μm.
因に、図３乃至図４に示される従来の製造方法により製造された半導体装置Ｐａ’の総厚みは８００μｍであり、本発明の半導体装置Ｐａは従来より３５μｍ薄型化されている。 Incidentally, the total thickness of the semiconductor device Pa ′ manufactured by the conventional manufacturing method shown in FIGS. 3 to 4 is 800 μm, and the semiconductor device Pa of the present invention is thinner by 35 μm than the conventional one.
本発明を説明するに当たって、図１乃至図２を例にして説明したが、本発明の構成はこの限りでなく、またこの例により何ら制限されるものではなく、本発明の範囲内で種々の変更が可能である。 In the description of the present invention, FIGS. 1 and 2 have been described by way of example. However, the configuration of the present invention is not limited to this example, and is not limited to this example. Various modifications are possible within the scope of the present invention. It can be changed.
１，３１：半導体構成体
２，３２：銅ポスト
３，３３：封止材
４，３４：シリコン（Ｓｉ）
５，３５：接着層
６，９，３６，３９：絶縁材（埋め込み材）
７，３７：キャリア付き銅箔ベース材料
８：銅箔
１０，４０：半導体構成体内蔵基材
１１，４１：絶縁層
１２，４２：導体層
１３，４３：層間接続ビア
１４，４４：層間接続スルーホール
１５，４５：回路（回路形成された導体層）
Ｐａ，Ｐａ’：半導体装置
DESCRIPTION OF SYMBOLS 1,31: Semiconductor structure 2, 32: Copper post 3,33: Sealing material 4,34: Silicon (Si)
5, 35: Adhesive layers 6, 9, 36, 39: Insulating material (embedding material)
7, 37: Copper foil base material with carrier 8: Copper foil 10, 40: Substrate with built-in semiconductor structure 11, 41: Insulating layer 12, 42: Conductor layer 13, 43: Interlayer connection via 14, 44: Interlayer connection through Holes 15 and 45: circuit (conductor layer on which the circuit is formed)
Pa, Pa ′: Semiconductor device
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006049731A JP2007227834A (en) | 2006-02-27 | 2006-02-27 | Semiconductor device, and method for manufacturing same |
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| Application Number | Priority Date | Filing Date | Title |
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| JP2006049731A JP2007227834A (en) | 2006-02-27 | 2006-02-27 | Semiconductor device, and method for manufacturing same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2007227834A true JP2007227834A (en) | 2007-09-06 |
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| JP2006049731A Pending JP2007227834A (en) | 2006-02-27 | 2006-02-27 | Semiconductor device, and method for manufacturing same |
Country Status (1)
| Country | Link |
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| JP (1) | JP2007227834A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012216601A (en) * | 2011-03-31 | 2012-11-08 | Fujitsu Ltd | Electronic device manufacturing method and electronic device |
| JP2020065088A (en) * | 2020-01-29 | 2020-04-23 | 株式会社アムコー・テクノロジー・ジャパン | Semiconductor device and method for manufacturing the same |
-
2006
- 2006-02-27 JP JP2006049731A patent/JP2007227834A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012216601A (en) * | 2011-03-31 | 2012-11-08 | Fujitsu Ltd | Electronic device manufacturing method and electronic device |
| JP2020065088A (en) * | 2020-01-29 | 2020-04-23 | 株式会社アムコー・テクノロジー・ジャパン | Semiconductor device and method for manufacturing the same |
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