JP2007227757A - Base board for mounting semiconductor element - Google Patents

Base board for mounting semiconductor element Download PDF

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JP2007227757A
JP2007227757A JP2006048469A JP2006048469A JP2007227757A JP 2007227757 A JP2007227757 A JP 2007227757A JP 2006048469 A JP2006048469 A JP 2006048469A JP 2006048469 A JP2006048469 A JP 2006048469A JP 2007227757 A JP2007227757 A JP 2007227757A
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semiconductor element
pad
conductor
opening
substrate
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JP4957013B2 (en
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Masahito Tsujii
雅人 辻井
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Toppan Inc
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Toppan Printing Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45748—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit
    • H03F3/45753—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit using switching means, e.g. sample and hold
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45757—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedforward circuit
    • H03F3/45762—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedforward circuit using switching means, e.g. sample and hold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/453—Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45212—Indexing scheme relating to differential amplifiers the differential amplifier being designed to have a reduced offset
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45588—Indexing scheme relating to differential amplifiers the IC comprising offset compensating means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45616—Indexing scheme relating to differential amplifiers the IC comprising more than one switch, which are not cross coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45652—Indexing scheme relating to differential amplifiers the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45681—Indexing scheme relating to differential amplifiers the LC comprising offset compensating means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45726—Indexing scheme relating to differential amplifiers the LC comprising more than one switch, which are not cross coupled

Abstract

<P>PROBLEM TO BE SOLVED: To provide a base board that suppresses a transmission loss caused by reflection in high-frequency transmission between a base board for mounting a semiconductor element and a printed-wiring board. <P>SOLUTION: A structure has been used to reduce a capacity coupling between pads and inner-layer conductive layers such that a discontinuous degree of characteristic impedance is suppressed, the structure in which openings 20 and 21 with a diameter larger than the pad's diameter are formed at positions opposed to pads of inner conductive layers 6 and 10 so as to be adjacent to a pad 14, and conductors 11A and 5A are formed in these openings that are electrically separated from other conductors and are in a floating state. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、ＬＳＩ、ＩＣ等の半導体素子を搭載するための基板に関し、特にパッドの反射による伝送損失を抑制した高周波伝送用の半導体素子搭載用基板に関する。   The present invention relates to a substrate for mounting a semiconductor element such as an LSI or an IC, and more particularly to a semiconductor element mounting substrate for high-frequency transmission in which transmission loss due to pad reflection is suppressed.

近年の情報機器の高速伝送化に伴い、信号周波数の高周波化や広帯域化が進み、信号の信頼性確保が厳しく問われるようになった。
一方、インターポーザとプリント配線基板の接続方法には主にＱＦＰ（Quad Flat Package）に代表されるワイヤーボンディング接続、ＰＧＡ（Pin Grid Array）接続、ＢＧＡ（Ball Grid Array）接続、ＬＧＡ（Land Grid Array）接続が使われている。 With the recent high-speed transmission of information equipment, the signal frequency has been increased and the bandwidth has been increased, and ensuring the reliability of the signal has become strict.
On the other hand, the interposer and printed wiring board are mainly connected by wire bonding represented by QFP (Quad Flat Package), PGA (Pin Grid Array) connection, BGA (Ball Grid Array) connection, LGA (Land Grid Array). Connection is in use.

このうちワイヤーボンディング接続は、リードフレームとワイヤー部の誘導性に起因する高周波インピーダンスが無視できず、高周波信号の伝送特性の劣化をもたらす。
また、ＰＧＡ接続は、ＰＧＡのピンの受け皿としてプリント配線板にスルーホールを設けており、このスルーホールがスタブとなるため高周波信号伝送を困難なものにしている。 Of these, the wire bonding connection cannot ignore the high-frequency impedance caused by the inductivity between the lead frame and the wire portion, and deteriorates the transmission characteristics of the high-frequency signal.
In addition, in the PGA connection, a through hole is provided in the printed wiring board as a tray for the pin of the PGA, and this through hole becomes a stub, making high frequency signal transmission difficult.

これに対して、ＢＧＡ接続やＬＧＡ接続は、ワイヤーボンディング接続に比べて誘導性に起因する高周波インピーダンスの影響は小さく、ＰＧＡ接続のようなスタブを形成する必要がない。そこで、近年では、ＢＧＡ接続やＬＧＡ接続を用いた実装方式が高周波信号伝送に用いられる主たる実装方式となっている。
しかし、ＢＧＡ接続やＬＧＡ接続であっても、その接続部はインターポーザやプリント配線基板上の配線のようにインピーダンスコントロールがされておらず、伝送路の反射点となっているのが現状である。 On the other hand, BGA connection and LGA connection are less affected by high frequency impedance due to inductivity than wire bonding connection, and it is not necessary to form a stub like PGA connection. Therefore, in recent years, the mounting method using BGA connection or LGA connection has become the main mounting method used for high-frequency signal transmission.
However, even in the case of BGA connection or LGA connection, the connection portion is not impedance-controlled like the wiring on the interposer or the printed wiring board, and is currently the reflection point of the transmission line.

また、インターポーザに使用している材料は主にプラスチィックで、半導体チップのような半導体素子に比べ、温度変化による膨張もしくは収縮の度合いが大きい。
そのため、インターポーザ内では、半導体素子を実装した付近で熱膨張が抑制され、それ以外の個所との熱膨張の度合いが変わる。
例えば、熱サイクル試験で観測すると、高温で半導体素子実装側に反るような力が働き、低温でプリント配線板側に反るような力が働くため、ＢＧＡ接続等に使われるパッド部の接続強度がないと、剥がれやクラックが発生してしまう。
そこで、これを回避するために、パッド面積を広く取ることで接続強度を高める手法がとられている。 The material used for the interposer is mainly plastic, and the degree of expansion or contraction due to temperature change is larger than that of a semiconductor element such as a semiconductor chip.
Therefore, in the interposer, thermal expansion is suppressed in the vicinity where the semiconductor element is mounted, and the degree of thermal expansion with other parts changes.
For example, when observed in a heat cycle test, a force that warps the semiconductor element mounting side at high temperatures and a force that warps the printed wiring board side at low temperatures work. If there is no strength, peeling and cracking will occur.
Therefore, in order to avoid this, a method of increasing the connection strength by taking a large pad area is employed.

しかしながら、パッドは対向する導体面（例えば、グランド用導体面）との容量性結合によって、伝送線路の特性インピーダンスを局部的に低下させる原因となる。
具体的には、パッドと隣接する導体面の対向している面積をＳ、パッドと導体面間の間隔をｈ、パッドと導体面間の絶縁材料の比誘電率をεｒとおくと、パッドと隣接する導体面間に働く容量Ｃpは、次の式（１）で表され、特性インピーダンスＺ0が式（２）から導かれる。

Figure 2007227757

このため、パッド部では他の部分より容量が大きくなるので、特性インピーダンスが他の部分より低くなっている。よって、パッド部はインピーダンス不連続部、つまりは信号伝送路の反射点となり、伝送特性の劣化をもたらしていることが分かる。 However, the pad causes local reduction in the characteristic impedance of the transmission line by capacitive coupling with the opposing conductor surface (for example, the ground conductor surface).
Specifically, when the opposing area of the conductor surface adjacent to the pad is S, the distance between the pad and the conductor surface is h, and the relative dielectric constant of the insulating material between the pad and the conductor surface is ε r , The capacitance Cp acting between the adjacent conductor surfaces is expressed by the following equation (1), and the characteristic impedance Z 0 is derived from the equation (2).
Figure 2007227757
For this reason, since the capacitance of the pad portion is larger than that of the other portion, the characteristic impedance is lower than that of the other portion. Therefore, it can be seen that the pad portion becomes a discontinuous portion of the impedance, that is, a reflection point of the signal transmission path, resulting in deterioration of transmission characteristics.

図３はこの問題を説明するために作成した、従来技術の半導体素子搭載用基板の例を示す図であり、図３（ａ）は断面図、図３（ｂ）は電源用導体層を示す平面図である。
図３（ａ）に示すように、この基板は、上下のソルダーレジスト１、１５の間に、導体２、４、６、９、１０、１４と絶縁材３、７、１２の各層を順次積層したものであり、グランド用導体２と信号用導体４によってＭＳＬ（マイクロストリップライン）を形成し、信号用導体４を信号用ビア８、信号用ランド９、信号用ビア１３を介してパッド１４に接続し、パッド１４を図示しない外部電気回路基板にはんだボールなどを利用して接続できるよう構成されている。また、図３（ｂ）に示すように、ランド９を設けた層には電源用導体１０が形成されており、パッド１４の上部に電気的に分離された状態で配置されている。
図４の実線１７は、図３に示す従来例の透過特性（伝送出力レベル（ｄＢ）と周波数（ＧＨｚ）の関係）を示している。
図示のように、高周波領域において伝送出力レベルが低下しており、パッド１４とその上部の導体（図３の例では電源用導体）１０との間で容量性結合を起こしていることが分かる。 FIG. 3 is a view showing an example of a conventional semiconductor element mounting substrate prepared for explaining this problem. FIG. 3A is a sectional view and FIG. 3B is a power supply conductor layer. It is a top view.
As shown in FIG. 3A, this substrate is formed by sequentially laminating conductors 2, 4, 6, 9, 10, 14 and insulating materials 3, 7, 12 between upper and lower solder resists 1, 15. An MSL (microstrip line) is formed by the ground conductor 2 and the signal conductor 4, and the signal conductor 4 is connected to the pad 14 via the signal via 8, the signal land 9, and the signal via 13. The pad 14 is configured to be connected to an external electric circuit board (not shown) using a solder ball or the like. Further, as shown in FIG. 3B, a power supply conductor 10 is formed on the layer provided with the lands 9 and is disposed in an electrically separated state on the upper portion of the pad 14.
A solid line 17 in FIG. 4 shows the transmission characteristics (relationship between transmission output level (dB) and frequency (GHz)) of the conventional example shown in FIG.
As shown in the figure, the transmission output level is lowered in the high frequency region, and it can be seen that capacitive coupling occurs between the pad 14 and the conductor (the power supply conductor in the example of FIG. 3) 10 above.

そこで、このような従来技術の対策として、パッドと容量性結合を起こす導体面にパッド径より大きい開口部を設けることで、パッド部分の容量成分を低減させ、高周波信号伝送の反射による損失を抑制する方法も提案されている（例えば特許文献１参照）。
特開２００２−２９９３７９号公報 Therefore, as a countermeasure against such a conventional technique, by providing an opening larger than the pad diameter on the conductor surface that causes capacitive coupling with the pad, the capacitance component of the pad portion is reduced and the loss due to reflection of high-frequency signal transmission is suppressed. There has also been proposed a method (see, for example, Patent Document 1).
JP 2002-299379 A

上記従来技術（図３）で説明したように、ＢＧＡ実装等に用いるパッドと隣接する導体面との容量性結合は、伝送線路の特性インピーダンスを局部的に低下させる原因となる。その結果、高周波信号に対してパッド部分が反射点となり、伝送特性の劣化をもたらすという問題がある。
また、ＢＧＡはんだボール用パッドと容量性結合を起こす導体面に開口部を設ける方法は、パッド部の容量成分を低減することは可能であるが、銅ベタパターンに大きな開口部を設けると、開口部内に気泡が残り、リフロー時に気泡が膨れてしまうといった事情から、銅ベタパターンに大きな開口部を形成できないという問題があり、実際上、適応できない基板も存在するため、より有効な対策が求められる。 As described in the above prior art (FIG. 3), the capacitive coupling between the pad used for BGA mounting and the like and the adjacent conductor surface causes a local decrease in the characteristic impedance of the transmission line. As a result, there is a problem that the pad portion becomes a reflection point for a high-frequency signal, resulting in deterioration of transmission characteristics.
In addition, the method of providing an opening in the conductor surface that causes capacitive coupling with the BGA solder ball pad can reduce the capacitance component of the pad, but if a large opening is provided in the copper solid pattern, the opening is provided. There is a problem that a large opening cannot be formed in the copper solid pattern due to the fact that air bubbles remain in the part and the air bubbles swell during reflow, and there are actually substrates that cannot be adapted, so more effective measures are required. .

本発明は、上記問題点に鑑みて提案されたものであり，その目的は、半導体素子搭載用基板とプリント配線基板間の高周波伝送における反射による伝送損失を抑制することが可能な半導体素子搭載用基板を提供することにある。   The present invention has been proposed in view of the above-described problems, and its object is to mount a semiconductor element capable of suppressing transmission loss due to reflection in high-frequency transmission between the semiconductor element mounting substrate and the printed wiring board. It is to provide a substrate.

上述の目的を達成するため、本発明の半導体素子搭載用基板は、一方の面に半導体素子を搭載し、他方の面に外部回路基板との接続用に設けられたパッドと、前記パッドに隣接して配置される内部導体層とを有した半導体素子搭載用基板であって、前記内部導体層は前記パッドと対向する部分に開口部を有し、前記パッドの径Ｗｐと、前記開口部の径Ｗｋとが、Ｗｋ≧Ｗｐの関係を有し、さらに、前記内部導体層の開口部内に他の導体と電気的に分離されて浮いた状態の導体が形成されていることを特徴とする。なお、開口部内に形成される浮いた状態の導体は、単数に限らず、複数であっても良い。また、複数層の内部導体層に開口部を設けて、それぞれに他の導体と電気的に分離されて浮いた状態の導体を形成するようにしても良い。さらに、１つの導体の面積は、１平方ｃｍ以下であることが好ましい。   In order to achieve the above object, a semiconductor element mounting substrate according to the present invention has a semiconductor element mounted on one surface, a pad provided for connection to an external circuit substrate on the other surface, and adjacent to the pad. A substrate for mounting a semiconductor element, wherein the inner conductor layer has an opening in a portion facing the pad, the pad diameter Wp, and the opening of the opening. The diameter Wk has a relationship of Wk ≧ Wp, and further, a floating conductor is formed in the opening of the inner conductor layer and is electrically separated from other conductors. Note that the number of floating conductors formed in the opening is not limited to one, but may be plural. Further, openings may be provided in the inner conductor layers of a plurality of layers, and the floating conductors may be formed separately from the other conductors. Furthermore, the area of one conductor is preferably 1 cm 2 or less.

本発明の半導体素子搭載用基板によれば、パッドに隣接して配置される内部導体層のパッド対向位置に、パッド径以上の径をもった開口部を形成し、この開口部内に他の導体と電気的に分離されて浮いた状態の導体を形成した構造により、パッドと内層導体層との間に生じる容量結合を低減し、特性インピーダンスの不連続の度合いを抑えることができる。これにより、パッド部分での反射による伝送損失を抑え、高周波信号伝送がより良好な半導体素子搭載基板を提供することが可能となる。   According to the substrate for mounting a semiconductor element of the present invention, an opening having a diameter equal to or larger than the pad diameter is formed at the pad facing position of the inner conductor layer arranged adjacent to the pad, and another conductor is formed in the opening. With the structure in which the floating conductor is formed which is electrically separated from the capacitor, capacitive coupling generated between the pad and the inner conductor layer can be reduced, and the degree of discontinuity in the characteristic impedance can be suppressed. As a result, it is possible to provide a semiconductor element mounting substrate in which transmission loss due to reflection at the pad portion is suppressed and high-frequency signal transmission is better.

本発明の実施の形態に係る半導体素子搭載用基板では、パッドに隣接して配置される内部導体層のパッド対向位置に、パッド径以上の径をもった開口部を形成し、この開口部内に他の導体と電気的に分離されて浮いた状態の導体を形成した構造により、パッドと内層導体層との間に生じる容量結合を低減し、特性インピーダンスの不連続の度合いを抑えるようにしたものである。
すなわち、パッドは対向する導体面と容量性結合を生じるが、対向する導体面がパッドと違う電位を持っている場合、パッドに流れる電流（電荷Ｑ＝ＣＶ）に大きく影響を及ぼす。そして、パッドとある電位を持った導体面の間に電気的に浮いた状態（他の導体と電気的に接続されていない状態）の導体がある場合、この浮いた状態の導体はパッドと安定した導体面間の電位分布に対応した電位となる、つまりはパッドに近い位置にある場合はパッドに近い電位を、安定した導体に近い位置にある場合は安定した導体の電位に近い電位を取ることになる。 In the semiconductor element mounting substrate according to the embodiment of the present invention, an opening having a diameter equal to or larger than the pad diameter is formed at the pad facing position of the internal conductor layer arranged adjacent to the pad, and the opening is formed in the opening. A structure in which a floating conductor is formed that is electrically isolated from other conductors to reduce capacitive coupling between the pad and the inner conductor layer and suppress the degree of discontinuity in characteristic impedance. It is.
That is, the pad causes capacitive coupling with the opposing conductor surface, but when the opposing conductor surface has a potential different from that of the pad, it greatly affects the current (charge Q = CV) flowing through the pad. If there is a conductor that is in an electrically floating state (not electrically connected to another conductor) between the pad and a conductor surface having a certain potential, this floating conductor is stable with the pad. The potential corresponding to the potential distribution between the conductor surfaces, that is, the potential close to the pad when it is close to the pad, and the potential close to the potential of the stable conductor when it is close to the stable conductor It will be.

したがって、パッドに対向する領域に浮いた状態の導体を配置することにより、パッド部の容量を低減することができ、他の部分との特性インピーダンスの不連続度合いを軽減し、伝送特性を向上できる。
また、開口部内に浮いた状態の導体を配置することにより、開口部内に気泡が残ることも防止でき、製造工程上の種々の制約をもった基板にも幅広く適応できる効果がある。
なお、この開口部内の浮いた状態の導体の面積が１平方ｃｍより大きくなると、この導体が安定した電位をもつようになり、本効果が低減してしまうため、導体の面積は１平方ｃｍ以下が好ましい。 Therefore, by disposing a floating conductor in a region facing the pad, the capacity of the pad portion can be reduced, the degree of discontinuity in characteristic impedance with other portions can be reduced, and transmission characteristics can be improved. .
Further, by disposing the floating conductor in the opening, it is possible to prevent bubbles from remaining in the opening, and there is an effect that can be widely applied to substrates having various restrictions in the manufacturing process.
When the area of the floating conductor in the opening is larger than 1 square cm, the conductor has a stable potential and this effect is reduced. Therefore, the conductor area is 1 square cm or less. Is preferred.

以下、本発明の具体例を図面を参照して説明する。
図１は、本実施の形態による半導体素子搭載用基板の第１実施例を示す図であり、図１（ａ）は断面図、図１（ｂ）は電源用導体層の形状を示す平面図である。なお、図３に示した従来例と共通の構成要素については同一符号を付し、図３と異なる部分を中心に説明する。
図１において、最下層のパッド１４と隣接する上層には、電源用導体１０のための導体層（第３層）が形成され、この層に開口部２０が形成されている。この開口部２０は、パッド１４と同心円状に形成され、パッド１４より大きい径をもっている。なお、パッド１４と同等の径を有する開口部であってもよい。
そして、この開口部２０内に他の導体と電気的に分離されて浮いた状態の導体１１Ａを形成している。この導体１１Ａは、図１（ｂ）に示すように、ランド９を中心とした円環状に形成されている。 Specific examples of the present invention will be described below with reference to the drawings.
1A and 1B are diagrams showing a first example of a semiconductor element mounting substrate according to the present embodiment, in which FIG. 1A is a cross-sectional view, and FIG. 1B is a plan view showing the shape of a power supply conductor layer. It is. In addition, the same code | symbol is attached | subjected about the same component as the prior art example shown in FIG. 3, and it demonstrates centering on a different part from FIG.
In FIG. 1, a conductor layer (third layer) for the power supply conductor 10 is formed in an upper layer adjacent to the lowermost pad 14, and an opening 20 is formed in this layer. The opening 20 is formed concentrically with the pad 14 and has a larger diameter than the pad 14. An opening having the same diameter as the pad 14 may be used.
A conductor 11 </ b> A is formed in the opening 20 so as to be electrically separated from other conductors and floated. As shown in FIG. 1B, the conductor 11A is formed in an annular shape with the land 9 as the center.

また、本例では、グランド用導体６を設けた導体層（第２層）にも開口部２１が形成され、この開口部２１内にも他の導体と電気的に分離されて浮いた状態の導体５Ａが形成されている。なお、この開口部２１及び導体５は、開口部２０及び導体１１の作用を強化するものであるので、大きさや形状等は任意であるものとする。
以上のような構成により、パッド１４と対向する安定した電位を持つ導体はグランド用導体２となり、パッド部の容量結合を低減する構造となっている。これにより、高周波伝送波形の劣化を抑制する構造となる。 In this example, the opening 21 is also formed in the conductor layer (second layer) provided with the ground conductor 6, and the opening 21 is also electrically separated from other conductors and floated in the opening 21. A conductor 5A is formed. Since the opening 21 and the conductor 5 reinforce the action of the opening 20 and the conductor 11, the size, shape, and the like are arbitrary.
With the above-described configuration, the conductor having a stable potential facing the pad 14 becomes the ground conductor 2 and has a structure that reduces the capacitive coupling of the pad portion. Thereby, it becomes a structure which suppresses degradation of a high frequency transmission waveform.

図２は、本実施の形態による半導体素子搭載用基板の第２実施例を示す図であり、図２（ａ）は断面図、図２（ｂ）は電源用導体層の形状を示す平面図である。なお、図１に示した実施例と共通の構成要素については同一符号を付し、図１と異なる部分を中心に説明する。
本例では導体層に設けた開口部２０、２１内に複数の浮いた状態の導体１１Ｂ、５Ｂを配置したものである。各導体１１Ｂ、５Ｂは、それぞれ円形に形成され、１平方ｃｍ以下の面積を有し、開口部内にほぼ均等に分散配置されている。
このように浮いた状態の導体１１Ｂ、５Ｂを複数分散して配置し、各導体の面積を小さく抑えたことから、第１実施例に比して、さらに安定した特性を得ることが可能となる。 2A and 2B are diagrams showing a second example of the semiconductor element mounting substrate according to the present embodiment, in which FIG. 2A is a cross-sectional view and FIG. 2B is a plan view showing the shape of a power supply conductor layer. It is. In addition, the same code | symbol is attached | subjected about the same component as the Example shown in FIG. 1, and it demonstrates centering on a different part from FIG.
In this example, a plurality of floating conductors 11B and 5B are arranged in openings 20 and 21 provided in the conductor layer. Each of the conductors 11B and 5B is formed in a circular shape, has an area of 1 cm 2 or less, and is substantially uniformly distributed in the opening.
Since the floating conductors 11B and 5B are arranged in a dispersed manner and the area of each conductor is kept small, it is possible to obtain more stable characteristics as compared with the first embodiment. .

図４は本実施例の半導体素子搭載用基板による透過特性（伝送特性）を従来技術及び特許文献１に開示された基板の透過特性と対比して示す説明図であり、横軸に周波数（ＧＨｚ）、縦軸に透過出力レベル（ｄＢ）を示している。
図中の透過特性１６は、上述した第１実施例の半導体素子搭載用基板（図１）をプリント配線基板にＢＧＡ実装した評価基板の透過特性を示している。
また、透過特性１７は、上述した従来技術の半導体素子搭載用基板（図３）をプリント配線基板にＢＧＡ実装した評価基板の透過特性を示しており、透過特性１８は、特許文献１の半導体素子搭載用基板をプリント配線基板にＢＧＡ実装した評価基板の透過特性を示している。なお、それぞれの半導体素子搭載用基板の線路長は１５ｍｍ、プリント配線基板の線路長は１０ｍｍとして設計している。
この図４から分かるように、浮いた状態の導体を設けても、従来技術の半導体素子搭載用基板より伝送特性は大きく改善されており、浮いた状態の導体がない特許文献１の場合とほぼ同等の特性を得ることができる。したがって、特許文献１で説明した開口部の形成に制約を受ける基板においても、本発明を適用することにより、十分な特性の改善を実現でき、幅広い基板に適用できる点で本発明は優位性を有する。 FIG. 4 is an explanatory diagram showing the transmission characteristics (transmission characteristics) of the substrate for mounting a semiconductor element according to the present embodiment in comparison with the transmission characteristics of the substrate disclosed in the prior art and Patent Document 1, and the horizontal axis indicates the frequency (GHz). ), And the vertical axis represents the transmission output level (dB).
The transmission characteristic 16 in the figure shows the transmission characteristic of the evaluation board in which the above-described semiconductor element mounting board (FIG. 1) of the first embodiment is mounted on a printed wiring board by BGA.
Further, the transmission characteristic 17 indicates the transmission characteristic of the evaluation substrate in which the above-described conventional semiconductor element mounting substrate (FIG. 3) is mounted on the printed wiring board by BGA. The transmission characteristic 18 indicates the semiconductor element of Patent Document 1. The transmission characteristic of the evaluation board | substrate which mounted the board | substrate for mounting on the printed wiring board by BGA is shown. Each semiconductor element mounting board is designed to have a line length of 15 mm, and a printed wiring board has a line length of 10 mm.
As can be seen from FIG. 4, even when a floating conductor is provided, the transmission characteristics are greatly improved over the conventional semiconductor element mounting substrate, which is almost the same as in Patent Document 1 where there is no floating conductor. Equivalent characteristics can be obtained. Therefore, even in a substrate that is restricted by the formation of the opening described in Patent Document 1, by applying the present invention, sufficient characteristics can be improved, and the present invention is advantageous in that it can be applied to a wide range of substrates. Have.

本発明の実施の形態による半導体素子搭載用基板の第１実施例を示す図であり、図１（ａ）は断面図、図１（ｂ）は電源用導体層の形状を示す平面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows 1st Example of the board | substrate for semiconductor element mounting by embodiment of this invention, FIG. 1 (a) is sectional drawing, FIG.1 (b) is a top view which shows the shape of the conductor layer for power supplies. . 本発明の実施の形態による半導体素子搭載用基板の第２実施例を示す図であり、図２（ａ）は断面図、図２（ｂ）は電源用導体層の形状を示す平面図である。It is a figure which shows 2nd Example of the board | substrate for semiconductor element mounting by embodiment of this invention, Fig.2 (a) is sectional drawing, FIG.2 (b) is a top view which shows the shape of the conductor layer for power supplies. . 従来技術による半導体素子搭載用基板の例を示す図であり、図３（ａ）は断面図、図３（ｂ）は電源用導体層の形状を示す平面図である。It is a figure which shows the example of the board | substrate for semiconductor element mounting by a prior art, FIG. 3 (a) is sectional drawing, FIG.3 (b) is a top view which shows the shape of the conductor layer for power supplies. 本発明の実施例の半導体素子搭載用基板による透過特性を従来技術及び特許文献１に開示された基板の透過特性と対比して示す説明図である。It is explanatory drawing which shows the permeation | transmission characteristic by the board | substrate for semiconductor element mounting of the Example of this invention compared with the permeation | transmission characteristic of the board | substrate disclosed by the prior art and patent document 1. FIG.

符号の説明Explanation of symbols

１、１５……ソルダーレジスト、２、６……グランド用導体、３、７、１２……絶縁材、４……信号用導体、５Ａ、５Ｂ、１１Ａ、１１Ｂ……他の導体と電気的に接続されていない導体、８、１３……信号用ビア、９……信号用ランド、１０……電源用導体、１４……パッド、２０、２１……開口部。
1, 15 ... Solder resist, 2, 6 ... Ground conductor, 3, 7, 12 ... Insulating material, 4 ... Signal conductor, 5A, 5B, 11A, 11B ... Electrically with other conductors Unconnected conductor, 8, 13... Signal via, 9... Signal land, 10 .. power supply conductor, 14... Pad, 20, 21.

Claims (5)

一方の面に半導体素子を搭載し、他方の面に外部回路基板との接続用に設けられたパッドと、前記パッドに隣接して配置される内部導体層とを有した半導体素子搭載用基板であって、
前記内部導体層は前記パッドと対向する部分に開口部を有し、
前記パッドの径Ｗｐと、前記開口部の径Ｗｋとが、Ｗｋ≧Ｗｐの関係を有し、さらに、前記内部導体層の開口部内に他の導体と電気的に分離されて浮いた状態の導体が形成されている、
ことを特徴とする半導体素子搭載用基板。 A semiconductor element mounting substrate having a semiconductor element mounted on one surface, a pad provided for connection to an external circuit board on the other surface, and an internal conductor layer disposed adjacent to the pad. There,
The inner conductor layer has an opening in a portion facing the pad;
A conductor in a state where the pad diameter Wp and the opening diameter Wk have a relationship of Wk ≧ Wp, and are electrically separated from other conductors and floated in the opening of the inner conductor layer Is formed,
A substrate for mounting a semiconductor element. 前記内部導体層の開口部に形成された浮いた状態の導体が複数設けられていることを特徴とする請求項１記載の半導体素子搭載用基板。   2. The semiconductor element mounting substrate according to claim 1, wherein a plurality of floating conductors formed in the openings of the inner conductor layer are provided. 前記内部導体層の開口部に形成された浮いた状態の導体１つの面積は１平方ｃｍ以下であることを特徴とする請求項１または２記載の半導体素子搭載用基板。   3. The semiconductor element mounting substrate according to claim 1, wherein an area of one floating conductor formed in the opening of the inner conductor layer is 1 cm 2 or less. 前記パッドに隣接して配置される複数層の内部導体層のパッドと対向する部分に開口部を有し、各開口部に他の導体と電気的に分離されて浮いた状態の導体が形成されていることを特徴とする請求項１〜３のいずれか１項記載の半導体素子搭載用基板。   A plurality of inner conductor layers disposed adjacent to the pads have openings in portions facing the pads, and a floating conductor is formed in each opening that is electrically separated from other conductors. The substrate for mounting a semiconductor element according to claim 1, wherein the substrate for mounting a semiconductor element is provided. 前記半導体素子には高周波伝送用の半導体素子を含むことを特徴とする請求項１〜４のいずれか１項記載の半導体素子搭載用基板。
The semiconductor element mounting substrate according to claim 1, wherein the semiconductor element includes a semiconductor element for high-frequency transmission.
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