JP2007220948A5 - - Google Patents
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- JP2007220948A5 JP2007220948A5 JP2006040687A JP2006040687A JP2007220948A5 JP 2007220948 A5 JP2007220948 A5 JP 2007220948A5 JP 2006040687 A JP2006040687 A JP 2006040687A JP 2006040687 A JP2006040687 A JP 2006040687A JP 2007220948 A5 JP2007220948 A5 JP 2007220948A5
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- Prior art keywords
- region
- film
- insulating film
- forming
- thin film
- Prior art date
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- 239000010408 film Substances 0.000 claims 61
- 239000010409 thin film Substances 0.000 claims 23
- 239000000758 substrate Substances 0.000 claims 21
- 239000004065 semiconductor Substances 0.000 claims 14
- 238000000034 method Methods 0.000 claims 13
- 239000002184 metal Substances 0.000 claims 12
- 238000002425 crystallisation Methods 0.000 claims 11
- 230000008025 crystallization Effects 0.000 claims 11
- 230000015572 biosynthetic process Effects 0.000 claims 5
- 239000013078 crystal Substances 0.000 claims 5
- 230000001678 irradiating effect Effects 0.000 claims 4
- 238000000151 deposition Methods 0.000 claims 3
- 238000005530 etching Methods 0.000 claims 3
- 238000010438 heat treatment Methods 0.000 claims 3
- 229910021332 silicide Inorganic materials 0.000 claims 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 239000011521 glass Substances 0.000 claims 1
- 239000011159 matrix material Substances 0.000 claims 1
- 230000003287 optical effect Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 239000010453 quartz Substances 0.000 claims 1
- 230000003252 repetitive effect Effects 0.000 claims 1
Claims (15)
絶縁基板上に逐次下地絶縁膜、半導体膜、そしてキャップ絶縁膜を含む膜構造を形成し、
所定の光強度分布を有するレーザ光を前記膜構造に照射することにより、前記半導体膜を結晶化し、
薄膜トランジスタにおけるチャネル形成領域上のキャップ絶縁膜を残すように、前記チャネル形成領域周囲のキャップ絶縁膜をエッチングして除去し、
前記エッチングした基板全面に金属膜を堆積し、
熱処理を施して前記キャップ絶縁膜が除去された領域の前記半導体膜と前記金属膜を反応させて金属シリサイド層を形成し、
前記キャップ絶縁膜上の未反応の前記金属膜を除去し、
前記チャネル形成領域上の前記キャップ絶縁膜を除去する工程を含む、
薄膜トランジスタを形成する方法。 A method of forming a thin film transistor on an insulating substrate, wherein a film structure including a base insulating film, a semiconductor film, and a cap insulating film is sequentially formed on the insulating substrate,
By irradiating the film structure with laser light having a predetermined light intensity distribution, the semiconductor film is crystallized,
Etching and removing the cap insulating film around the channel forming region so as to leave a cap insulating film on the channel forming region in the thin film transistor,
Depositing a metal film on the entire surface of the etched substrate;
A metal silicide layer is formed by reacting the semiconductor film and the metal film in a region where the cap insulating film is removed by heat treatment,
Removing the unreacted metal film on the cap insulating film;
Removing the cap insulating film on the channel formation region;
A method of forming a thin film transistor.
請求項１記載の薄膜トランジスタを形成する方法。 The method for forming a thin film transistor according to claim 1, further comprising the step of separating the channel formation region into island regions of individual transistors.
前記チャネル形成予定領域内の前記ゲート絶縁膜上にゲート電極パターンを形成する工程を含む、
請求項２記載の薄膜トランジスタを形成する方法。 Forming the gate insulating film on the island region of the transistor;
Forming a gate electrode pattern on the gate insulating film in the channel formation scheduled region,
A method for forming a thin film transistor according to claim 2.
請求項１乃至３の何れか１項記載の薄膜トランジスタを形成する方法。 4. The method of forming a thin film transistor according to claim 1, wherein the insulating substrate is a glass substrate or a quartz substrate.
請求項１乃至３の何れか１項記載の薄膜トランジスタを形成する方法。 4. The method for forming a thin film transistor according to claim 1, wherein the base insulating film is a silicon oxide film.
請求項１乃至３の何れか１項記載の薄膜トランジスタを形成する方法。 4. The method of forming a thin film transistor according to claim 1, wherein the semiconductor film is an amorphous or polycrystalline silicon film.
請求項１乃至３の何れか１項記載の薄膜トランジスタを形成する方法。 4. The method of forming a thin film transistor according to claim 1, wherein the cap insulating film is a silicon oxide film.
絶縁基板上に逐次下地絶縁膜、半導体膜、そしてキャップ絶縁膜を含む膜構造を形成し、
所定の光強度分布を有するレーザ光を前記膜構造に照射することにより、前記半導体膜に前記基板に対し傾斜した結晶化領域を生成し、
薄膜トランジスタにおけるチャネル形成領域上のキャップ絶縁膜を残すように、前記チャネル形成領域周囲のキャップ絶縁膜をエッチングして除去し、
前記エッチングした基板全面に金属膜を堆積し、
熱処理を施して前記キャップ絶縁膜が除去された領域の前記半導体膜と前記金属膜を反応させて金属シリサイド層を形成し、
前記キャップ絶縁膜上の未反応の前記金属膜を除去し、
前記チャネル形成領域上の前記キャップ絶縁膜を除去する工程を含む、
薄膜トランジスタを形成する方法。 A method of forming a thin film transistor on an insulating substrate, wherein a film structure including a base insulating film, a semiconductor film, and a cap insulating film is sequentially formed on the insulating substrate,
By irradiating the film structure with laser light having a predetermined light intensity distribution, a crystallized region inclined with respect to the substrate is generated in the semiconductor film,
Etching and removing the cap insulating film around the channel forming region so as to leave a cap insulating film on the channel forming region in the thin film transistor,
Depositing a metal film on the entire surface of the etched substrate;
A metal silicide layer is formed by reacting the semiconductor film and the metal film in a region where the cap insulating film is removed by heat treatment,
Removing the unreacted metal film on the cap insulating film;
Removing the cap insulating film on the channel formation region;
A method of forming a thin film transistor.
前記チャネル領域は前記基板に対して傾斜した結晶化領域に設けられていることを特徴とする薄膜トランジスタ。 A thin film transistor having a source region, a channel region, and a drain region in a semiconductor thin film having a crystallization region grown so as to be inclined with respect to a substrate, and having a gate insulating film and a gate electrode on the channel region. And
The thin film transistor, wherein the channel region is provided in a crystallization region inclined with respect to the substrate.
絶縁基板上に逐次下地絶縁膜、半導体膜、そしてキャップ絶縁膜を含む膜構造を形成し、
所定の光強度分布を有するレーザ光を前記膜構造に照射することにより、前記半導体膜の所定の結晶成長の開始位置より前記基板に対して横方向に結晶成長させた結晶化領域を生成し、
前記薄膜トランジスタのチャネル形成領域上のキャップ絶縁膜を残すように、前記チャネル形成領域周囲のキャップ絶縁膜をエッチングして除去し、
前記エッチングした基板全面に金属膜を堆積し、
熱処理を施して前記キャップ絶縁膜が除去された領域の前記半導体膜と前記金属膜を反応させて金属シリサイド層を形成し、
前記キャップ絶縁膜上の未反応の前記金属膜を除去し、
前記チャネル形成領域上の前記キャップ絶縁膜を除去する工程を含む、
薄膜トランジスタを形成する方法。 A method of forming a thin film transistor on an insulating substrate, wherein a film structure including a base insulating film, a semiconductor film, and a cap insulating film is sequentially formed on the insulating substrate,
By irradiating the film structure with laser light having a predetermined light intensity distribution, a crystallized region in which crystal growth is performed in a lateral direction with respect to the substrate from a start position of predetermined crystal growth of the semiconductor film is generated,
Etching and removing the cap insulating film around the channel forming region so as to leave a cap insulating film on the channel forming region of the thin film transistor;
Depositing a metal film on the entire surface of the etched substrate;
A metal silicide layer is formed by reacting the semiconductor film and the metal film in a region where the cap insulating film is removed by heat treatment,
Removing the unreacted metal film on the cap insulating film;
Removing the cap insulating film on the channel formation region;
A method of forming a thin film transistor.
前記ドレイン領域又は前記ソース領域の前記チャネル領域側端部は結晶成長の開始位置を除く結晶化領域に設けられていることを特徴とする薄膜トランジスタ。 A thin film transistor having a source region, a channel region, and a drain region in a semiconductor thin film having a crystallization region laterally grown from a predetermined crystal growth start position, and having a gate insulating film and a gate electrode above the channel region Because
A thin film transistor, wherein an end of the drain region or the source region on the channel region side is provided in a crystallization region excluding a crystal growth start position.
レーザ光を発生するレーザ源と、
膜構造を有する前記絶縁基板が載置されるステージと、
前記ステージと前記レーザ光源との間に設けられ、入射角度および光強度に関して前記レーザ光を均一化するホモジナイザと、
前記ホモジナイザと前記ステージとの間に設けられ、前記ホモジナイザで均一化されたレーザ光を位相変調して、鋸歯状の繰り返しパターンの光強度分布を形成するする位相変調光学系と、
を具備することを特徴とする結晶化装置。 A crystallization apparatus for crystallizing the semiconductor film by irradiating a laser beam onto a film structure including a base insulating film, a semiconductor film, and a cap insulating film sequentially formed on an insulating substrate,
A laser source for generating laser light;
A stage on which the insulating substrate having a film structure is placed;
A homogenizer provided between the stage and the laser light source, and homogenizing the laser light with respect to an incident angle and light intensity;
A phase modulation optical system that is provided between the homogenizer and the stage and phase-modulates the laser light uniformized by the homogenizer to form a light intensity distribution of a sawtooth repetitive pattern;
A crystallization apparatus comprising:
この絶縁基板上に設けられた横方向に結晶成長された結晶粒からなる長方形状結晶化領域と、A rectangular crystallization region made of crystal grains grown in the lateral direction provided on the insulating substrate;
この長方形状結晶化領域内の短辺方向に離間して設けられたソース領域およびドレイン領域を有するＰＭＯＳトランジスタと、A PMOS transistor having a source region and a drain region spaced apart in the short side direction in the rectangular crystallization region;
前記長方形状結晶化領域内であって前記ＰＭＯＳトランジスタと長辺方向に離間した位置に設けられ、且つ前記短辺方向に離間して設けられたソース領域およびドレイン領域を有するＮＭＯＳトランジスタと、An NMOS transistor having a source region and a drain region provided in the rectangular crystallization region at positions spaced apart from the PMOS transistor in the long side direction and spaced apart in the short side direction;
前記ＰＭＯＳトランジスタ又はＮＭＯＳトランジスタのソース領域又はドレイン領域に接続され前記短辺方向に長く設けられた電源配線と、 A power supply line connected to the source region or drain region of the PMOS transistor or NMOS transistor and provided long in the short side direction;
前記NＭＯＳトランジスタ又はPＭＯＳトランジスタのドレイン領域又はソース領域に接続され前記電源配線と離隔して前記短辺方向に長く設けられた接地配線と、 A ground wiring that is connected to a drain region or a source region of the NMOS transistor or the PMOS transistor and is provided long in the short side direction and separated from the power supply wiring;
前記長方形状結晶化領域の長辺方向に長く設けられた前記ＰＭＯＳトランジスタのゲート電極および前記ＮＭＯＳトランジスタのゲート電極とA gate electrode of the PMOS transistor and a gate electrode of the NMOS transistor provided long in the long side direction of the rectangular crystallization region;
を具備してなることを特徴とするＣＭＯＳインバータ回路。A CMOS inverter circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006040687A JP2007220948A (en) | 2006-02-17 | 2006-02-17 | Thin-film semiconductor device, and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006040687A JP2007220948A (en) | 2006-02-17 | 2006-02-17 | Thin-film semiconductor device, and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007220948A JP2007220948A (en) | 2007-08-30 |
| JP2007220948A5 true JP2007220948A5 (en) | 2008-03-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006040687A Abandoned JP2007220948A (en) | 2006-02-17 | 2006-02-17 | Thin-film semiconductor device, and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2007220948A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5305696B2 (en) | 2008-03-06 | 2013-10-02 | キヤノン株式会社 | Semiconductor device processing method |
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2006
- 2006-02-17 JP JP2006040687A patent/JP2007220948A/en not_active Abandoned
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