JP2007219968A - Bus interface wrapper circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a circuit scale of a bus interface wrapper circuit by allowing an AHB-Lite master to be built in an AHB bus system in the same manner as an AHB master without providing local arbiters per AHB slave. <P>SOLUTION: A wrapper circuit 1-1 is added to an AHB-Lite master 4-5. The wrapper circuit 1-1 sends a signal showing a state of being not capable of receiving data, to the AHB-Lite master when receiving a data transfer request from the AHB-Lite master and temporarily holds transfer data, and during this period, the wrapper circuit issues an access request signal to an arbiter 2-4 and transfers data to an AHB slave 4-4 through a selector 4-3 in response to reception of an access permission signal. The wrapper circuit ceases to issue the access request signal to the arbiter and transmits a data transfer completion signal to the AHB-Lite master, in response to reception of a data transfer completion signal from the AHB slave. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface wrapper circuit, and in particular, an open standard on-chip bus specification that stipulates the interconnection of functional blocks constituting an ARM (Advanced RISC Machines) system on chip (SoC) and the management method thereof. The present invention relates to a bus interface wrapper circuit used in an apparatus using an advanced high performance bus (AHB) and an advanced high performance bus-write (AHB-Lite) in the AMBA (Advanced Microcontroller Bus Architecture) standard.

  The Advanced High Performance Bus (AHB) is a high-speed, high-bandwidth bus that connects embedded processors such as ARM (Advanced RISC Machines) cores to high-performance peripherals, DMA controllers, on-chip memory, and various interfaces. This bus supports multi-master bus management that maximizes system performance and enables high-speed access to memory and peripherals through pipeline processing and burst transfer.

  On the other hand, the Advanced High Performance Bus-Write (AHB-Lite) is a subset of the Advanced High Performance Bus (AHB) full specification, and there is only a simple single bus master system or one AHB master on the layer. This is a bus used for a system that uses only one bus master, such as a multi-layer AHB system.

  In the following description, the advanced high performance bus (AHB) is simply referred to as AHB, and the advanced high performance bus-write (AHB-Lite) is simply referred to as AHB-Lite. A bus master and a bus slave of the AHB interface are referred to as an AHB master and an AHB slave, and a bus master of the AHB-Lite interface is referred to as an AHB-Lite master.

  The AHB master has a function of preparing an address and control information and starting a read operation or a write operation through the bus. However, only one AHB master can actually use the bus at each time point on the time axis. The AHB slave has a function of responding to a read operation or a write operation in a given address space by the AHB master and returning success, failure or wait (wait request) of data transfer as a response signal.

  FIG. 4 shows a configuration example of a bus system using AHB and AHB-Lite. As shown in the figure, the AHB master 4-1 includes a plurality of AHB masters (# 1, # 2) via a selector 4-3, and a plurality of AHB slaves 4-4 (# 1, # 2, # 3). ) Can be transferred to and from. However, between the plurality of AHB masters 4-1 (# 1, # 2), arbitration of the bus use right is performed by the arbiter 4-2, and only one AHB master that has acquired the bus use right uses the bus. be able to.

  The arbiter 4-2 in the AHB can be changed to an arbitration algorithm such as the highest priority (high priority) or the same priority (fair) access even when the arbitration protocol (control procedure) is predetermined. There is an arbitration protocol that can be changed and executed each time an application requests it.

  The AHB-Lite is an interface that is almost the same as the AHB, but the AHB-Lite is an interface on the premise that a single bus master is used instead of a plurality of bus masters. -1 (# 1, # 2) and a plurality of AHB slaves 4-4 (# 1, # 2, # 3) can be directly connected to the AHB-Lite master As shown in FIG. 4, the AHB-Lite master 4-5 communicates with the AHB slave 4-4 (# 3) via the local arbiter 4-6 that arbitrates the bus use contention between the AHB and the AHB-Lite. Data transfer needs to be performed.

  As prior art documents related to the present invention, the following Patent Document 1 includes an AMBA bus, an AHB-lite memory system (using a plurality of private slaves at the core level), a full AHB memory system (a plurality of masters at the core level). Is used).

  In Patent Document 2 below, in a design using IP (Intellectual Property), it is possible to operate normally even when a signal line from a master module outside PLATFORM to a slave module inside PLATFORM is excluded. A bus configuration circuit is described.

Further, in Patent Document 3 below, all the bus masters that have requested to use the bus operate as if they have obtained the right to use the bus, and by acquiring the drive information necessary for slave access, the optimized access can be achieved. The bus system and the like that have been arbitrated to improve the slave access bandwidth are described.
JP 2005-25726 A (paragraph 0058 etc.) Japanese Patent Laying-Open No. 2005-100210 (a column of problems to be solved by the invention) JP 2004-348745 A (front page, etc.)

  When the AHB-Lite master is incorporated into an AHB bus system having a plurality of AHB masters by using the master circuit of the AHB-Lite interface, as described above, the AHB-Lite uses one bus master. Since the interface is based on the premise, the AHB-Lite master cannot be directly connected to the AHB bus system.

  Even if AHB-Lite is added as a master, a local arbiter that serves to adjust bus access between bus access requests from other AHB masters and bus access requests from AHB-Lite masters ( Interconnect Matrix) must be provided for each AHB slave, and the configuration and scale are complicated and large.

  The present invention makes it possible to incorporate an AHB-Lite master into an AHB bus system in the same way as an AHB master without providing a local arbiter (Interconnect Matrix) for each AHB slave. The purpose is to simplify.

  The bus interface wrapper circuit of the present invention will be described with reference to FIG. 2. When a data transfer request (2-1) from a bus master is received, the data from the bus master is held and data cannot be received by the bus master. A means for transmitting (2-2) a signal indicating the status of the bus, and transmitting (2-3) a signal requesting bus access to an arbiter that arbitrates bus use rights among a plurality of bus masters, and the arbiter Means for sending (2-5) the held data to a selector for selecting connections between a plurality of bus masters and a plurality of bus slaves when receiving a signal permitting bus access from (2-4). , Provided.

  When a signal indicating completion of data transfer is received from the bus slave through the selector (2-6), a signal indicating no bus access request is transmitted to the arbiter (2-7), and And a means for transmitting (2-8) a signal indicating completion of data transfer to the bus master.

  The bus interface wrapper circuit of the present invention will be described with reference to FIG. 3. When a transfer type signal (HTRANS) indicating a data transfer request is input from the bus master, the bus master is in a state in which data reception is not possible. A trigger unit 3-1 having means for sending a signal (HREADY) indicating that there is a signal and sending a signal (HREQUEST) requesting bus access to the arbiter, and a trigger signal from the trigger unit 3-1, A transfer type signal indicating that data transfer is not requested to a selector that selects connection between a plurality of bus masters and a plurality of bus slaves while latching and holding data (HWDATA or the like) from the bus master. HTRANS) and an access permission signal (HGRANT) from the arbiter A latch unit 3-2 having a transfer type signal (HTRANS) indicating whether the data is continuous transfer data or non-continuous transfer data and the held data (HWDATA, etc.) to the selector when received. It is provided with.

  Further, when the trigger unit 3-1 receives a signal (HREADY) indicating completion of data transfer from the bus slave through the selector, the trigger unit 3-1 outputs a signal (HREQUEST) indicating that there is no bus access request to the arbiter. And a means for transmitting a signal (HREADY) indicating completion of data transfer to the bus master.

  The bus master has a bus interface to which a single bus master is connected in accordance with the advanced high-performance bus-write (AHB-Lite) standard in AMBA (Advanced Microcontroller Bus Architecture). The bus slave is characterized by having a bus interface to which a plurality of bus masters are connected in accordance with the advanced high-performance bus (AHB) standard in AMBA (Advanced Microcontroller Bus Architecture).

  By adding the bus interface wrapper circuit of the present invention to the AHB-Lite master, the AHB-Lite master can be incorporated into the AHB bus system in the same manner as the AHB master, and a local arbiter (Interconnect Matrix) is connected to each AHB. Since it is not necessary to provide the slave, the circuit scale is reduced, the configuration is simplified, and the cost can be reduced.

  In addition, since a local arbiter (Interconnect Matrix) is not used, a relay procedure in data transfer is omitted, bus use efficiency is improved, and bus access requests from more complicated AHB masters and AHB-Lite masters are processed smoothly. It becomes possible. In addition, since the main bus can be shared by the AHB master and the AHB-Lite master, the circuit configuration is simplified and the performance can be improved.

  FIG. 1 shows a configuration example of a bus system using AHB and AHB-Lite according to the present invention. In the figure, an AHB master 4-1 supports a data transfer function of an AHB bus according to a normal AMBA standard, and a plurality of bus masters 4-1 (# 1, # 2) pass through a selector 4-3 to Data can be transferred to and from the AHB slave 4-4 (# 1, # 2, # 3).

  The arbiter 4-2 arbitrates a bus access request from each bus master and controls the bus. The selector 4-3 is a functional unit that performs switching of bus connections and the like in accordance with a control signal from the arbiter 4-2. The AHB slave 4-4 is a functional unit that performs data transfer in accordance with an access request from each bus master. The AHB-Lite master 4-5 is a bus master, but can only be a bus master.

  The wrapper (WRAPPER) circuit 1-1 is a block that generates signals (mainly, an HG Grant signal indicating bus use permission and an HRequest signal indicating a bus use request) necessary for connection to the arbiter 4-2. The AHB-Lite bus interface includes an HRequest signal for requesting the AHB bus usage right to the AHB arbiter 4-2, and an HG grant signal transmitted from the AHB arbiter 4-2 when the AHB bus usage right is granted. Is not complemented by the wrapper circuit 1-1.

  The AHB slave 4-4 is an AHB slave circuit according to the normal AMBA standard, and performs an AHB response in accordance with a signal from the bus master that has acquired the bus use right by arbitration by the arbiter 4-2, and performs data transfer with the bus master. .

  FIG. 2 shows an access procedure from the AHB-Lite master 4-5 to the AHB slave 4-4 according to the present invention. The AHB-Lite master 4-5 issues an HTrans signal indicating a transfer type to the AHB slave 4-4 to make a data transfer request (2-1). The wrapper circuit 1-1 that has received the HTrans signal outputs a signal of “HReady = 0” indicating that the AHB slave 4-4 is processing and cannot receive data (Busy state), and the AHB-Lite master 4- 5 is transmitted in a pseudo manner (2-2). Thereby, the AHB interface is concealed from the AHB-Lite master 4-5, and the AHB-Lite interface is assumed.

  At this time, the wrapper circuit 1-1 temporarily holds a data signal, an address signal, and the like related to the transfer from the AHB-Lite master 4-5. This is to enable immediate switching to the next data transfer when accessing the continuous data transfer from the AHB-Lite master 4-5.

  On the other hand, the wrapper circuit 1-1 requests the arbiter 4-2 to provide an access permission (HGrant) signal to the AHB slave 4-4 connected to the main bus (AHB). An (HRequest) signal is issued (2-3).

  The arbiter 4-2 that has received the access request (HRequest) signal arbitrates the bus use right with the access request from the other AHB master 4-1, and grants permission for the access from the wrapper circuit 1-1. Sometimes, an access permission (HG Grant) signal is sent to the wrapper circuit 1-1 (2-4).

  Receiving the access permission (HG Grant) signal, the wrapper circuit 1-1 recognizes that access to the main bus (AHB) is permitted, and transfers it to the AHB slave 4-4 as the transfer partner through the selector 4-3. The data transfer is performed together with the transmission of the HTrans signal indicating the type (2-5). Then, the AHB slave 4-4 returns a signal of “HReady = 1” indicating that the data transfer is completed (2-6).

  When the wrapper circuit 1-1 receives the “HReady = 1” signal from the AHB slave 4-4, it cancels the issuance of the access request (HRequest) signal to notify the arbiter 4-2 of the end of access. (2-7). At the same time, a signal “HReady = 1” indicating that the data transfer is completed is transmitted to the AHB-Lite master 4-5 (2-8). As a result, the AHB-Lite master 4-5 can receive the AHB response from the AHB slave 4-4 regardless of the existence of other AHB masters, as in the prior art.

  FIG. 3 shows the configuration of the wrapper circuit 1-1. The wrapper circuit 1-1 includes a trigger unit 3-1, and a latch unit 3-2. In the trigger unit 3-1, an access request signal from the AHB-Lite master 4-5 and an instruction signal from the arbiter 4-2. And a trigger signal is sent to the latch unit 3-2 for transferring actual bus data.

  When the first trigger signal (Trigger = 1 (pulse)) is input from the trigger unit 3-1, the latch unit 3-2 latches and holds data from the AHB-Lite master 4-5. At this time, a transfer type signal “HTrans = 00” indicating that data transfer is not requested (idle state) is transmitted to the selector 4-3.

  When the latch unit 3-2 receives the access permission signal “HG Grant = 1” from the arbiter 4-2, the latch unit 3-2 sends to the selector 4-3 a transfer type signal “HTrans = 10 or 11 "and the previously stored data are sent out. After that, when the trigger signal (Trigger = 1) is input again by the response from the AHB slave 4-4, the data from the AHB-Lite master 4-5 is output and the output of the write data (HWdata) is started. To do.

  In the wait state, the trigger unit 3-1 indicates a signal “HReady = 1” indicating data transfer completion from the selector and a transfer type indicating that data transfer is not requested (idle state) from the AHB-Lite master 4-5. A signal “HTrans = 00” is input, and at this time, a signal “HReady = 1” indicating the completion of data transfer is sent to the AHB-Lite master 4-5, indicating that there is no access request to the arbiter 4-2. A signal “HRequest = 0” is transmitted.

  In addition, when the data transfer request is sent from the AHB-Lite master 4-5, the trigger unit 3-1 receives a transfer type signal “HTrans = 10 or 11” indicating whether the data is continuous transfer data or non-continuous transfer data. At this time, “HReady = 0” indicating that data reception is not possible (Busy state) is sent to the AHB-Lite master 4-5, and to the arbiter 4-2. On the other hand, a signal “HRequest = 1” indicating that there is an access request is sent, and a trigger signal (Trigger = 1 (pulse)) is output to the latch unit 3-2.

  When a signal “HG Grant = 1” indicating access permission is received from the arbiter 4-2, data transfer is started from the latch unit 3-2. When the data transfer is completed, a signal “HReady = 1” indicating completion of the data transfer is input from the selector 4-3 to the trigger unit 3-1. As a result, the trigger unit 3-1 receives the AHB-Lite master 4-5. In response to this, a signal “HReady = 1” indicating completion of data transfer is transmitted, and a signal “HRequest = 0” indicating that there is no access request is transmitted to the arbiter 4-2, and the latch unit 3-2. A trigger signal (Trigger = 1) for performing post-processing on is output.

It is a figure which shows the structural example of the bus system using AHB and AHB-Lite by this invention. It is a figure which shows the access procedure from the AHB-Lite master by this invention to an AHB slave. It is a figure which shows the structure of the wrapper circuit by this invention. It is a figure which shows the structural example of the bus system using AHB and AHB-Lite.

Explanation of symbols

1-1 Wrapper circuit 3-1 Trigger section 3-2 Latch section 4-1 AHB master 4-2 Arbiter 4-3 Selector 4-4 AHB slave 4-5 AHB-Lite master 4-6 Local arbiter

Claims (5)

When receiving a data transfer request from a bus master, the arbiter holds data from the bus master, sends a signal indicating that data cannot be received to the bus master, and arbitrates the bus use right among a plurality of bus masters. A means for transmitting a signal requesting bus access;
Means for sending the held data to a selector that selects connections between a plurality of bus masters and a plurality of bus slaves when receiving a signal permitting bus access from the arbiter;
A bus interface wrapper circuit comprising:   When a signal indicating completion of data transfer is received from the bus slave through the selector, a signal indicating that there is no bus access request is transmitted to the arbiter, and data transfer completion is indicated to the bus master. The bus interface wrapper circuit according to claim 1, further comprising means for transmitting a signal. When a transfer type signal indicating a data transfer request is input from the bus master, a signal indicating that data reception is not possible is sent to the bus master, and a signal requesting bus access to the arbiter A trigger unit having means for delivering;
The trigger signal from the trigger unit latches and holds data from the bus master, and data transfer is not requested to a selector that selects connections between a plurality of bus masters and a plurality of bus slaves. Means for transmitting a transfer type signal indicating;
A latch unit having a transfer type signal indicating whether it is continuous transfer data or non-continuous transfer data and means for sending the held data to the selector when an access permission signal is received from the arbiter;
A bus interface wrapper circuit comprising:   When the trigger unit receives a signal indicating the completion of data transfer from the bus slave through the selector, the trigger unit transmits a signal indicating no bus access request to the arbiter, and the bus master, 4. The bus interface wrapper circuit according to claim 3, further comprising means for transmitting a signal indicating completion of data transfer.   The bus master has a bus interface to which a single bus master conforms to the advanced high performance bus-write (AHB-Lite) standard in AMBA (Advanced Microcontroller Bus Architecture), and the arbiter and the bus slave 5. The system according to claim 1, further comprising: a bus interface to which a plurality of bus masters are connected in accordance with an advanced high-performance bus (AHB) standard in an AMBA (Advanced Microcontroller Bus Architecture). Bus interface wrapper circuit.

Images