JP2007214519A - Metal-coated polyimide substrate and tin plating method using the same - Google Patents

Metal-coated polyimide substrate and tin plating method using the same Download PDF

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JP2007214519A
JP2007214519A JP2006035854A JP2006035854A JP2007214519A JP 2007214519 A JP2007214519 A JP 2007214519A JP 2006035854 A JP2006035854 A JP 2006035854A JP 2006035854 A JP2006035854 A JP 2006035854A JP 2007214519 A JP2007214519 A JP 2007214519A
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plating
copper
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copper plating
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Shuichi Ogasawara
修一 小笠原
Tomomichi Nihei
知倫 二瓶
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Sumitomo Metal Mining Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a metal-coated polyimide substrate, capable of providing COF for which peeling is not caused by a heat history for hardening a sealing resin, without forming a heterogeneous metal layer of nickel or the like on a copper plated surface, by controlling the layer thickness near final plating, to an appropriate thickness in the copper plating coating of a laminated structure formed into a desired thickness, by continuously executing plating. <P>SOLUTION: For the metal-coated polyimide substrate, the copper plating coating is executed by a plurality of electrolytic cells on the surface of a metal layer formed on a polyimide film surface by a sputtering method, and tin plating coating is executed on the surface of the copper plating coating. When tin plating of a film thickness (t) is applied to the surface of the copper plating coating, electric copper plating is applied by the same electrolytic cell to an area from the copper plating surface layer, to at least a depth 3t. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、例えば液晶画面駆動用半導体を実装するための半導体実装用金属被覆ポリイミド基板と、この基板を用いて得られる電子回路への錫めっき法に関する。   The present invention relates to a metal-coated polyimide substrate for mounting a semiconductor for mounting a semiconductor for driving a liquid crystal screen, for example, and a tin plating method for an electronic circuit obtained using the substrate.

液晶画面表示用ドライバーICチップを実装する手法としてCOF(Chip on Film)が注目されている。COFは従来の実装法であったTCP(Tape Carrier Package)に比べ、ファインピッチ実装が可能であり、ドライバーICの小型化、コストダウンをはかることが容易な実装法である。COFは高耐熱、高絶縁性樹脂であるポリイミドフィルムと良導電体である銅層を密着させてなる金属被覆ポリイミド基板を使用し、銅層をフォトリソグラフィー技法によってファインパターニングし、さらに所望な箇所に錫めっきおよびソルダーレジストを被覆して得るのが一般的である。上記金属被覆ポリイミド基板に用いられるポリイミドフィルムとしては、Kapton EN(東レ・デュポン製)、Upilex(宇部興産製)、NPI(カネカ製)等が用いられ、その厚みは25〜38μmが一般的である。   COF (Chip on Film) attracts attention as a technique for mounting a driver IC chip for liquid crystal display. COF is a mounting method that allows fine pitch mounting compared to TCP (Tape Carrier Package), which is a conventional mounting method, and makes it easy to reduce the size and cost of the driver IC. COF uses a metal-coated polyimide substrate in which a polyimide film, which is a highly heat-resistant and highly insulating resin, and a copper layer, which is a good conductor, are in close contact, and the copper layer is finely patterned by a photolithography technique. Generally, it is obtained by coating with tin plating and solder resist. As the polyimide film used for the metal-coated polyimide substrate, Kapton EN (manufactured by Toray DuPont), Upilex (manufactured by Ube Industries), NPI (manufactured by Kaneka), etc. are used, and the thickness is generally 25 to 38 μm. .

また、ポリイミドフィルム表面に金属層を形成する方法としては、まず、スパッタリング法によりニッケル−クロム合金等の金属層を形成し、引き続き良導電性を付与するために銅被膜を形成する方法が用いられる。上記スパッタリング法によって形成される金属層はおよそ100〜500nmが一般的である。さらに厚膜化が必要であれば、電気めっき、および電気めっきと無電解めっきを併用することによって行うことが一般的であり、その厚みは、例えばサブトラクティブ法によって回路を形成する場合は、5〜12μmが一般的である。   Moreover, as a method of forming a metal layer on the polyimide film surface, first, a method of forming a metal layer such as a nickel-chromium alloy by sputtering and subsequently forming a copper film in order to impart good conductivity is used. . The metal layer formed by the sputtering method is generally about 100 to 500 nm. If further thickening is necessary, it is generally performed by electroplating and using electroplating and electroless plating in combination, and the thickness is 5 when a circuit is formed by a subtractive method, for example. ˜12 μm is common.

上記スパッタリング、めっき法によって、あるいは銅箔を接着剤にてポリイミドフィルムに貼り合わせる方法等によって得られた金属被覆ポリイミド基板を用いてCOF、あるいはTCPを製造する方法としては、銅層をエッチングして回路を形成した後、回路表面に無電解錫めっき法により錫を厚さ約0.5μm程度形成し、80〜150℃程度の熱処理を施した後、所望の部分にソルダーレジストを形成する方法が一般的である(特許文献1参照)。
この方法により銅被膜表面に形成された錫めっき被膜は、ホイスカーと呼ばれる針状結晶が急激に成長しやすく、場合によっては隣接する回路間でホイスカーによる短絡が発生し電子回路としての役割を果たさない。これに対し、特許文献1では、錫めっき後に80〜150℃の熱処理を施すことによって発生を抑制する手法が開示されている。また、無電解錫めっき液に鉛などの低融点金属の塩を加え、錫との合金めっき層を形成することによってホイスカーの発生を抑制する方法も開示されている(特許文献2参照)。
As a method of manufacturing COF or TCP using a metal-coated polyimide substrate obtained by sputtering, plating, or a method of bonding a copper foil to a polyimide film with an adhesive, etc., a copper layer is etched. After the circuit is formed, a method of forming a solder resist on a desired portion after forming a thickness of about 0.5 μm on the surface of the circuit by an electroless tin plating method, performing a heat treatment at about 80 to 150 ° C. It is general (refer patent document 1).
The tin-plated film formed on the surface of the copper film by this method is easy to grow a needle-like crystal called whisker, and in some cases, a short circuit occurs between the adjacent circuits, and does not serve as an electronic circuit. . On the other hand, Patent Document 1 discloses a technique for suppressing generation by performing heat treatment at 80 to 150 ° C. after tin plating. Moreover, the method of suppressing generation | occurrence | production of a whisker is also disclosed by adding the salt of low melting-point metals, such as lead, to an electroless tin plating solution, and forming an alloy plating layer with tin (refer patent document 2).

一方、上記ポリイミドフィルムに形成されたスパッタ被膜表面に電気めっきによって銅被膜を形成する方法としては、陽極及び電解液を有するめっき槽を複数配置し、スパッタ被膜、ないしはめっき被膜を有するポリイミドフィルムを、これらのめっき槽に順次連続的に供給し、各めっき槽毎に通電量を制御しながら電気めっきを行なって該被膜表面に電気めっき層を連続的に所望の厚みまで形成する方法が一般的である(特許文献3参照)。   On the other hand, as a method of forming a copper film by electroplating on the surface of the sputtered film formed on the polyimide film, a plurality of plating tanks having an anode and an electrolytic solution are arranged, a sputtered film, or a polyimide film having a plated film, A general method is to successively supply these plating tanks in succession, perform electroplating while controlling the amount of current for each plating tank, and continuously form an electroplating layer on the coating surface to a desired thickness. Yes (see Patent Document 3).

ところで、COFは、ICチップとインナーリード部をボンディングした後、通常ICチップおよびその周辺部に熱硬化型樹脂を塗布、硬化することによって封止する。この際、樹脂の硬化は150℃〜160℃にて3〜4時間の熱履歴を経ることによって行われるが、上記特許文献3の手法によって得られた金属被覆ポリイミド基板を用いた場合は、上記熱履歴後、錫めっき被膜、あるいは錫めっき被膜とその表面に形成されたソルダーレジスト、封止樹脂等の被膜と共に回路から剥離する問題が発生する。これは、ホイスカー発生抑制の為の熱処理、および前記封止樹脂を硬化させるための熱処理を経ることによって、錫めっき被膜に銅が拡散することによって形成された銅錫合金層と銅被膜の界面にKirkendallボイドと呼ばれる空隙が発生、成長することによってその界面で剥離が発生する。一般に、この問題を抑制する手法として銅と錫の界面にニッケル等の異種金属層を形成する方法が開示されている(特許文献4参照)。
特開2001−144145号公報 特開平8−296050号公報 特開平7−022473号公報 特開2005−226097号公報
By the way, the COF is sealed by applying and curing a thermosetting resin to the IC chip and its peripheral part after bonding the IC chip and the inner lead part. Under the present circumstances, although hardening of resin is performed by passing through the heat history of 3 to 4 hours at 150 to 160 degreeC, when using the metal-coated polyimide substrate obtained by the method of the said patent document 3, After the thermal history, there arises a problem of peeling from the circuit together with the tin plating film, or the tin plating film and a film such as a solder resist or a sealing resin formed on the surface thereof. This is because the heat treatment for suppressing whisker generation and the heat treatment for curing the sealing resin cause the copper tin alloy film formed at the interface between the copper tin alloy layer and the copper film to diffuse. When voids called Kirkendall voids are generated and grow, peeling occurs at the interface. In general, a method of forming a dissimilar metal layer such as nickel at the interface between copper and tin has been disclosed as a technique for suppressing this problem (see Patent Document 4).
JP 2001-144145 A JP-A-8-296050 Japanese Patent Laid-Open No. 7-022473 Japanese Patent Laying-Open No. 2005-226097

しかしながら、上記特許文献4の手法を特許文献3の手法によって得られた金属被覆ポリイミド基板に用いた場合は、錫めっきに先だってニッケル等の異種金属層を銅被膜に形成するための経済的コストが増加し、また、ニッケルめっきを施すことによって新たに回路に加わる応力によってICチップのボンディング等で所定のバンプとリードに位置ずれが発生し、特にファインピンチCOFの場合はボンディング不良を引き起こす危険性が高くなる。   However, when the technique of Patent Document 4 is used for the metal-coated polyimide substrate obtained by the technique of Patent Document 3, there is an economical cost for forming a dissimilar metal layer such as nickel on the copper film prior to tin plating. In addition, the stress applied to the circuit due to nickel plating increases the position of the bumps and leads due to the bonding of the IC chip, etc., especially in the case of fine pinch COF. Get higher.

本発明者は、上記問題を解決するためになされたもので、連続的にめっきすることによって所望の厚みまで形成される積層構造の銅めっき被膜において、最終めっき近傍の層厚を適切な厚みにコントロールすることによって、銅めっき表面にニッケル等に異種金属層を形成することなく、封止樹脂を硬化させるための熱履歴によって剥離が発生しないCOFを提供することが可能な金属被覆ポリイミド基板とこれを用いた錫めっき法を提供することを目的とするものである。   The present inventor has been made to solve the above problems, and in a copper plating film having a laminated structure formed to a desired thickness by continuous plating, the layer thickness in the vicinity of the final plating is set to an appropriate thickness. A metal-coated polyimide substrate capable of providing a COF that does not cause peeling due to a thermal history for curing the sealing resin without forming a dissimilar metal layer such as nickel on the copper plating surface by controlling It aims at providing the tin plating method using this.

本発明に係る金属被覆ポリイミド基板は、ポリイミドフィルム表面にスパッタリング法によって形成した金属層の表面に、複数の電解槽により銅めっき被膜が施され、さらに前記銅めっき被膜表面に錫めっき被膜が施された金属被覆ポリイミド基板であって、前記銅めっき被膜表面に膜厚tの錫めっきを施すに際し、該銅めっき表層から少なくとも深さ3tまでの領域に同一の電解槽で電気銅めっきが施されたことを特徴とするものである。   In the metal-coated polyimide substrate according to the present invention, a copper plating film is applied to the surface of the metal layer formed by sputtering on the polyimide film surface using a plurality of electrolytic baths, and a tin plating film is further applied to the surface of the copper plating film. When the tin plating with a film thickness t was applied to the surface of the copper plating film, the copper plating was applied to the region from the copper plating surface layer to a depth of 3 t in the same electrolytic cell. It is characterized by this.

また、本発明に係る金属被覆ポリイミド基板を用いた錫めっき法は、ポリイミドフィルム表面にスパッタリング法によって金属層を形成した後、複数の電解槽を用い連続的に電気めっきを施すことによって銅めっき被膜を形成し、さらに該銅めっき被膜表面に膜厚tの錫めっきを施す金属被覆ポリイミド基板を用いた錫めっき法において、前記銅めっき被膜表面に膜厚tの錫めっきを施すに際し、該銅めっき表層から少なくとも深さ3tまでの領域に同一の電解槽で電気銅めっきを施し、錫めっき後、120℃以上の熱処理を施すことを特徴とするものである。   In addition, the tin plating method using the metal-coated polyimide substrate according to the present invention is a copper plating film formed by forming a metal layer on the polyimide film surface by a sputtering method and then continuously performing electroplating using a plurality of electrolytic cells. In the tin plating method using a metal-coated polyimide substrate for forming a tin plating with a film thickness t on the surface of the copper plating film, the copper plating is performed when the tin plating with a film thickness t is applied to the surface of the copper plating film. Electrolytic copper plating is applied to the region from the surface layer to at least a depth of 3 t in the same electrolytic bath, and after tin plating, heat treatment at 120 ° C. or higher is performed.

本発明に係る金属被覆ポリイミド基板は、これを用いて得られるCOFとICの組み立て工程において加わる封止樹脂を硬化させるための熱履歴を経ても、回路部からの錫めっき被膜の剥離を防止することが可能となり、電気的絶縁信頼性が十分確保される。また、本発明の金属被覆ポリイミド基板は、前記剥離の問題を解消するために、回路表面と錫めっき被膜界面にニッケル等の異種金属層を形成する必要がないため、COF等の電子部品の更なる高密度化を実現することが可能となり、また経済的に製品を供給することが可能となる。   The metal-coated polyimide substrate according to the present invention prevents the tin plating film from peeling off from the circuit portion even after undergoing a thermal history for curing the sealing resin applied in the assembly process of the COF and IC obtained using the same. Thus, electrical insulation reliability is sufficiently ensured. In addition, the metal-coated polyimide substrate of the present invention does not require the formation of a dissimilar metal layer such as nickel on the interface between the circuit surface and the tin plating film in order to eliminate the above-mentioned peeling problem. It becomes possible to realize a high density, and it is possible to supply products economically.

本発明において、連続的に電気めっきすることによって所望の厚みまで形成される積層構造の銅めっき被膜表面に膜厚tの錫めっきを施すに際し、該銅めっき表層から少なくとも深さ3tまでの領域に同一の電解槽で電気銅めっきを施す理由およびその具体的手法について、以下に説明する。   In the present invention, when tin plating having a film thickness t is applied to the surface of a copper plating film having a laminated structure formed to have a desired thickness by continuous electroplating, it is applied to a region from the copper plating surface layer to a depth of at least 3 t. The reason why the copper electroplating is performed in the same electrolytic cell and the specific method thereof will be described below.

一般に、銅表面に錫被膜を形成し、さらに120℃以上の熱処理を行った場合、前記のように銅と銅−錫合金の界面にKirkendallボイドと呼ばれる空隙が少なからず発生するが、これは例えば200℃、24時間以上程度の過大な熱履歴を経る場合、ないしはコネクタの端子部等の過大な外力が加わる場合を除けば、COF等の電子部品用途は剥離に到らない。しかしながら、前記の銅層が複数の電解槽で連続的に、すなわち積層構造として所望の厚みまで形成された場合、各層間には少なからずめっき結晶成長に不連続性が発生する。通常の用途では、この不連続性は、例えば銅層間の剥離等の問題に発展する危険性は極めて少ない。しかし、不連続性の程度は、例えば電解槽間で発生するめっき成長停止時間、その際のめっき表面状態、例えば、めっき液、水洗水等の被覆具合、暴露される環境、例えば温度、湿度等、種々の要因によって影響を受けるため、不連続性が極めて抑制された状況を常時確実に実現することは極めて困難であり、前記Kirkendallボイドの発生部位と比較的強い不連続性を有する銅層界面が一致、ないしは極めて隣接した場合は剥離が発生する可能性が生じる。   In general, when a tin coating is formed on the copper surface and further heat treatment at 120 ° C. or more is performed, there are not a few voids called Kirkendall voids at the interface between copper and the copper-tin alloy as described above. Except when an excessive heat history of about 200 ° C. for about 24 hours or more, or when an excessive external force such as a terminal portion of the connector is applied, the use of electronic parts such as COF does not result in peeling. However, when the copper layer is continuously formed in a plurality of electrolytic baths, that is, to a desired thickness as a laminated structure, discontinuity occurs in the growth of the plated crystal in each layer. In normal applications, this discontinuity has very little risk of developing into problems such as delamination between copper layers. However, the degree of discontinuity is, for example, the plating growth stop time generated between the electrolytic cells, the plating surface state at that time, for example, the coating condition of the plating solution, washing water, etc., the exposed environment, such as temperature, humidity, etc. Since it is affected by various factors, it is extremely difficult to always realize a situation in which the discontinuity is extremely suppressed, and the copper layer interface having a relatively strong discontinuity with the generation site of the Kirkendall void. If they are coincident or very close to each other, peeling may occur.

本発明では、前記不連続性が存在したとしても、根本的にKirkendallボイドの発生部位と一致しない構造とすることによって剥離の危険性を排除した。これは、銅表面に形成した錫めっき被膜の厚さとその後に加わる熱履歴の程度によって、Kirkendallボイドの発生部位を推定し、この発生部位と銅めっき層間の不連続部、すなわち積層界面部が一致しないように銅めっき層厚をコントロールすることによって行う。
具体的には、該当する電解槽での電着時間、例えば陰極間距離、あるいは陰極電流密度を調整することによって行う。ここで、銅表面に形成される錫めっき被膜の厚みをtとした場合、その後にCOF加工工程で通常施される熱処理としては、錫めっきホイスカー成長抑制のための120℃、30〜60分の熱処理、ソルダーレジスト硬化のための120℃、2〜3時間の熱処理、COFへのICボンディングの際に加わる420℃、1〜5秒程度の熱処理、IC封止樹脂硬化のための150℃、3〜4時間の熱処理、および液晶パネルへのアウターリードボンディングのための200℃、1分程度の熱処理を経ることによって発生するKirkendallボイドの発生位置は、錫めっきを形成する直前の銅被膜表面からおよそ深さ2tの位置に該当する。よって、Kirkendallボイド発生位置と銅めっき層間の不連続性界面位置との遭遇を回避するためには、上記熱履歴のばらつき、差異による変動を加味すると、銅めっき表層から少なくとも深さ3tまでの領域にめっき界面が存在しないように調整する必要がある。
無論、所望の銅めっき厚みが単独の電解槽で得られる場合には、前記の剥離の問題は解決されるが、本発明のようにスパッタ被膜へ電気めっきによって銅被膜を形成する場合は、通常スパッタ被膜が0.1〜0.5μmと非常に薄いため、めっき初期では大きな電流量を供給することが不可能なため、長い陰極間距離を確保することが困難であり、複数の電解槽を設ける、即ち電極間距離を適切に維持しながらめっきをする方法が一般的である。
In the present invention, even if the discontinuity exists, the risk of peeling is eliminated by adopting a structure that does not basically coincide with the site where the Kirkendall void is generated. This is based on the thickness of the tin-plated film formed on the copper surface and the degree of thermal history applied thereafter, and the generation site of Kirkendall void is estimated, and the discontinuity between this generation site and the copper plating layer, that is, the laminated interface is the same. This is done by controlling the copper plating layer thickness.
Specifically, it is performed by adjusting the electrodeposition time in the corresponding electrolytic cell, for example, the distance between the cathodes or the cathode current density. Here, when the thickness of the tin plating film formed on the copper surface is t, the heat treatment usually applied in the COF processing step is 120 ° C. for 30 to 60 minutes for tin plating whisker growth suppression. Heat treatment, 120 ° C. for solder resist curing, 2-3 hours heat treatment, 420 ° C. applied during IC bonding to COF, heat treatment for about 1-5 seconds, 150 ° C. for IC sealing resin curing, 3 The location of the Kirkendall void generated by heat treatment for ˜4 hours and heat treatment for about 1 minute at 200 ° C. for outer lead bonding to the liquid crystal panel is approximately from the surface of the copper coating immediately before the tin plating is formed. It corresponds to the position of depth 2t. Therefore, in order to avoid the encounter between the Kirkendall void generation position and the discontinuous interface position between the copper plating layers, the region from the copper plating surface layer to at least a depth of 3 t is taken into consideration when the variation of the thermal history and the variation due to the difference are taken into account. It is necessary to adjust so that there is no plating interface.
Of course, when the desired copper plating thickness is obtained in a single electrolytic cell, the above-mentioned peeling problem is solved, but when a copper coating is formed on a sputter coating by electroplating as in the present invention, it is usually Since the sputter coating is very thin, 0.1 to 0.5 μm, it is impossible to supply a large amount of current at the initial stage of plating, so it is difficult to ensure a long distance between the cathodes. A general method is to provide, that is, to perform plating while maintaining an appropriate distance between the electrodes.

次に、本発明に係る金属被覆ポリイミド基板の形態および製造方法について説明する。
図1は本発明の金属被覆ポリイミド基板の一実施例を示す概略断面図である。
すなわち、本発明の金属被覆ポリイミド基板は、ポリイミドフィルム1と複数の電解槽を用い連続的にめっき層が形成された積層構造の電気銅めっき層4の間にスパッタリングにて形成されたニッケル−クロム合金層2および銅層3が設けられている。
本発明において用いられるポリイミドフィルム1は、液晶表示用ドライバーICの実装法であるCOFの素材として見た場合、厚さは25〜50μmが一般的であり、さらに好ましくは30〜40μmである。例えばKapton 150EN(東レ・デュポン製)、Upilex 35(宇部興産製)等が好適である。
Next, the form and manufacturing method of the metal-coated polyimide substrate according to the present invention will be described.
FIG. 1 is a schematic sectional view showing an embodiment of the metal-coated polyimide substrate of the present invention.
That is, the metal-coated polyimide substrate of the present invention is nickel-chromium formed by sputtering between a copper film 4 having a laminated structure in which a plating layer is continuously formed using a polyimide film 1 and a plurality of electrolytic baths. An alloy layer 2 and a copper layer 3 are provided.
The polyimide film 1 used in the present invention generally has a thickness of 25 to 50 μm, more preferably 30 to 40 μm, when viewed as a COF material, which is a mounting method for a liquid crystal display driver IC. For example, Kapton 150EN (made by Toray DuPont), Upilex 35 S (made by Ube Industries), etc. are suitable.

ポリイミドフィルム表面にスパッタリングによって形成される金属層は、ポリイミドフィルムに直接形成される金属層としてニッケル−クロム合金層2が一般的である。この第1の金属層は、ポリイミドフィルムと金属層の密着強度、およびその耐熱、耐湿度環境下での安定性を確保する役割を果たすとされる。このニッケル−クロム合金層2の合金組成および厚みは、前記特性と密接に関係するとともに、COF等、金属層をエッチングすることによって電子回路を形成する場合は、良導電体である銅とエッチング性が大幅に異なる組成、厚みでは不都合である。よって、合金層中のクロム濃度は5〜30%、合金層の厚さは5nm〜50nmが好適とされている。   The metal layer formed by sputtering on the polyimide film surface is generally a nickel-chromium alloy layer 2 as a metal layer directly formed on the polyimide film. The first metal layer is assumed to play a role of ensuring the adhesion strength between the polyimide film and the metal layer, and its heat resistance and stability in a humidity resistant environment. The alloy composition and thickness of the nickel-chromium alloy layer 2 are closely related to the above characteristics, and in the case where an electronic circuit is formed by etching a metal layer such as COF, etching with copper which is a good conductor. However, it is inconvenient if the composition and thickness are significantly different. Therefore, the chromium concentration in the alloy layer is preferably 5 to 30%, and the thickness of the alloy layer is preferably 5 nm to 50 nm.

スパッタリングによって第1の金属層を形成した後、電気めっきを施す前に、スパッタ層の導電性を確保するために引き続きスパッタリングによって銅層3を形成する手法が取られる。この銅層3は、電気めっきによる析出を均一かつ円滑に行うべく、スパッタ層に導電性を付与するために形成され、その厚みは一般的に50〜500nmである。すなわち、50nmより薄い場合は十分な導電性が得られず、その後の電気めっきによる銅の析出均一性に悪影響を及ぼす可能性があり、他方、500nmを超えて厚く形成した場合は、導電性を付与する点ではさらに好都合であるが、スパッタリングによるポリイミドフィルムへの熱履歴強度が高まることによる基板の寸法変化、変形等の影響によって、COF等得られる製品への悪影響が懸念されるためである。   After the first metal layer is formed by sputtering, before the electroplating is performed, a technique of subsequently forming the copper layer 3 by sputtering is used to ensure the conductivity of the sputtered layer. This copper layer 3 is formed in order to impart conductivity to the sputtered layer in order to perform deposition by electroplating uniformly and smoothly, and its thickness is generally 50 to 500 nm. That is, when the thickness is less than 50 nm, sufficient conductivity cannot be obtained, which may adversely affect the copper deposition uniformity by subsequent electroplating. On the other hand, when the thickness exceeds 500 nm, the conductivity is reduced. Although it is more convenient in terms of application, it is because there is a concern about adverse effects on the product obtained such as COF due to the influence of dimensional change, deformation, etc. of the substrate due to the increase of thermal history strength to the polyimide film by sputtering.

スパッタリング処理後は、スパッタ被膜表面に複数の電解槽を用い連続的に積層構造の電気銅めっき層4を形成する。その場合、電解槽および給電機構、基板搬送機構等を組み合わせためっき装置の構成は特に限定されないが、一般的には、各電解槽毎に通電量が制御され、概ね被めっき層である導体層が薄い初期の段階では通電量が小さく、電気めっきの順序にしたがって通電量が大きくなるように設定される。各めっき槽内には、通常、被めっき物の搬入側及び搬出側の両方に電気めっきを行なうための陽極が配置されている。一方、電解槽間には、めっき被膜に電力を供給する機構が存在し、これは例えば耐食性に優れたステンレス製のローラーにめっき表面が接触する構造とし、該ローラーを介してめっき表面に電力を供給する構造が取られる。また、電解層間では給電機構の基板が大気中に暴露されるため、めっき表面が適度な電解質、例えば水で希釈されためっき液等で被覆された状態が望ましい。これは、前記基板が大気中に暴露される状況によって、前記の積層構造の界面に存在するめっき結晶成長の不連続性の程度が影響されるためである。   After the sputtering treatment, the electrolytic copper plating layer 4 having a laminated structure is continuously formed on the surface of the sputter coating using a plurality of electrolytic baths. In that case, the configuration of the plating apparatus in which the electrolytic cell, the power feeding mechanism, the substrate transport mechanism, etc. are combined is not particularly limited. In general, the amount of energization is controlled for each electrolytic cell, and the conductor layer is generally a layer to be plated. In the initial stage where the thickness is thin, the energization amount is small, and the energization amount is set to increase in accordance with the electroplating sequence. In each plating tank, anodes for performing electroplating are usually arranged on both the carry-in side and the carry-out side of the object to be plated. On the other hand, there is a mechanism for supplying power to the plating film between the electrolyzers, which has a structure in which the plating surface is in contact with, for example, a stainless steel roller having excellent corrosion resistance, and power is supplied to the plating surface via the roller. Supply structure is taken. In addition, since the substrate of the power feeding mechanism is exposed to the atmosphere between the electrolytic layers, it is desirable that the plating surface be covered with an appropriate electrolyte, for example, a plating solution diluted with water. This is because the degree of discontinuity of the plating crystal growth present at the interface of the laminated structure is affected by the situation where the substrate is exposed to the atmosphere.

本発明で用いるめっき液としては、特に限定されないが、硫酸、銅を主成分とするいわゆる硫酸銅めっき浴が一般的であり、本発明では硫酸180g/L、硫酸銅80g/L、塩素イオン50mg/L、および銅めっき被膜の表面平滑性、および電着応力緩和性を得るための添加剤を適量加えた溶液を用いることができる。
本発明で用いる陽極は、硫酸銅めっき浴を用いる場合、含リン銅を用いることが望ましい。また、本発明で用いる給電機構としては、例えばステンレス製ローラーにめっき表面を接触させる方式を採用し、また、接触前にイオン交換水をめっき面に散布することによってめっき面表面の乾燥を抑制する。
Although it does not specifically limit as a plating solution used by this invention, The so-called copper sulfate plating bath which has a sulfuric acid and copper as a main component is common, In this invention, sulfuric acid 180g / L, copper sulfate 80g / L, chloride ion 50mg. / L, and a solution to which an appropriate amount of an additive for obtaining the surface smoothness and electrodeposition stress relaxation property of the copper plating film is added can be used.
The anode used in the present invention is preferably made of phosphorous copper when a copper sulfate plating bath is used. Moreover, as a power feeding mechanism used in the present invention, for example, a method in which a plating surface is brought into contact with a stainless steel roller is adopted, and drying of the plating surface is suppressed by spraying ion exchange water on the plating surface before contact. .

本発明で形成する銅めっき厚は、COF用途であれば総厚8μmが一般的であり、また銅表面に形成する錫めっき厚は0.6μmが一般的である。よって、本発明では、銅めっき表層から少なくとも1.8μmの領域は、一つの電解槽でめっきする構成とすればよい。上記厚さ1.8μm以上の銅めっき層厚を確保するためには、基板の搬送速度、すなわち電解槽内での電解時間、および電極間距離と基板幅からめっき面に供給する電流量を求めることができる。また、無電解錫めっきを施す前に、銅表面を活性化、あるいは付着異物除去のためにあらかじめ一部をエッチングする場合は、エッチングされる厚みを考慮し、積層構造の銅層厚を調整する必要がある。
本発明で銅表面に錫層を形成する場合、無電解めっき法によって行うことができ、無電解めっき液としては、一般的なほうフッ化浴を用いることができる。例えばロームアンドハース社のTinposit LT−34を用いる。また、無電解錫めっき後、錫ホイスカー成長抑制のために施す熱処理等、およそ120℃以上の熱処理を施す場合は、本発明による剥離防止効果がより発揮される。
The copper plating thickness formed in the present invention is generally a total thickness of 8 μm for COF applications, and the tin plating thickness formed on the copper surface is generally 0.6 μm. Therefore, in this invention, what is necessary is just to set it as the structure plated by the one electrolytic vessel at least 1.8 micrometers area | region from a copper plating surface layer. In order to secure a copper plating layer thickness of 1.8 μm or more, the substrate transport speed, that is, the electrolysis time in the electrolytic cell, the distance between the electrodes, and the amount of current supplied to the plating surface is obtained from the substrate width. be able to. In addition, before activating the electroless tin plating, if the copper surface is activated or partly etched to remove adhering foreign matter, the thickness of the etched structure is taken into consideration and the copper layer thickness of the laminated structure is adjusted. There is a need.
In the present invention, when a tin layer is formed on the copper surface, it can be performed by an electroless plating method, and a general fluorination bath can be used as the electroless plating solution. For example, Rim & Haas Tinposit LT-34 is used. In addition, when heat treatment at about 120 ° C. or higher, such as heat treatment for suppressing tin whisker growth, is performed after electroless tin plating, the peeling prevention effect according to the present invention is more exhibited.

[実施例]
以下、本発明の有効性を実施例を挙げて説明するが、本発明はこれらに限定されるものではない。
[Example]
Hereinafter, the effectiveness of the present invention will be described with reference to examples, but the present invention is not limited thereto.

ポリイミドフィルムとしてKapton 150EN(東レ・デュポン製)を用い、真空度0.01〜0.1Paに保持されたチャンバー内で150℃、1分間の加熱処理を行った。引き続き、クロムを20重量%含有するニッケル−クロム合金ターゲット、および銅ターゲットを用い、ポリイミドフィルム表面に厚さ20nmのニッケル−クロム合金層、および厚さ100nmの銅層を形成した。その後、電解槽間にステンレス製ローラーによる給電機構を有した18槽の電解槽、およびスパッタ面の活性化処理、めっき面の水洗、防錆処理を電解槽列の前後に配し、水平方向に保持されたローラーによる搬送機構を有した電気銅めっきラインを使用し、各電解槽でめっきされる銅めっき層の厚みを調整し、総めっき層厚8.1μmの銅めっき被膜を形成した。その銅めっき被膜を表1に示す。   Kapton 150EN (manufactured by Toray DuPont) was used as a polyimide film, and heat treatment was performed at 150 ° C. for 1 minute in a chamber maintained at a vacuum degree of 0.01 to 0.1 Pa. Subsequently, a nickel-chromium alloy target containing 20% by weight of chromium and a copper target were used to form a nickel-chromium alloy layer having a thickness of 20 nm and a copper layer having a thickness of 100 nm on the polyimide film surface. After that, 18 electrolytic tanks with a power feeding mechanism with stainless steel rollers between the electrolytic tanks, and sputtering surface activation treatment, plating surface water washing, and rust prevention treatment were arranged before and after the electrolytic cell rows in the horizontal direction. The thickness of the copper plating layer plated in each electrolytic bath was adjusted using an electrolytic copper plating line having a transport mechanism by a held roller to form a copper plating film having a total plating layer thickness of 8.1 μm. The copper plating film is shown in Table 1.

次に、前記表1に示す銅めっき被膜を有する金属被覆ポリイミド基板を用い、銅めっき表面の活性化処理をめっき表層から厚さ0.5μmの銅をエッチング除去することによって行った後、銅表面にフォトリソグラフィー法によってエッチングレジスト層を形成し、露出した銅層を溶解除去し、さらにエッチングレジスト層を剥離することによってインナーリード部が35μmピッチの回路を形成した。続いて、該回路表面に、ロームアンドハース社製無電解錫めっき液(Tinposit LT−34)を用い、厚さ0.6μmの錫めっき被膜を形成し、120℃で30分間熱処理を施した。その後、インナーリード部、およびアウターリード部以外の所望な部分にソルダーレジスト被膜を形成し、120℃で2時間熱処理を行うことによって、インナーリード部35μmピッチのCOFを得た。得られたCOFのインナーリード部とICの所定のパッド部を420℃、0.3秒間圧着することによってボンディングし、しかる後、ICおよびその周辺の所望部に封止樹脂を塗布し、150℃、3.5時間熱処理を施した。
以上の処理後、COFおよび封止樹脂周辺部を顕微鏡によって観察したが、錫めっき被膜、およびソルダーレジスト、あるいは封止樹脂が表面に形成された錫めっき被膜と回路部との剥離は観察されなかった。
Next, using the metal-coated polyimide substrate having the copper plating film shown in Table 1, the copper plating surface activation treatment was performed by etching away 0.5 μm thick copper from the plating surface layer, and then the copper surface. Then, an etching resist layer was formed by photolithography, the exposed copper layer was dissolved and removed, and the etching resist layer was peeled off to form a circuit having inner lead portions of 35 μm pitch. Subsequently, an electroless tin plating solution (Tinposit LT-34) manufactured by Rohm and Haas was used to form a tin plating film having a thickness of 0.6 μm on the circuit surface, and heat treatment was performed at 120 ° C. for 30 minutes. Thereafter, a solder resist film was formed on a desired portion other than the inner lead portion and the outer lead portion, and a heat treatment was performed at 120 ° C. for 2 hours to obtain a COF having an inner lead portion of 35 μm pitch. The obtained COF inner lead portion and a predetermined pad portion of the IC are bonded by pressure bonding at 420 ° C. for 0.3 seconds, and then a sealing resin is applied to the IC and a desired portion around it, and 150 ° C. For 3.5 hours.
After the above treatment, the COF and the periphery of the sealing resin were observed with a microscope, but no peeling between the tin plating film and the solder resist or the tin plating film having the sealing resin formed on the surface and the circuit part was observed. It was.

Figure 2007214519
Figure 2007214519

実施例1において、銅めっきを表2に示す積層構造となるように電解槽の電流を調節し、総めっき層厚8.1μmの銅めっき被膜を形成し、また銅めっき被膜の活性化処理を行わなかった以外は実施例1と同様にCOFを製造し、得られたCOFにICをボンディングし樹脂封止した。
以上の処理後、COFおよび封止樹脂周辺部を顕微鏡によって観察したが、本実施例においても錫めっき被膜、およびソルダーレジスト、あるいは封止樹脂が表面に形成された錫めっき被膜と回路部との剥離は観察されなかった。
In Example 1, the current in the electrolytic cell was adjusted so that the copper plating had the laminated structure shown in Table 2, a copper plating film having a total plating layer thickness of 8.1 μm was formed, and the activation process of the copper plating film was performed. A COF was produced in the same manner as in Example 1 except that it was not performed, and an IC was bonded to the obtained COF and sealed with resin.
After the above treatment, the COF and the peripheral portion of the sealing resin were observed with a microscope. In this example, the tin plating film, the solder resist, or the tin plating film having the sealing resin formed on the surface and the circuit portion No peeling was observed.

Figure 2007214519
Figure 2007214519

実施例1において、銅めっきを表3に示す積層構造となるように電解槽の電流を調節し、総厚8.1μmの銅めっき被膜を形成した以外は実施例1と同様にCOFを製造し、得られたCOFにICをボンディングし樹脂封止した。
以上の処理後、COFおよび封止樹脂周辺部を顕微鏡によって観察したが、本実施例においても錫めっき被膜、およびソルダーレジスト、あるいは封止樹脂が表面に形成された錫めっき被膜と回路部との剥離は観察されなかった。
In Example 1, a COF was produced in the same manner as in Example 1 except that the current in the electrolytic cell was adjusted so that the copper plating had a laminated structure shown in Table 3 and a copper plating film having a total thickness of 8.1 μm was formed. Then, an IC was bonded to the obtained COF and sealed with resin.
After the above treatment, the COF and the peripheral portion of the sealing resin were observed with a microscope. In this example, the tin plating film, the solder resist, or the tin plating film having the sealing resin formed on the surface and the circuit portion No peeling was observed.

Figure 2007214519
Figure 2007214519

実施例1において、銅めっきを表4に示す積層構造となるように電解槽の電流を調節し、総厚8.1μmの銅めっき被膜を形成した以外は実施例1と同様にCOFを製造し、得られたCOFにICをボンディングし樹脂封止した。
以上の処理後、COFおよび封止樹脂周辺部を顕微鏡によって観察したが、本実施例においても錫めっき被膜、およびソルダーレジスト、あるいは封止樹脂が表面に形成された錫めっき被膜と回路部との剥離は観察されなかった。
In Example 1, COF was produced in the same manner as in Example 1 except that the current in the electrolytic cell was adjusted so that the copper plating had a laminated structure shown in Table 4 and a copper plating film having a total thickness of 8.1 μm was formed. Then, an IC was bonded to the obtained COF and sealed with resin.
After the above treatment, the COF and the peripheral portion of the sealing resin were observed with a microscope. In this example, the tin plating film, the solder resist, or the tin plating film having the sealing resin formed on the surface and the circuit portion No peeling was observed.

Figure 2007214519
〔比較例1〕
Figure 2007214519
[Comparative Example 1]

実施例1において、銅めっきを表5に示す積層構造となるように電解槽の電流を調節し、総厚8.1μmの銅めっき被膜を形成した以外は実施例1と同様にCOFを製造し、得られたCOFにICをボンディングし樹脂封止した。
以上の処理後、COFおよび封止樹脂周辺部を顕微鏡によって観察したところ、10μm×10μmの大きさで錫めっき被膜が剥離していることが判明し、電子部品としての信頼性に欠けるものであった。
In Example 1, COF was produced in the same manner as in Example 1 except that the current in the electrolytic cell was adjusted so that the copper plating had the laminated structure shown in Table 5 and a copper plating film having a total thickness of 8.1 μm was formed. Then, an IC was bonded to the obtained COF and sealed with resin.
After the above treatment, the COF and the periphery of the sealing resin were observed with a microscope. As a result, it was found that the tin plating film was peeled off with a size of 10 μm × 10 μm, and the reliability as an electronic component was lacking. It was.

Figure 2007214519
Figure 2007214519

本発明によって得られる金属被覆ポリイミド基板は、これを用いて得られたCOFとICの組み立て工程において加わる熱履歴を経ても、回路部からの錫めっき被膜の剥離を防止することが可能となり、電気的、絶縁信頼性が十分確保される。また、前記剥離の問題を解消するために、回路表面と錫めっき被膜界面にニッケルなどの異種金属層を形成する必要がないため、本発明によって得られる金属被覆ポリイミド基板は、COF等の電子部品の更なる高密度化を実現することが可能となり、また経済的に製品を供給することが可能となる。   The metal-coated polyimide substrate obtained by the present invention can prevent the peeling of the tin-plated film from the circuit portion even through the thermal history applied in the assembly process of the COF and IC obtained using this, Sufficient insulation reliability. In addition, since it is not necessary to form a dissimilar metal layer such as nickel on the circuit surface and the tin plating film interface in order to eliminate the problem of peeling, the metal-coated polyimide substrate obtained by the present invention is an electronic component such as COF. This makes it possible to realize a higher density and to supply products economically.

本発明の金属被覆ポリイミド基板の一実施例を示す概略断面図である。It is a schematic sectional drawing which shows one Example of the metal-coated polyimide board | substrate of this invention.

符号の説明Explanation of symbols

1 ポリイミドフィルム
2 ニッケル−クロム合金層
3 スパッツタリングによる銅層
4 積層構造の電気銅めっき層

DESCRIPTION OF SYMBOLS 1 Polyimide film 2 Nickel-chromium alloy layer 3 Copper layer by spattering 4 Electrolytic copper plating layer of laminated structure

Claims (2)

ポリイミドフィルム表面にスパッタリング法によって形成した金属層の表面に、複数の電解槽により銅めっき被膜が施され、さらに前記銅めっき被膜表面に錫めっき被膜が施された金属被覆ポリイミド基板であって、前記銅めっき被膜表面に膜厚tの錫めっきを施すに際し、該銅めっき表層から少なくとも深さ3tまでの領域に同一の電解槽で電気銅めっきが施された金属被覆ポリイミド基板。   A metal-coated polyimide substrate in which a copper plating film is applied to a surface of a metal layer formed by a sputtering method on a polyimide film surface, and a tin plating film is further applied to the surface of the copper plating film, A metal-coated polyimide substrate in which electrolytic copper plating is performed in the same electrolytic cell in a region from the copper plating surface layer to at least a depth of 3 t when tin plating having a film thickness t is applied to the surface of the copper plating film. ポリイミドフィルム表面にスパッタリング法によって金属層を形成した後、複数の電解槽を用い連続的に電気めっきを施すことによって銅めっき皮膜を形成し、さらに該銅めっき被膜表面に膜厚tの錫めっきを施す金属被覆ポリイミド基板を用いた錫めっき法において、前記銅めっき被膜表面に膜厚tの錫めっきを施すに際し、該銅めっき表層から少なくとも深さ3tまでの領域に同一の電解槽で電気銅めっきを施し、錫めっき後、120℃以上の熱処理を施すことを特徴とする金属被覆ポリイミド基板を用いた錫めっき法。

After a metal layer is formed on the polyimide film surface by sputtering, a copper plating film is formed by continuously performing electroplating using a plurality of electrolytic baths, and tin plating with a film thickness t is further formed on the surface of the copper plating film. In the tin plating method using a metal-coated polyimide substrate to be applied, when performing tin plating with a film thickness t on the surface of the copper plating film, electrolytic copper plating is performed in the same electrolytic cell in a region from the copper plating surface layer to a depth of 3 t. A tin plating method using a metal-coated polyimide substrate, characterized by applying a heat treatment at 120 ° C. or higher after tin plating.

JP2006035854A 2006-02-13 2006-02-13 Metal-coated polyimide substrate and tin plating method using the same Pending JP2007214519A (en)

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US20120132531A1 (en) * 2007-10-18 2012-05-31 Jx Nippon Mining And Metals Corporation Process and Apparatus for Producing a Metal Covered Polyimide Composite
US8568899B2 (en) 2007-10-18 2013-10-29 Jx Nippon Mining & Metals Corporation Metal covered polyimide composite, process for producing the composite, and process for producing electronic circuit board
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US8470450B2 (en) 2007-12-27 2013-06-25 Jx Nippon Mining & Metals Corporation Method of producing two-layered copper-clad laminate, and two-layered copper-clad laminate
JP2010126766A (en) * 2008-11-27 2010-06-10 Toyota Motor Corp PLATED BASE MATERIAL HAVING Sn PLATING LAYER AND METHOD OF MANUFACTURING THE SAME
JP2012001793A (en) * 2010-06-21 2012-01-05 Sumitomo Metal Mining Co Ltd Method and apparatus for manufacturing metallized resin film
JP2015140447A (en) * 2014-01-27 2015-08-03 住友金属鉱山株式会社 flexible wiring board

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