JP2007213512A - Printer and printer controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the processing speed of a printer from lowering without causing any underrun error. <P>SOLUTION: A printer controller includes; an image processing circuit which is provided with a raster buffer and outputs image data to a printing engine per raster; a CPU; a memory; and an arbitration circuit for arbitrating between a data transfer request from the image processing circuit and a memory access request from the CPU. When receiving a request for data transfer per raster from the image processing circuit, the arbitration circuit arbitrates so as to give priority to the memory access request from the CPU within a prescribed time after the start of data transfer and to give priority to the request for data transfer per raster from the image processing circuit after passage of the prescribed time. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a printing apparatus, and more particularly to a printer controller having an arbitration circuit that arbitrates memory access.

  In a laser type printing apparatus, printing is executed by transferring bitmap-developed image data to a print engine in units of one line (raster).

  The image data output to the print engine is once written in the raster buffer and read out in synchronization with the raster processing cycle of the print engine.

  In the laser printing method, when image data transfer to the print engine is started, the process cannot be stopped in the middle of the page. For this reason, as described in Patent Document 1, writing of image data to the raster buffer is not in time, and an error occurs if the image data to be transferred to the print engine is not stored in the raster buffer. This error is generally referred to as an underrun error.

  FIG. 7 is a block diagram illustrating a configuration related to data transfer processing in a conventional laser type printing apparatus.

  As shown in the figure, a CPU 120, an input / output control circuit 140, and an image processing circuit 150 are connected to a memory control circuit 110 that controls memory access to the main memory 130. The memory control circuit 110 includes a memory access circuit 111 that performs access processing to the main memory 130, and an arbitration circuit that arbitrates access requests from the CPU 120, DMA requests from the input / output control circuit 140, and DMA requests from the image processing circuit 150. 112 is provided.

  The image processing circuit 150 acquires the compressed image data stored in the main memory 130 by DMA transfer via the memory control circuit 110. For this purpose, a DMA request control circuit 151 is provided.

  The image processing circuit 150 decompresses the DMA-transferred compressed image data by the decompression circuit 152 and temporarily stores the obtained image data in the raster buffer 153. The adjustment circuit 154 performs position control processing, image adjustment processing, and the like, and sequentially outputs them to the print engine 600 in synchronization with a raster processing start signal (raster start signal).

  In this example, the image processing circuit 150 includes two raster buffers 153, and alternately outputs image data to the print engine 600. That is, while one raster buffer 153 is outputting image data, the other raster buffer 153 stores image data of the next raster.

JP 2001-26151 A

  As described above, if the writing of the image data to the raster buffer 153 is not in time for the transfer to the print engine 600, an underrun error occurs.

  Therefore, the arbitration circuit 112 of the memory control circuit 110 arbitrates the DMA request from the image processing circuit 150, particularly the DMA request for reading compressed image data, with the highest priority in order to prevent the occurrence of an underrun error. ing.

  For this reason, after the start of image data transfer to the print engine 600, even if continuous access requests from the CPU 120 are generated, the DMA request from the image processing circuit 150 is prioritized and the processing of the CPU 120 is divided. become.

  In general, since it is more efficient to perform processing in the CPU 120 continuously, priority is given to the DMA request from the image processing circuit 150, so that the processing speed of the CPU 120 decreases. In addition, the processing speed may decrease due to the CPU 120 waiting for memory access.

  An object of the present invention is to prevent a decrease in processing speed of a printing apparatus without causing an underrun error.

In order to solve the above problems, a printer controller according to a first aspect of the present invention provides:
An image processing circuit that includes a raster buffer and outputs image data in raster units to the print engine, a CPU, a memory, an arbitration for arbitrating a data transfer request from the image processing circuit and a memory access request from the CPU A printer controller comprising a circuit,
When there is a data transfer request in raster units from the image processing circuit, the arbitration circuit performs arbitration by giving priority to the memory access request from the CPU within a predetermined time from the start of data transfer, and the predetermined time has elapsed. Thereafter, arbitration is performed with priority given to data transfer requests in raster units from the image processing circuit.

  That is, within a predetermined time from the start of data transfer, data transfer to the image processing circuit is performed at a time when there is no memory access request from the CPU. As a result, the processing of the CPU is less likely to be divided due to a data transfer request from the image processing circuit, and a reduction in processing speed of the printing apparatus can be prevented. In particular, if the data transfer to the image processing circuit is completed within a predetermined time, the CPU processing is not affected. On the other hand, after a predetermined elapsed time, since the data transfer request from the image processing circuit is given priority, it is possible to prevent the occurrence of an underrun error.

In order to solve the above problem, a printer controller according to a second aspect of the present invention provides:
An image processing circuit that includes a raster buffer and outputs image data in raster units to the print engine, a CPU, a memory, an arbitration that arbitrates a data transfer request from the image processing circuit and a memory access request from the CPU A printer controller comprising a circuit,
When there is a data transfer request in raster units from the image processing circuit, the arbitration circuit performs arbitration by giving priority to the memory access request from the CPU within a predetermined time from the start of data transfer, and the predetermined time has elapsed. Thereafter, it is determined whether or not the data transfer to the image processing circuit has been completed. If the data transfer has not been completed, the data transfer request from the image processing circuit is preferentially arbitrated. .

  As a result, the processing of the CPU is less likely to be divided due to a data transfer request from the image processing circuit, and a reduction in processing speed of the printing apparatus can be prevented. In addition, when the data transfer to the image processing circuit is not completed after the predetermined elapsed time, it is possible to prevent the occurrence of an underrun error because priority is given to the data transfer request from the image processing circuit.

In either case, the predetermined time is
It can be calculated based on the output start interval of the image data to the print engine and the maximum data transfer amount to the raster buffer.

  More specifically, the predetermined time can be calculated by estimating the maximum data transfer time from the maximum data transfer amount to the raster buffer and subtracting it from the output start interval of the image data to the print engine.

In order to solve the above-described problem, a printer controller according to a third aspect of the present invention includes:
An image processing circuit that includes a raster buffer and outputs image data in raster units to the print engine, a CPU, a memory, an arbitration for arbitrating a data transfer request from the image processing circuit and a memory access request from the CPU A printer controller comprising a circuit,
The arbitration circuit sets a reference time based on the amount of data to be transferred when there is a raster-unit data transfer request from the image processing circuit, and within the reference time from the start of data transfer, the CPU Arbitration is performed with priority given to the memory access request from the memory, and arbitration is performed with priority given to the data transfer request in raster units from the image processing circuit after the reference time has elapsed.

  As a result, the processing of the CPU is less likely to be divided due to a data transfer request from the image processing circuit, and a reduction in processing speed of the printing apparatus can be prevented. Further, after the reference time set from the amount of data to be transferred, it is possible to prevent the occurrence of an underrun error because priority is given to the data transfer request from the image processing circuit.

  Here, the reference time can be calculated based on an output start interval of image data to the print engine and a data transfer amount to the raster buffer.

  More specifically, the reference time can be calculated by estimating the data transfer time from the data transfer amount to the raster buffer and subtracting it from the output start interval of the image data to the print engine.

In order to solve the above-described problem, a printer controller according to a fourth aspect of the present invention includes:
An image processing circuit that includes a raster buffer and outputs image data in raster units to the print engine, a CPU, a memory, an arbitration for arbitrating a data transfer request from the image processing circuit and a memory access request from the CPU A printer controller comprising a circuit,
The arbitration circuit performs arbitration by giving priority to the memory access request from the CPU at the start of data transfer when there is a data transfer request in raster units from the image processing circuit, and the remaining data amount to be transferred When the reference time elapses, the data transfer request from the image processing circuit is preferentially arbitrated when the reference time elapses.

  As a result, the processing of the CPU is less likely to be divided due to a data transfer request from the image processing circuit, and a reduction in processing speed of the printing apparatus can be prevented. In addition, when the remaining amount of data to be transferred and the elapsed time satisfy predetermined conditions, it is possible to prevent the occurrence of an underrun error because priority is given to the data transfer request from the image processing circuit.

  Here, the predetermined condition is that the time from the elapsed time from the start of data transfer to the start of output of image data to the print engine is calculated, and the difference between this time and the transfer time of the remaining data amount to be transferred May fall within a predetermined range.

  The present invention also provides a printing apparatus equipped with each printer controller described above.

  Embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram for explaining a configuration related to data transfer processing in a laser type printing apparatus to which the present invention is applied.

  As shown in the figure, a CPU 20, an input / output control circuit 40, and an image processing circuit 50 are connected to a memory control circuit 10 that controls memory access to the main memory 30. The memory control circuit 10 includes a memory access circuit 11 that performs access processing to the main memory 30, and an arbitration circuit that arbitrates access requests from the CPU 20, DMA requests from the input / output control circuit 40, and DMA requests from the image processing circuit 50. 12 is provided.

  The image processing circuit 50 acquires the compressed image data stored in the main memory 30 by DMA transfer via the memory control circuit 10. For this purpose, a DMA request control circuit 51 is provided. The compressed image data is obtained by compressing image data in raster units.

  The compressed image data is decompressed by the decompression circuit 52 and the obtained image data is temporarily stored in the raster buffer 53. The adjustment circuit 54 performs position control processing, image adjustment processing, and the like, and sequentially outputs them to the print engine 60 in synchronization with a raster processing start signal (raster start signal).

  The image processing circuit 50 includes two raster buffers 53 and alternately outputs image data to the print engine 60. That is, while data is stored in one raster buffer 53, image data is output from the other raster buffer 53. For this reason, underrun occurs when data for one raster cannot be accumulated by the next raster start signal after outputting image data from the raster buffer.

  Here, due to the characteristics of the print engine 60, the raster start signal is generated at regular intervals. The interval between the raster start signals is determined according to the printing resolution, the size of the printing paper, and the like.

  In this embodiment, the arbitration circuit 12 includes a transfer counter 12a and a timer 12b. The transfer counter 12 a counts the number of DMA transfers to the raster buffer 53. Since the amount of data to be DMA transferred is notified in advance from the DMA request control circuit 51 of the image processing circuit, it is possible to calculate how many DMA transfers are required for the raster being processed.

  Therefore, by counting the number of DMA transfers to the raster buffer 53, it is possible to know whether the DMA transfer to the raster buffer 53 has been completed, or the remaining transfer amount (remaining transfer count) to the raster buffer 53. Can do.

  The timer 12b measures the elapsed time from the raster start. This makes it possible to grasp the remaining time until the next raster start. Therefore, the transfer counter 12a and the timer 12b are reset at each raster start.

  Next, data transfer processing in the first embodiment of the present invention will be described with reference to the flowchart of FIG.

  This flowchart shows processing when DMA transfer of compressed image data stored in the main memory 30 to the image processing circuit 50 is performed.

  In this embodiment, when the DMA transfer to the image processing circuit 50 is started, the priority of the DMA request from the image processing circuit 50 is lowered. As a result, the access request from the CPU 20 and the DMA request from the input / output control circuit 40 are processed with priority over the DMA request from the image processing circuit 50.

  Then, the priority is switched when the elapsed time from the start of the DMA transfer has passed a predetermined reference time, so that the DMA request from the image processing circuit 50 is arbitrated to the highest priority.

  Thereby, the processing of the CPU 20 is reduced from being divided by the DMA processing to the image processing circuit 50, and the processing speed of the printing apparatus is prevented from being lowered.

  Here, the predetermined reference time can be determined as follows, for example. That is, the time required for DMA transfer can be estimated in advance from the amount of data to be transferred to the raster buffer 53. The amount of data to be transferred is estimated assuming, for example, the worst compression rate. Also, the efficiency of DMA transfer is estimated on the assumption that the conditions are bad.

  As a result, it is possible to calculate how long the DMA transfer to the raster buffer 53 is completed at least before the next raster start by starting the DMA transfer before the next raster start. The predetermined reference time can be determined as the time from the raster start to that time.

  When there is a DMA request from the image processing circuit 50, the first raster data is stored in the raster buffer 53 with the DMA transfer priority being low (S101).

  Then, image data output to the print engine 60 is started by the raster start signal (S102). Prior to the DMA transfer to the image processing circuit 50, the interval between the raster start signals is already determined.

  At the same time, the timer 12b starts counting (S103). Until the reference time elapses (S104), DMA transfer to the image processing circuit 50 is performed with low priority. Therefore, since the access request to the main memory 30 from the CPU 20 is not divided by the DMA transfer, it is possible to prevent the processing efficiency of the CPU 20 from being lowered.

  When the reference time has elapsed (S104: Y), the arbitration circuit 12 arbitrates the DMA transfer to the image processing circuit 50 with the highest priority.

  In response to the next raster start signal (S106), the image data stored in the raster buffer 53 is output to the print engine 60. Even if the DMA transfer to the image processing circuit 50 is started after the lapse of the reference time, the reference time is set so that data storage in the raster buffer 53 is in time, so that an underrun error can be prevented.

  By repeating the process (S103) until the raster to be DMA transferred is completed (S107), printing for one page is executed.

  Thus, according to the first embodiment of the present invention, it is possible to prevent a decrease in the processing speed of the printing apparatus without causing an underrun error.

  FIG. 3 is a timing chart schematically showing the state of DMA transfer in this embodiment. As shown in the figure, DMA transfer in units of rasters is started by a raster start signal. Since the request from the CPU 20 is given priority at the start of DMA transfer, the arbitration circuit 12 arbitrates so that the CPU request is given priority when the CPU request from the CPU 20 and the VDMA request from the image processing circuit 50 overlap. To do. As a result, the memory bus is preferentially used by the CPU 20.

  on the other hand. The DMA transfer by the VDMA request from the image processing circuit 50 is performed at a timing when there is no CPU request.

  After the reference time elapses, the priority is switched by an internal signal in the arbitration circuit, and the arbitration circuit 12 arbitrates so that the VDMA request from the image processing circuit 50 has the highest priority. As a result, the image processing circuit 50 preferentially uses the memory bus.

  Next, data transfer processing in the second embodiment of the present invention will be described with reference to the flowchart of FIG.

  The difference between the present embodiment and the first embodiment is that when the reference time has elapsed, it is determined whether or not the DMA transfer to the image processing circuit 50 has been completed. The priority of DMA transfer to the circuit 50 is to be increased.

  For this reason, the number of DMA transfers to the image processing circuit 50 is counted using the transfer counter 12a, and compared with the number of DMA transfers necessary for transfer, it is determined whether or not the DMA transfer to the image processing circuit 50 has been completed. to decide.

  Also in this embodiment, when there is a DMA request from the image processing circuit 50, the first raster data is stored in the raster buffer 53 with the DMA transfer priority being low (S201).

  Then, image data output to the print engine 60 is started by the raster start signal (S202). Prior to the DMA transfer to the image processing circuit 50, the interval between the raster start signals is already determined. Further, since the amount of data to be transferred to the image processing circuit 50 is notified from the image processing circuit 50, the necessary number of DMA transfers can be calculated.

  At the same time, the timer 12b starts counting (S203). Until the reference time elapses (S204), DMA transfer to the image processing circuit 50 is performed with low priority. Therefore, since the access request to the main memory 30 from the CPU 20 is not divided by the DMA transfer, it is possible to prevent the processing efficiency of the CPU 20 from being lowered.

  The value of the transfer counter 12a is increased every time DMA transfer to the image processing circuit 50 is performed.

  When the reference time elapses (S204: Y), the arbitration circuit 12 compares the value of the transfer counter 12a with the number of DMA transfers necessary for transfer, thereby completing the DMA transfer to the image processing circuit 50. It is determined whether or not (S205).

  As a result, when it is determined that the DMA transfer to the image processing circuit 50 has been completed (S205: Y), it is not necessary to increase the priority of the DMA transfer to the image processing circuit 50, so the priority is changed. Without waiting for the next raster start signal.

  On the other hand, if it is determined that the DMA transfer to the image processing circuit 50 has not been completed (S205: N), the DMA transfer to the image processing circuit 50 is arbitrated with the highest priority (S206).

  In response to the next raster start signal (S207), the image data stored in the raster buffer 53 is output to the print engine 60. Even if the DMA transfer to the image processing circuit 50 is started after the lapse of the reference time, the reference time is set so that data storage in the raster buffer 53 is in time, so that an underrun error can be prevented.

  By repeating the process of the process (S203) until the raster to be DMA-transferred is completed (S208), printing for one page is executed. The calculation of the necessary number of DMA transfers and the count of the number of DMA transfers are performed for each raster.

  Thus, according to the second embodiment of the present invention, it is possible to prevent a decrease in the processing speed of the printing apparatus without causing an underrun error. Furthermore, unnecessary priority switching can be prevented from being performed.

  Next, data transfer processing in the third embodiment of the present invention will be described with reference to the flowchart of FIG.

  The difference between this embodiment and the first embodiment is that the reference time is calculated for each raster based on the amount of data to be DMA transferred.

  For this reason, the reference time differs for each raster. That is, the reference time is short for a raster with a large amount of data to be transferred, and the reference time is long for a raster with a small amount of data to be transferred.

  Also in this embodiment, when there is a DMA request from the image processing circuit 50, the first raster data is stored in the raster buffer 53 with the DMA transfer priority being low (S301). At this time, the number of DMA transfers is counted.

  Then, image data output to the print engine 60 is started by the raster start signal (S302). Prior to the DMA transfer to the image processing circuit 50, the interval between the raster start signals is already determined.

  Then, a reference time is set based on the amount of data to be transferred to the image processing circuit 50 notified from the image processing circuit 50 (S303). The reference time estimates the time required to transfer the data amount of the raster, and if DMA transfer is started before the next raster start, at least the DMA to the raster buffer 53 by the next raster start. It can be obtained by calculating whether the transfer is completed.

  At the same time, the timer 12b starts counting (S304). Until the reference time elapses (S305), DMA transfer to the image processing circuit 50 is performed with low priority. Therefore, since the access request to the main memory 30 from the CPU 20 is not divided by the DMA transfer, it is possible to prevent the processing efficiency of the CPU 20 from being lowered.

  When the reference time has elapsed (S305: Y), the arbitration circuit 12 arbitrates the DMA transfer to the image processing circuit 50 with the highest priority.

  In response to the next raster start signal (S307), the image data stored in the raster buffer 53 is output to the print engine 60. Even if the DMA transfer to the image processing circuit 50 is started after the lapse of the reference time, the reference time is set so that data storage in the raster buffer 53 is in time, so that an underrun error can be prevented.

  By repeating the process (S303) until the raster to be DMA transferred is completed (S308), printing for one page is executed.

  Thus, according to the third embodiment of the present invention, it is possible to prevent a decrease in the processing speed of the printing apparatus without causing an underrun error. Furthermore, since the reference time is changed in accordance with the amount of data to be transferred, more realistic control is possible, and a reduction in processing speed of the printing apparatus can be further prevented.

  Next, data transfer processing in the fourth embodiment of the present invention will be described with reference to the flowchart of FIG.

  The difference between the present embodiment and the first embodiment is that the remaining data amount to be transferred to the image processing circuit 50 and the time until the next raster start signal are acquired in real time, and further to the image processing circuit 50. If the DMA transfer priority level continues to be low, the priority level is switched when there is a possibility that data accumulation in the raster buffer 53 may not be in time.

  For this reason, the arbitration circuit 12 counts the number of DMA transfers to the image processing circuit 50 using the transfer counter 12a, thereby acquiring the remaining data amount (number of remaining transfers) to be transferred to the image processing circuit 50, and the timer. By measuring the elapsed time from the raster start in 12b, the time until the next raster start signal is acquired.

  Then, the time necessary for transferring the remaining data amount is estimated, and when the time almost coincides with the time until the next raster start signal, it is determined that the transfer is possible, and the DMA transfer to the image processing circuit 50 is given the highest priority. Mediate. Whether or not they coincide with each other does not have to be exact, and it is sufficient to judge that the time difference is within a predetermined range. However, various methods can be adopted to determine the transferable limit.

  Also in this embodiment, when there is a DMA request from the image processing circuit 50, the first raster data is stored in the raster buffer 53 in a state where the priority of the DMA transfer is low (S401).

  Then, image data output to the print engine 60 is started by the raster start signal (S402). Prior to the DMA transfer to the image processing circuit 50, the interval between the raster start signals is already determined. Further, since the amount of data to be transferred to the image processing circuit 50 is notified from the image processing circuit 50, the necessary number of DMA transfers can be calculated. Each time a DMA transfer is performed, the remaining number of DMA transfers is calculated.

  At the same time, the timer 12b starts counting (S403). At the start of DMA transfer, the priority of DMA transfer to the image processing circuit 50 is set low. Therefore, since the access request to the main memory 30 from the CPU 20 is not divided by the DMA transfer, it is possible to prevent the processing efficiency of the CPU 20 from being lowered.

  The arbitration circuit 12 acquires the remaining number of DMA transfers and the elapsed time from the raster start (S404). Then, the time required for the remaining number of DMA transfers is estimated, and based on the time and the time until the next raster start signal, it is determined whether or not a transferable limit state has been reached (S405). Here, the time when the time required for transferring the remaining data amount substantially coincides with the time until the next raster start signal is determined as the transferable limit.

  As a result, when it is determined that the transfer limit has not been reached (S405: N), there is no need to increase the priority of the DMA transfer to the image processing circuit 50, so the priority is not switched and the DMA transfer is not performed. Continue.

  On the other hand, if it is determined that the transfer limit has been reached (S405: Y), the DMA transfer to the image processing circuit 50 is arbitrated with the highest priority (S406). Note that, depending on the processing status of the CPU 20, the DMA transfer may be completed without switching the priority order.

  In response to the next raster start signal (S407), the image data stored in the raster buffer 53 is output to the print engine 60.

  The transferable limit is set so that the data storage in the raster buffer 53 is in time even if the priority of DMA transfer to the image processing circuit 50 is increased at that time, so an underrun error is prevented. be able to.

  By repeating the process (S403) until the raster to be DMA-transferred is completed (S408), printing for one page is executed.

  Thus, according to the fourth embodiment of the present invention, it is possible to prevent a decrease in the processing speed of the printing apparatus without causing an underrun error. Further, the remaining data amount to be transferred to the image processing circuit 50 and the time until the next raster start signal are acquired in real time, and if the priority of DMA transfer to the image processing circuit 50 continues to be lower than this, The priority order is switched when there is a possibility that data storage in the raster buffer 53 may not be in time. As a result, more realistic control is possible, and the processing of the CPU 20 can be further prevented from being divided, so that a reduction in the processing speed of the printing apparatus can be further prevented.

FIG. 3 is a block diagram illustrating a configuration related to data transfer processing in the printing apparatus according to the embodiment. The flowchart explaining the data transfer process in a 1st Example. FIG. 6 is a timing chart for explaining data transfer processing according to the embodiment. The flowchart explaining the data transfer process in a 2nd Example. The flowchart explaining the data transfer process in a 3rd Example. The flowchart explaining the data transfer process in a 4th Example. FIG. 6 is a block diagram illustrating a configuration related to data transfer processing in a conventional printing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Memory control circuit, 11 ... Memory access circuit, 12 ... Arbitration circuit, 12a ... Transfer counter, 12b ... Timer, 20 ... CPU, 30 ... Main memory, 40 ... Input / output control circuit, 50 ... Image processing circuit, 51 ... DMA request control circuit 52 ... decompression circuit 53 ... raster buffer 54 ... adjustment circuit 60 ... print engine 110 ... memory control circuit 111 ... memory access circuit 112 ... arbitration circuit 130 ... main memory 140 ... input Output control circuit 150... Image processing circuit 151... DMA request control circuit 152. Decompression circuit 153 Raster buffer 154 Adjustment circuit 160 Print engine

Claims (10)

An image processing circuit that includes a raster buffer and outputs image data in raster units to the print engine, a CPU, a memory, an arbitration for arbitrating a data transfer request from the image processing circuit and a memory access request from the CPU A printer controller comprising a circuit,
When there is a data transfer request in raster units from the image processing circuit, the arbitration circuit performs arbitration by giving priority to the memory access request from the CPU within a predetermined time from the start of data transfer, and the predetermined time has elapsed. Thereafter, the printer controller performs arbitration by giving priority to data transfer requests in raster units from the image processing circuit. An image processing circuit that includes a raster buffer and outputs image data in raster units to the print engine, a CPU, a memory, an arbitration that arbitrates a data transfer request from the image processing circuit and a memory access request from the CPU A printer controller comprising a circuit,
When there is a data transfer request in raster units from the image processing circuit, the arbitration circuit performs arbitration by giving priority to the memory access request from the CPU within a predetermined time from the start of data transfer, and the predetermined time has elapsed. Thereafter, it is determined whether or not the data transfer to the image processing circuit has been completed. If the data transfer has not been completed, the data transfer request from the image processing circuit is preferentially arbitrated. Printer controller. The printer controller according to claim 1 or 2,
The predetermined time is
A printer controller, which is calculated based on an output start interval of image data to a print engine and a maximum data transfer amount to the raster buffer. The printer controller according to claim 2,
The printer controller according to claim 1, wherein the predetermined time is calculated by estimating a maximum data transfer time from a maximum data transfer amount to the raster buffer and subtracting it from an output start interval of the image data to the print engine. An image processing circuit that includes a raster buffer and outputs image data in raster units to the print engine, a CPU, a memory, an arbitration for arbitrating a data transfer request from the image processing circuit and a memory access request from the CPU A printer controller comprising a circuit,
The arbitration circuit sets a reference time based on the amount of data to be transferred when there is a raster-unit data transfer request from the image processing circuit, and within the reference time from the start of data transfer, the CPU A printer controller characterized in that arbitration is performed with priority given to a memory access request from the image processing unit, and arbitration is performed with priority given to a data transfer request in raster units from the image processing circuit after the reference time has elapsed. The printer controller according to claim 5, wherein
The reference time is
A printer controller, which is calculated based on an output start interval of image data to a print engine and a data transfer amount to the raster buffer. The printer controller according to claim 6, wherein
The calculation of the reference time is performed by estimating a data transfer time from a data transfer amount to the raster buffer and subtracting it from an output start interval of the image data to the print engine. An image processing circuit that includes a raster buffer and outputs image data in raster units to the print engine, a CPU, a memory, an arbitration that arbitrates a data transfer request from the image processing circuit and a memory access request from the CPU A printer controller comprising a circuit,
The arbitration circuit performs arbitration by giving priority to the memory access request from the CPU at the start of data transfer when there is a data transfer request in raster units from the image processing circuit, and the remaining data amount to be transferred And an elapsed time from the start of data transfer satisfy a predetermined condition, and after the reference time has elapsed, arbitration is performed with priority given to a raster unit data transfer request from the image processing circuit. . The printer controller according to claim 8, comprising:
The predetermined condition is:
Calculate the time from the start of data transfer to the start of output of image data to the print engine, and the difference between this time and the transfer time of the remaining data amount to be transferred falls within a predetermined range. A printer controller characterized by the above. A printing apparatus equipped with the printer controller according to claim 1.

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