JP2007208815A - High-precision cyclic a/d converter and image sensor using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-precision cyclic A/D converter and image sensor using the same. <P>SOLUTION: Capacitors (C1, C2) are connected between an input of an inverted amplifier and an input signal and similarly between the input of the inverted amplifier and an output thereof, thereby obtaining a stable gain 2 and a capacitance error between the capacitors (C1, C2) is canceled by a capacitor (C3) for correction, thereby performing high-precision cyclic A/D conversion. It is important therefor to control opening/closing of a switch which changes over the connection of the capacitors. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for reducing a conversion error in a cyclic A / D converter.

In a pipeline A / D converter using a switched capacitor, a method for canceling a mismatch in capacitance is disclosed in Non-Patent Document 1. Further, Non-Patent Document 2 discloses a method for reducing the offset voltage and 1 / f noise of an amplifier to about 1/3 in a pipeline A / D converter that shares an amplifier using a switched capacitor.
In the cyclic A / D converter, the inventor has already filed a patent application regarding a method of sharing an amplifier and providing a noise canceling function in the column of the image sensor (see Patent Document 1).
JP 2005-136540 A Bang-Sup Song, Michael F. Tompsett, and Kadaba R. Lakshmikumar, "A 12-bit 1-Msample / s capacitor error-averaging pipelined A / D converter," IEEE Journal of Solid-State Circuits, vol. 23, pp 1324-1333, December 1988. BM Min, P. Kim, D. Boisvert, A. Aude, "A 69mW 10b 80MS / s pipelined CMOS ADC," Dig. Tech. Papers, Int. Solid-State Circuits Conf., Pp.324-235, 2003.

The cyclic A / D converter generally includes an amplifier having a gain of 2, a sampling hold circuit, a comparator, and a subtraction circuit that subtracts a comparison result from an input signal.
In the present invention, a cyclic A / D converter is constituted by an inverting amplifier and a capacitor while omitting a sampling and holding circuit.

FIG. 1 shows a cyclic A / D converter for canceling a capacity mismatch error. A diagram for explaining the operation principle is shown in FIG. The operation timing is shown in FIG. Each switch is controlled by control signals φ0 to φ5 and φc from a control circuit (not shown). Some switches are controlled by the output signal φD of the decoder (4).
The first capacitor (hereinafter referred to as “C1”), the second capacitor (hereinafter referred to as “C2”), and the third capacitor for correction (hereinafter referred to as “C3”) all have the same capacitance C1 = C2 = C3. .
In the first sampling, as shown in FIG. 2A, C1 and C2 are connected in parallel to sample the input signal. At this time, C3 is connected between the inverting input and output of the amplifier (1) having a differential input and a differential output, and the input and output are short-circuited by a switch, so the voltage at both ends of C3 is 0. . At this time, the two comparators (2, 3) determine by sampling the input signal difference and determine the most significant digit. In order to perform A / D conversion of 1.5b per cycle, two comparators are provided, and the reference voltage is determined as VR and ± VR / 4 is determined as a threshold according to the characteristic diagram of FIG.
In the first comparator (2), the output (D0) becomes “1” in the range of Vin> VR / 4, and the output (D0) becomes “0” in the range of Vin ≦ VR / 4. In the second comparator (3), the output (D1) becomes “1” in the range of Vin ≧ −VR / 4, and the output (D1) becomes “0” in the range of Vin <−VR / 4.
The relationship between the digital outputs D0 and D1 in FIG. 1, D in FIG. 4, and the input signal Vin (= Vinp−Vin) to the comparator is as follows.

すなわち、入力を(1) -VRから-VR/4, (2) -VR/4からVR/4, (3) VR/4からVRの３領域に分割し、これらの領域に対して３値のA/D変換を行って-1, 0, 1のディジタルコードを割り当てる。最初のコードは最上位桁になる。
デコーダ(４)の出力はφc2が"１"のときに、φD0，φDN，φDPのいずれかが"１"になり、Vin＞VR/4の場合はφDPが"１"，-VR/4≦Vin≦VR/4の場合はφD0が"１"，Vin＜-VR/4の場合はφDNが"１"となるように動作する。
次に、図２(b)に移り、比較器の出力をデコーダ(４)によりデコードした出力をもちいてＤ／Ａ変換器(５：以下「DAC」という)を制御し、２倍増幅して、DACの出力を引く基本演算を行う。このとき、各Ｃ３の一端はアンプ(１)の各出力に接続される。また、各Ｃ３の他端が相互に接続される。これは電位的に接地電位に接続されることと等価である。したがって、シングルエンドの反転増幅器を用いる際には、Ｃ３の他端を適切な接地電位に接続することとなる。これらの接続を、ここでは仮想的な接地電位に接続するという。増幅器としてシングルエンドの差動入力オペアンプ(６)を使用した回路例を図５に示す。
キャパシタの容量に誤差がなければ、その演算は、次式で表される。

That is, the input is divided into (1) -VR to -VR / 4, (2) -VR / 4 to VR / 4, and (3) VR / 4 to VR. A / D conversion of -1, 0, 1 is assigned. The first code is the most significant digit.
The output of the decoder (4) is that when φc2 is “1”, any of φD0, φDN, and φDP is “1”, and when Vin> VR / 4, φDP is “1”, −VR / 4 ≦ When Vin ≦ VR / 4, the operation is performed so that φD0 is “1”, and when Vin <−VR / 4, φDN is “1”.
Next, moving to FIG. 2 (b), a D / A converter (5: hereinafter referred to as "DAC") is controlled by using the output obtained by decoding the output of the comparator by the decoder (4), and amplified twice. , Basic operation to subtract DAC output. At this time, one end of each C3 is connected to each output of the amplifier (1). Moreover, the other end of each C3 is mutually connected. This is equivalent to being connected to the ground potential in terms of potential. Therefore, when using a single-ended inverting amplifier, the other end of C3 is connected to an appropriate ground potential. These connections are referred to herein as virtual ground potentials. A circuit example using a single-ended differential input operational amplifier (6) as an amplifier is shown in FIG.
If there is no error in the capacitance of the capacitor, the calculation is expressed by the following equation.

ここでVout=Voutp - Voutnである。
しかしながら、回路に用いる容量C1, C2に誤差があると次のような関係式になる。

これにより生じる誤差を低減するために、C3にこのときの出力電圧を記憶させる。
その後、図２(c)に移り、容量のC1とC2を入れ替えて、動作させる。このときの出力は、次式で与えられる。

Here, Vout = Voutp−Voutn.
However, if there is an error in the capacitors C1 and C2 used in the circuit, the following relational expression is obtained.

In order to reduce the error caused by this, the output voltage at this time is stored in C3.
Thereafter, the process moves to FIG. 2 (c), and the capacitors C1 and C2 are switched to operate. The output at this time is given by the following equation.

次に、図２(d)に移り、C3をアンプの入出力間に接続するとともに、C1に、そのときの出力電圧を記憶する。C3には、式(3)の電圧が記憶されていることから、C3と式(4)の電圧が記憶されたC2を並列に接続したときに、出力電圧は、次式のようになる。

ΔＣ３＝Ｃ３−Ｃ１，ΔＣ２＝Ｃ２−Ｃ１と置くと、

Next, moving to FIG. 2 (d), C3 is connected between the input and output of the amplifier, and the output voltage at that time is stored in C1. Since the voltage of equation (3) is stored in C3, when C3 and C2 in which the voltage of equation (4) is stored are connected in parallel, the output voltage is as follows.

If ΔC3 = C3-C1, ΔC2 = C2-C1,

と表される。これは、式(3)の

と比べると誤差が遙かに小さくなっている。例えば、ΔＣ２／Ｃ１＝０．０１，ΔＣ３／Ｃ１＝０．０１であったとして、式(6)の誤差の項 (ΔＣ３ΔＣ２)／Ｃ１(２Ｃ１＋ΔＣ３＋ΔＣ２) は、ほぼ0.00005 (0.005%)である。このように、容量のバラツキが１%程度あったとしても、その誤差を殆ど無視できる値にすることができる。

It is expressed. This is the equation (3)

The error is much smaller than that. For example, assuming that ΔC2 / C1 = 0.01 and ΔC3 / C1 = 0.01, the error term (ΔC3ΔC2) / C1 (2C1 + ΔC3 + ΔC2) in Equation (6) is approximately 0.00005 (0.005%). Thus, even if there is a variation in capacity of about 1%, the error can be made a value that can be almost ignored.

The voltage subjected to error correction in this way is stored in C1, but the voltage stored in C2 is also corrected for error. After the operation of FIG. 2 (d), the process proceeds to FIG. 2 (b), and the A / D conversion of the next digit is executed, but the calculation is continued for the voltage whose error is corrected, and the variation in capacity is A / D conversion can be performed without being affected.
Here, the configuration in the case of performing the calculation of 1.5b has been described, but it can be easily analogized that this can also be realized in the case of performing the calculation of 1b using only one comparator.
Furthermore, although a differential circuit is used here, it can be easily analogized that a circuit that cancels variation in capacitance due to the same operation can be configured even with a single-ended circuit, and these are excluded from the present invention. is not.
Since the high-accuracy cyclic A / D converter described so far has a small number of parts, it can be incorporated on a chip of a CMOS image sensor or a CCD image sensor. That is, a large area is not consumed even if it is incorporated in an array in the signal line column led out from each photodetecting element.

  With the configuration described above, a high-accuracy cyclic A / D converter can be put into practical use by correcting the capacitance error of the capacitor. This configuration is useful because it has a small number of components and can be incorporated on a chip of a CMOS image sensor or a CCD image sensor.

Cyclic A / D converter canceling capacity mismatch error The figure explaining operation | movement of the cyclic | annular A / D converter of FIG. The figure which shows the operation timing in the converter of FIG. Diagram showing the input / output characteristics of a cyclic A / D converter that performs 1.5b A / D conversion per cycle Diagram showing an example using a single-ended differential input operational amplifier as an amplifier

Explanation of symbols

1 Amplifier 2, 3 Comparator 4 Decoder 5 D / A Converter (DAC)
6 Differential input operational amplifier

Claims (4)

In the cyclic A / D converter, an inverting amplifier, a comparator connected to the output of the inverting amplifier, a D / A converter that converts a determination result of the comparator into an analog value, a first capacitor, A second capacitor set equivalent to the capacitance of the first capacitor, a third capacitor for correction, a plurality of switches provided for switching connection of these capacitor groups, and these switches A high-accuracy cyclic A / D converter comprising control means for controlling on / off of the group. In the first phase, the control means connects one end of the first capacitor and the second capacitor to the input signal, and connects the other end of the first capacitor and the second capacitor to the input of the inverting amplifier. , One end of a third capacitor is connected to the output of the inverting amplifier, the other end of the third capacitor is connected to the input of the inverting amplifier, and the comparator determines the output of the inverting amplifier;
In the second phase, the control means connects one end of the first capacitor to the output of the inverting amplifier, connects one end of the second capacitor to the output of the D / A converter, and outputs a third capacitor. And connect the other end to a virtual ground potential
In the third phase, the control means connects one end of the first capacitor to the output of the D / A converter, connects one end of the second capacitor to the output of the inverting amplifier, Separate the other end of
In the fourth phase, the control means connects one end of the first capacitor to the output of the inverting amplifier, connects the other end of the first capacitor to a virtual ground potential, and other than the third capacitor. Connect the end to the input of the inverting amplifier, the comparator makes the following decision:
2. The high-accuracy cyclic A / D converter according to claim 1, wherein the A / D conversion is cyclically performed by sequentially repeating the second phase to the fourth phase. An image sensor in which the high-accuracy cyclic A / D converter according to claim 1 is arranged in an array on a column of an image sensor on which photodetecting elements are arranged. An image sensor comprising the high-accuracy cyclic A / D converter according to claim 2 arranged in an array on a column of an image sensor on which photodetecting elements are arranged.

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