JP2007208790A - Signal processing apparatus and digital modulation signal demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing apparatus capable of reducing Gaussian noise included in an FSK or QPSK signal so as to stabilize an amplitude, and to provide a digital modulation signal demodulator. <P>SOLUTION: An A-D converter 22 converts an analog input signal s into a digital signal S which is given to a signal separation means 23. The signal separation means 23 separates the input signal S into two signals I, Q whose phases are mutually orthogonal to each other and outputs them to an amplitude calculation means 24. The amplitude calculation means 24 obtains the root of the sum of both of the squared signals I, Q as an amplitude V of the input signal. A division means 25 divides either of the signals I, Q by the amplitude V calculated by the amplitude calculation means 24 and outputs a signal S' whose amplitude is stabilized and a noise component is suppressed to a demodulation circuit 30. The demodulation circuit 30 applies demodulation processing to the signal S'. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for processing a digitally modulated signal via a transmission line, and more particularly to a technique for enabling signal demodulation with few errors by removing the influence of attenuation and noise caused by the transmission line.

  Conventionally, a frequency shift method (FSK) and a phase shift method (PSK, QPSK) are used as modulation methods for transmitting 1 and 0 digital information.

  These modulation systems are systems that vary the frequency and phase of the transmission signal, and communication that is not easily affected by the amplitude noise is possible. However, if the amplitude attenuation by the transmission path is large, the S / N decreases, and By superimposing Gaussian noise, errors during demodulation increase.

  For this reason, in a system that transmits a signal of the above modulation scheme, automatic gain control is performed in order to suppress amplitude attenuation by the transmission path.

  For example, in Patent Document 1, an intermediate frequency signal is input to a quadrature detection circuit via a variable gain amplifier, data is demodulated from baseband signals I and Q output from the quadrature detection circuit, and the square of the I signal is The square root of the sum of the square of the Q signal is calculated to obtain the amplitude, and the gain of the variable gain amplifier is feedback controlled so that the amplitude becomes constant.

JP-A-7-321864

  However, since the feedback control as described in Patent Document 1 results in average value processing, it is possible to follow a slow fluctuation in signal amplitude, but the amplitude fluctuation is fast, for example, to Gaussian noise superimposed on a signal. In response to this, it is impossible to suppress the amplitude fluctuation due to the noise component. In particular, noise components in the Nyquist band are difficult to remove by a filter.

  Therefore, if the FSK or QPSK signal is transmitted through a line with a poor S / N and demodulated, it is greatly affected by the amplitude fluctuation of the Gaussian noise and the error rate is lowered.

  An object of the present invention is to solve this problem and provide a signal processing device and a digital modulation signal demodulating device that can reduce Gaussian noise contained in FSK and QPSK signals.

In order to achieve the above object, a signal processing apparatus according to claim 1 of the present invention comprises:
Signal separation means (23) for separating the input signal into two signals I and Q whose phases are orthogonal to each other;
Amplitude calculation means (24) for obtaining an amplitude value of the input signal based on the signals I and Q;
Dividing means (25) for dividing one of the signals I and Q by the amplitude value calculated by the amplitude calculating means and outputting a signal whose amplitude is stabilized and whose noise component is suppressed; Have.

A signal processing device according to claim 2 of the present invention is the signal processing device according to claim 1,
Comparing means (28) for comparing the amplitude value calculated by the amplitude calculating means with a predetermined reference value;
In response to the result of the comparison means, during a period when the amplitude value exceeds the reference value, a signal obtained by dividing the one signal by the amplitude value is output as a processing result, and the amplitude value is the reference value Switching means (29) for outputting the one signal as a processing result during a period not exceeding the value is provided.

A digital modulation signal demodulating device according to claim 3 of the present invention comprises:
In a digital modulation signal demodulator having a demodulation circuit (30) for demodulating a digital modulation signal whose frequency or phase is modulated by a data signal,
The signal processing device according to claim 1 or 2 is provided before the demodulating circuit.

  As described above, the signal processing apparatus according to the present invention divides the signal I or the signal Q by the amplitude value calculated based on the two signals I and Q obtained from the input signal, thereby stabilizing the amplitude and suppressing the noise component. Is output.

  For this reason, the amplitude can be stabilized by high-speed real-time processing, and noise components that cannot be removed by the filter can be greatly suppressed.

  Further, the amplitude value calculated by the amplitude calculating means is compared with a predetermined reference value by the comparing means, and a signal obtained by dividing one signal by the amplitude value during a period when the amplitude value exceeds the reference value is obtained. A period in which one signal is output as a processing result during a period when the processing result is output and the amplitude value does not exceed the reference value can correspond to a burst wave.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of a digital modulation signal demodulating device 20 including a signal processing device to which the present invention is applied.

  The digital modulation signal demodulating device 20 includes a signal processing unit 21 that stabilizes the amplitude of a signal to be demodulated and suppresses noise, and a demodulation circuit 30.

  The signal processing unit 21 converts the analog input signal s (t) into a digital signal sequence S (k) by the A / D converter 22 and inputs the signal to the signal separation unit 23.

  The signal separation means 23 separates the signal S (k) into signals I (k) and Q (k) whose phases are orthogonal to each other.

  The signal separation means 23 inputs the signal S (k) to the Hilbert transformer 23a and generates a signal Q (k) obtained by shifting the signal S (k) by 90 degrees. The delay unit 23b gives the signal S (k) a delay time equal to the delay time Td necessary for the processing of the Hilbert transformer 23a, and outputs this as the signal I (k). This delay time Td is represented by an integer n times the sampling period Ts.

  The two signals I (k) and Q (k) obtained by the signal separation unit 23 are input to the amplitude calculation unit 24. The amplitude calculation means 24 calculates the amplitude value V of the signal S (k) by the following calculation.

V (k) = [I (k) ² + Q (k) ² ] ^1/2

  This amplitude value V (k) is input to the dividing means 25 together with the signal Q (k), and the following calculation is performed.

S (k) ′ = Q (k) / V (k) = Q (k) / [I (k) ² + Q (k) ² ] ^1/2

  The signal S (k) ′ thus obtained becomes a signal in which the noise component contained in the original signal S (k) is reduced and the amplitude is stabilized (standardized).

  For example, as shown in FIG. 2, when a signal S having amplitude A and frequency f and having no noise is input, each signal S, I, and Q is expressed as follows assuming that each signal is an analog signal. .

S = Acos (2πft + Td)
I = Acos (2πft)
Q = Asin (2πft)

Therefore, the amplitude value V calculated by the amplitude calculating means 24 is
V = [I ² + Q ² ] ^1/2
= A {[cos (2πft)] ² + [sin (2πft)] ² } ^1/2
= A
It becomes.

Therefore, the signal S ′ output from the dividing means 25 is
S ′ = Q / V = sin (2πft)
It becomes.

  As shown in FIG. 2, the output signal S ′ is normalized (attenuated) by multiplying the amplitude of the signal S by 1 / A and is normalized (attenuated), and the phase is shifted by 90 degrees with respect to the signal S. A delay of minutes.

  FIG. 2 shows the case where the amplitude A of the signal S is greater than 1, but the above processing is the same for an arbitrary amplitude A of the input signal. Therefore, even when the amplitude A of the signal S is smaller than 1 as shown in FIG. 3, the amplitude of the output signal S ′ is normalized (amplified) to 1.

  That is, even if the amplitude A of the signal S varies, the amplitude of the output signal S ′ is always stabilized at a constant value (in this case, 1).

  Moreover, since this signal processing is real-time control although there is a delay for the Hilbert transform, for example, as shown in FIG. 4, even if the signal S is superposed with Gaussian noise and the amplitude changes in small increments. Since the signal processing follows the change, the output signal S ′ is outputted as a sine wave having an amplitude ratio of about 1 and an improved S / N ratio. That is, the signal processing has an input signal amplitude stabilization and noise suppression action. In other words, as shown in FIG. 5, since the orthogonality between the signal I and the signal Q is ensured, the ratio Q / V (signal Q / V of the signal Q to the amplitude value V no matter how the amplitude value V varies) S ′) is sin 2πft, and its amplitude is constant at 1.

  In this way, the signal S ′ whose amplitude is stabilized with respect to the input signal s and whose noise component is suppressed is input to the demodulation circuit 30.

  For example, as shown in FIG. 6, the demodulating circuit 30 inputs local signals L1 and L2 that are output from the local signal generator 30a and have phases orthogonal to each other to the mixers 30b and 30c, respectively. S (k) ′, and the baseband signals I ′ and Q ′ are extracted from the outputs of the mixers 30b and 30c by the low-pass filters 30d and 30e, respectively, and input to the data demodulator 30f. Data corresponding to the symbol point determined by Q ′ is demodulated.

  Since the signal amplitude of the signal S (k) ′ input to the demodulation circuit 30 is stabilized and the noise component is suppressed in the signal processing unit 21, the data can be demodulated with a low error rate.

  In the above example, the signal Q that has undergone the phase shift processing by the Hilbert transformer 23a is divided by the amplitude V to obtain the signal S '. The processing of the Hilbert transformer 23a is basically high-pass filter processing. Therefore, the signal Q does not include a DC component, and the output signal S ′ does not include a DC component. Therefore, no direct current component is applied to the mixers 30b and 30c of the demodulation circuit 30, and demodulation errors due to leakage (carrier leakage) of the local signals L1 and L2 do not occur.

  However, when the error due to the carrier leakage is expected to be small, the signal S can be obtained by dividing the signal I by the amplitude value V.

in this case,
S ′ = I / V = cos 2πft
Thus, similarly to the above example, the signal S ′ whose amplitude is standardized to 1 and the noise component is suppressed can be obtained.

  In the above example, the case where the signal s is continuously input has been described. However, when the signal s is input in a burst shape, the amplitude calculating unit 24 as in the signal processing unit 21 ′ illustrated in FIG. The amplitude value V calculated in step (1) and a preset reference value Vr are input to the comparison means 28. While the amplitude value V exceeds the reference value Vr (signal input period), the calculation of the division means 25 is performed as described above. A switch 29 for outputting a signal Q is provided as a switching means in place of the calculation result S ′ of the dividing means 25 during a period (signal non-input period) in which the result S ′ is output and the amplitude value V is equal to or less than the reference value Vr. It can respond. Note that the switching means not only selects the output signal as in this example, but also forcibly sets the amplitude value V input to the dividing means 25 to 1 so that the signal Q is output from the dividing means 25. You can also.

  In the embodiment, the input signal s is A / D converted and then separated into two signals I and Q. However, the analog input signal is separated into two signals and then A / D converted. Good.

  The processing target of the signal processing units 21 and 21 'in the above embodiment is not limited to digital modulation signals such as FSK and QPSK, but also applies to various modulation signals other than amplitude modulation and non-modulation signals (carrier signals). it can.

Configuration diagram of an embodiment of the present invention Operation explanatory diagram of the main part of the embodiment Operation explanatory diagram of the main part of the embodiment Operation explanatory diagram of the main part of the embodiment Operation explanatory diagram of the main part of the embodiment Configuration diagram of the main part of the embodiment Configuration diagram of an embodiment corresponding to a burst wave

Explanation of symbols

  DESCRIPTION OF SYMBOLS 20 ... Digital modulation signal demodulator, 21, 21 '... Signal processing part, 22 ... A / D converter, 23 ... Signal separation means, 23a ... Hilbert converter, 23b ... Delay device, 24 ... ... Amplitude calculation means, 25 ... Division means, 28 ... Comparison means, 29 ... Switch, 30 ... Demodulation circuit

Claims (3)

Signal separation means (23) for separating the input signal into two signals I and Q whose phases are orthogonal to each other;
Amplitude calculation means (24) for obtaining an amplitude value of the input signal based on the signals I and Q;
Dividing means (25) for dividing one of the signals I and Q by the amplitude value calculated by the amplitude calculating means and outputting a signal whose amplitude is stabilized and whose noise component is suppressed; A signal processing apparatus. Comparing means (28) for comparing the amplitude value calculated by the amplitude calculating means with a predetermined reference value;
In response to the result of the comparison means, during a period when the amplitude value exceeds the reference value, a signal obtained by dividing the one signal by the amplitude value is output as a processing result, and the amplitude value is the reference value 2. A signal processing apparatus according to claim 1, further comprising switching means for outputting said one signal as a processing result during a period not exceeding the value. In a digital modulation signal demodulator having a demodulation circuit (30) for demodulating a digital modulation signal whose frequency or phase is modulated by a data signal,
3. A digital modulation signal demodulating device comprising the signal processing device according to claim 1 or 2 provided in a preceding stage of the demodulating circuit.

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