JP2007206029A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correctly determine whether stress application or a test is taking place in a device. <P>SOLUTION: A semiconductor device 20 is equipped with a first test circuit 1, a second test circuit 2, a test mode detection circuit 3 and a terminal Pad1. The first test circuit 1 is active, when an input signal IN1 is at "High" level and inactive, when the signal is at "Low" level and changes from "High" level to "Low". The second test circuit 2 is inactive, when an input signal IN2 is at a "Low" level and is active, when the signal is at "High" level and changes from "High" level to "Low". Bias application is continued on a gate of a Pch MOS transistor PT1 provided inside, after the signal changes from "High" level to "Low". <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a test circuit capable of determining stress application or test.

  In semiconductor devices such as semiconductor memory and SoC (system on a chip), malfunctions occur while operating by applying a burn-in test or applying power to reduce initial defects and improve reliability and quality in actual use conditions. A dynamic monitor burn-in test (also referred to as Dynamic Monitored Burn-In Test DMBT) or the like is performed (see, for example, Patent Document 1).

In recent years, with the progress of high integration and multi-functionalization of semiconductor devices such as semiconductor memories and SoCs, it has become necessary to execute various test modes, and a predetermined stress is applied to elements constituting the semiconductor device. It may be difficult to determine whether or not In addition, a DMBT device that operates a semiconductor device as an LSI so that a large number of elements are activated by applying a predetermined stress and can easily monitor whether the operation is normal or not is enormous. In addition, there is a problem that the test time increases.
JP 2002-296324 A (page 20, FIG. 1)

  It is an object of the present invention to provide a semiconductor device having a test circuit that can accurately determine whether stress application, special mode test, or the like is performed on a device as expected, or whether unexpected stress is applied.

  In order to achieve the above object, a semiconductor device of one embodiment of the present invention receives a first input signal, operates based on the first input signal, and outputs a first output signal. A test circuit, a second test circuit that receives the second input signal, operates based on the second input signal, and outputs a second output signal; and outside the first and second test circuits The first and second input signals are compared with the transistor provided in the first, the first and second output signals are detected, and whether a predetermined screening or test is normally applied to the transistor, Alternatively, a test mode detection circuit for determining whether or not unexpected noise is applied is provided.

  In order to achieve the above object, a semiconductor device according to another aspect of the present invention receives a first input signal, operates based on the first input signal, and outputs a first output signal. A first test circuit, a second test circuit that inputs a second input signal, operates based on the second input signal, and outputs a second output signal, and an nth (n is 3 or more) An nth test circuit that inputs an nth input signal, operates based on the nth input signal, and outputs an nth output signal, and is provided outside the first to nth test circuits. The first to nth input signals and the first to nth output signals are detected, and whether a predetermined screening or test is normally applied to the transistor, or unexpected. Test to determine if noise is applied Characterized by comprising a chromatography de detection circuit.

  According to the present invention, there is provided a semiconductor device having a test circuit that can accurately determine whether stress application, special mode test, or the like has been performed on a device as expected, or whether unexpected stress is applied. Can do.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings. 1 is a block diagram showing a semiconductor device, FIG. 2 is a circuit diagram showing a first test circuit, and FIG. 3 is a circuit diagram showing a second test circuit. In this embodiment, two types of test circuits are provided.

  As shown in FIG. 1, the semiconductor device 20 is provided with a first test circuit 1, a second test circuit 2, a test mode detection circuit 3, and a terminal Pad1, and the semiconductor device 20 is a volatile semiconductor integrated circuit. is there.

  In the first test circuit 1 and the second test circuit 2, whether or not stress application or test is normally performed in an initial failure screening process or a product shipment process of a semiconductor integrated circuit unit (not shown), that is, the semiconductor device 20 It can be used to determine whether excessive stress is applied to the constituent elements or whether expected stress is normally applied. Specifically, a NBTI (Negative Bias Temperature Instability) phenomenon that occurs in a fine Pch MOS transistor with a gate oxide film thickness of several nanometers or a fine Pch MISFET (Metal Insulator Semiconductor Field Effect Transistor) with a gate insulation film thickness of several nanometers. Can be discriminated from the variation amount of the absolute value of the threshold voltage of the fine Pch MOS transistor.

  Here, the NBTI phenomenon means that the absolute value of the threshold voltage of the Pch MOS transistor increases due to enhancement by boron, nitrogen, damage to the gate insulating film or the gate oxide film, and the like. The Pch MOS transistor is also called a Pch MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  The first test circuit 1 receives an input signal IN1 output from the inside of the semiconductor device 20 or from the outside through a terminal, operates in accordance with the input signal IN1, and outputs an output signal Out1. The second test circuit 2 receives an input signal IN2 output from the inside of the semiconductor device 20 or from the outside through a terminal, operates in accordance with the input signal IN2, and outputs an output signal Out2.

  The test mode detection circuit 3 is provided between the first test circuit 1 and the second test circuit 2 and the terminal Pad1, and the output signal Out1 output from the first test circuit 1 and the second test circuit 2 When the output signal Out2 is input, the output signal Out1 and the output signal Out2 detect “active” or “inactive”, and when both are active, the difference between the output signal Out1 and the output signal Out2 is detected. The detection output signal Tout is output to the terminal Pad1. Further, the test mode detection circuit 3 can compare the input signal IN1 and the input signal IN2 and amplify the difference between the output signal Out1 and the output signal Out2.

  As shown in FIG. 2, the first test circuit 1 is provided with a Pch MOS transistor PT1, an Nch MOS transistor NT1, an Nch MOS transistor NT2, an inverter INV1, an inverter INV2, a resistor R1, and a resistor R2.

  The resistor R1 has one end connected to the high potential side power source Vdd and the other end connected to the node N1. N-channel MOS transistor NT1 has a drain connected to node N1, and an input signal IN1 input to the gate. One end of the resistor R2 is connected to the source of the Nch MOS transistor NT1, and the other end is connected to the low potential side power source Vss as the ground potential.

  The Pch MOS transistor PT1 has a source connected to the high potential side power supply Vdd, a gate connected to the node N1, and a drain connected to the node N2. The Nch MOS transistor NT2 has a drain connected to the node N2, a source connected to the low potential power source Vss, a gate connected to the high potential power source Vdd, and the high potential power source Vdd being supplied. "is doing.

  The inverter INV1 receives the signal of the node N2 and inverts the signal. Inverter INV2 receives the signal output from INV1, inverts the signal, and outputs a signal in phase with node N2 to node N3.

  As shown in FIG. 3, the second test circuit 2 includes a Pch MOS transistor PT1, a Pch MOS transistor PT2, Nch MOS transistors NT1 to NT5, inverters INV1 to INV4, and resistors R1 to R4.

  The resistor R1 has one end connected to the high potential side power supply Vdd and the other end connected to the node N11. N-channel MOS transistor NT1 has a drain connected to node N11, and an input signal IN2 input to the gate. One end of the resistor R2 is connected to the source of the Nch MOS transistor NT1, and the other end is connected to the low potential side power source Vss as the ground potential.

  The Pch MOS transistor PT1 has a source connected to the high potential side power supply Vdd, a gate connected to the node N11, and a drain connected to the node N12. The Nch MOS transistor NT2 is “ON” when the drain is connected to the node N12, the source is connected to the low potential power source Vss, the gate is connected to the high potential power source Vdd, and the high potential power source Vdd is supplied. "is doing.

  The inverter INV1 inputs the signal of the node N12 and inverts the signal. Inverter INV2 receives the signal output from INV1, inverts the signal, and outputs a signal in phase with node N12 to node N13.

  The resistor R3 has one end connected to the high potential side power source Vdd and the other end connected to the node N14. N-channel MOS transistor NT3 has a drain connected to node N14, and an input signal IN13 input to the gate. The resistor R4 has one end connected to the source of the Nch MOS transistor NT3 and the other end connected to the low potential power source Vss.

  The Pch MOS transistor PT2 has a source connected to the high potential side power supply Vdd, a gate connected to the node N14, and a drain connected to the node N15. The Nch MOS transistor NT4 has a drain connected to the node N15, a source connected to the low potential power source Vss, a gate connected to the high potential power source Vdd, and the high potential power source Vdd being supplied. "is doing.

  The inverter INV3 receives the signal of the node N15 and inverts the signal. Inverter INV4 receives the signal output from INV3, inverts the signal, and outputs a signal in phase with node N15 to node N16. The Nch MOS transistor NT16 has a drain connected to the node N11, a source connected to the low potential power source Vss, and an input signal IN16 input to the gate.

Here, the resistance value of the resistor R1 is Ra, the resistance value of the resistor R2 is Rb, the resistance value of the resistor R3 is Rc, the resistance value of the resistor R4 is Rd, and the "ON" resistance value of the Nch MOS transistor NT1 is Rnt1, Nch MOS The “ON” resistance value of the transistor NT2 is Rnt2, the “ON” resistance value of the Nch MOS transistor NT3 is Rnt3, the “ON” resistance value of the Nch MOS transistor NT4 is Rnt4, the “ON” resistance value of the Nch MOS transistor NT5 is Rnt5, The “ON” resistance value of the Pch MOS transistor PT1 is Rpt1, the threshold voltage Vpt1 of the Pch MOS transistor PT1 is, for example, −2 V, the “ON” resistance value of the Pch MOS transistor PT2 is Rpt2, and the threshold of the Pch MOS transistor PT2 is For example, when the value voltage Vpt2 is -1V Here, for example,
Ra = Rb ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (1)
Rc = Rd ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (2)
Rnt2 = Rpt1 (3)
Rnt4 = Rpt2 (4)
Ra, Rb >> Rnt1, Rnt2, Rpt1,... (5)
Rc, Rd >> Rnt3, Rnt4, Rpt2,... (6)
Ra >> Rnt5 ... Formula (7)
Is set.

  Next, the operation of the test circuit will be described with reference to FIGS. FIG. 4 is a diagram showing the state of the output signal of the test circuit with respect to the input signal, FIG. 4A is a diagram showing the state of the output signal of the first test circuit with respect to the input signal, and FIG. FIG. 5 is a diagram showing the state of the output signal of the test circuit of FIG. 2, FIG. 5 is a diagram showing the variation of the absolute value of the threshold voltage with respect to the source-gate voltage of the Pch MOS transistor in the test circuit, and FIG. It is a figure which shows the variation | change_quantity of the absolute value of the threshold voltage with respect to the stress time of the source-gate voltage of a MOS transistor.

  As shown in FIG. 4A, in the first test circuit 1, when the input signal IN1 of “Low” level (disable signal level) is input, the Nch MOS transistor NT1 is “OFF”, so that output is performed. The signal Out1 becomes “Low” level (inactive).

  When an input signal IN1 of “High” level (enable signal level) is input, the Nch MOS transistor NT1 is turned “ON”. The node N1 becomes the “1 / 2Vdd” level (because it is set by the expressions (1) and (5)). For example, when the high potential side power supply Vdd voltage is 4 V or more, the Pch MOS transistor PT1 is “ON”. The voltage between the source and gate of the Pch MOS transistor PT1 is approximately ½ “Vdd” level.

  The node N2 becomes the “½ Vdd” level (because it is set by the expression (3)), and the signal level of the node N3 as the output signal Out1 becomes the Vdd level (the output signal Out1 is “active”).

  When the input signal IN1 changes from the “High” level (enable signal level) to the “Low” level (disable signal level), the Nch MOS transistor NT1 is “OFF”, so that the output signal Out1 is at the “Low” level (output signal level). Out1 becomes “inactive”).

  On the other hand, as shown in FIG. 4B, in the second test circuit 2, when the input signal IN2 of “Low” level (disable signal level) is input, the Nch MOS transistor NT1 is “OFF”. Therefore, the output signal Out2 is not output (the output signal becomes “inactive”).

  When the input signal IN2 of “High” level (enable signal level) is input, the Nch MOS transistor NT1 is turned “ON”. The node N11 is at the “½ Vdd” level (because it is set by the equations (1) and (5)). For example, the Pch MOS transistor PT1 is “ON” when Vdd ≧ 4V or more. The node N12 becomes the “1 / 2Vdd” level (because it is set by the expression (3)), and the signal level of the node N13 as the output signal Out2 becomes the “active” state.

  The Nch MOS transistor NT3 inputs the signal of the node N13 to “ON”, the Pch MOS transistor PT2 inputs the signal of the node N14 to “ON”, and the Nch MOS transistor NT5 inputs the signal of the node N16. “ON”.

  When the input signal IN2 changes from the “High” level (enable signal level) to the “Low” level (disable signal level), the Nch MOS transistor NT1 is “OFF”, but the Nch MOS transistor NT5 is “ON”. The node N11 is substantially “Vss” (because it is set by the equation (7)). That is, the source-gate voltage of the Pch MOS transistor PT1 is substantially at the “Vdd” level. The node N12 becomes the “1 / 2Vdd” level (because it is set by the expression (3)), and the signal level of the node N13 as the output signal Out2 becomes the “Vdd” level (the output signal remains “active”). Become).

  For this reason, even when the input signal IN2 changes from the “High” level to the “Low” level, the applied voltage of about “−Vdd” is applied to the gate of the Pch MOS transistor PT1 compared to the source voltage. Will be. This applied voltage cannot be released unless the high potential side power supply Vdd is turned “OFF” and then turned “ON” again, or the high potential side power supply Vdd voltage is lowered to, for example, 2 V or less.

  As shown in FIG. 5, when the Pch MOS transistor PT1 of the second test circuit is, for example, a fine MOS transistor having a gate insulating film thickness of several nanometers, the temperature is relatively high (100 ° C. or higher), and Static (DC type). When a continuous bias is applied between the source and the gate for a relatively long time, the NBTI phenomenon occurs. | ΔVthp |, which is an increase in the threshold voltage of the Pch MOS transistor PT1 due to the NBTI phenomenon, greatly depends on the source-gate voltage, and the amount of change increases rapidly as the source-gate voltage increases.

  As shown in FIG. 6, when the Pch MOS transistor PT1 of the second test circuit is, for example, a fine MOS transistor having a gate insulation film thickness of several nanometers, the temperature is relatively high (100 ° C. or higher), and Static (DC type). When a bias is applied between the source and the gate, | ΔVthp | increases with the stress application time. The amount of change in | ΔVthp | becomes more prominent as the bias application voltage between the source and the gate increases.

  Note that even if a pulse signal generally used in the operation of the semiconductor device 20 is applied to the gate of the Pch MOS transistor (dynamic application), the amount of change in | ΔVthp | This amount of change can also be controlled by adding nitrogen atoms to the gate oxide film.

  Next, the power supply voltage margin of the first test circuit 1 and the second test circuit 2 and the amount of change in | ΔVthp | due to the NBTI phenomenon of the Pch MOS transistor PT1 will be described.

If the input signals IN1 and IN2 change from the “High” level (enable signal level) to the “Low” level (disable signal level) and this state has passed for a predetermined time (t), the first test circuit 1 Since the amount of change | ΔVthp | due to the NBTI phenomenon of the Pch MOS transistor PT1 hardly changes, the power supply voltage margin Vddmin. 1 (the lowest power supply voltage at which the output signal Out1 is activated) is
Vddmin. 1 = Vddmin. 1 (Init.) ... Formula (8)
It can be expressed. Here, Vddmin. 1 (Init.) Is an initial power supply voltage margin.

On the other hand, the Pch MOS transistor PT1 of the second test circuit 2 increases / changes | ΔVthp | due to the NBTI phenomenon, so that the measured power supply voltage margin of the second test circuit 2 is Vddmin. 2 (the lowest power supply voltage at which the output signal Out2 is activated), the power supply voltage margin Vddmin. 2 is worse than the initial power supply voltage margin. Therefore, if the initial power supply voltage margin of the first test circuit 1 and the initial power supply voltage margin of the second test circuit 2 are the same, the second Deterioration amount ΔVddmin. Of power supply voltage margin of test circuit 2 Is
ΔVddmin. = Vddmin. 2-Vddmin. 1. Formula (9)
It can be expressed.

  If the relationship between the change amount of the power supply voltage margin of the second test circuit 2 and the change amount of the absolute value of the threshold voltage of the Pch MOS transistor PT1 of the second test circuit 2 is acquired in advance as a database, it is observed. ΔVddmin. From this, the change amount | ΔVthp | of the absolute value of the threshold voltage of the Pch MOS transistor PT1 of the second test circuit 2 can be calculated. Here, if, for example, a differential amplifier circuit or the like is used as the test mode circuit 3, the degradation amount ΔVddmin. It is also possible to directly output a level amplified by a factor of.

  As described above, the semiconductor device of this embodiment is provided with the first test circuit 1, the second test circuit 2, the test mode detection circuit 3, and the terminal Pad1. The first test circuit 1 becomes active when the input signal IN1 is at the “High” level, and becomes inactive when the input signal IN1 is at the “Low” level and after changing from the “High” level to the “Low” level. On the other hand, the second test circuit 2 becomes inactive when the input signal IN2 is at the “Low” level, becomes active after changing from the “High” level to the “Low”, and becomes “High” level when the input signal IN2 is at the “High” level. After changing from “Low” to “Low”, bias application is continued to the gate of the Pch MOS transistor PT1 provided therein.

  For this reason, the output signal Out1 output from the first test circuit 1 and the output signal Out2 output from the second test circuit 2 are detected and compared by the test mode detection circuit 3, whereby the second test circuit 2 Of the power supply voltage margin of ΔVddmin. From this value, the change amount | ΔVthp | of the absolute value of the threshold voltage due to the NBTI phenomenon of the Pch MOS transistor of the second test circuit 2 can be calculated.

  Therefore, the burn-in device, DMBT (Dynamic Monitored Burn-In Test) device, etc. are used to determine whether the elements constituting the semiconductor device 20 are normally stressed or tested and whether the reliability level is satisfied. This can be done using the test circuit 1 and the second test circuit 2. Further, it can be used to determine whether an excessive stress exceeding the rating (for example, an abnormal high voltage or an abnormal high voltage pulse signal) is applied in the actual use state of the semiconductor device 20. Furthermore, it is possible to determine whether or not the element fluctuates due to stress application or test, and whether or not the fluctuation amount still satisfies a predetermined standard.

  In this embodiment, the semiconductor device is composed of MOS transistors, but a MISFET (Metal Insulator Semiconductor Field Effect Transistor) whose gate is made of an insulator may be used.

  Next, a semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing a semiconductor device, and FIG. 8 is a circuit diagram showing a third test circuit. In the present embodiment, a first test circuit that normally operates in response to an input signal and (n−1) test circuits that maintain an “active state” even after the input signal has changed from a “High” level to a “Low” level. Is provided.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  7, the semiconductor device 20a includes a first test circuit 1, a second test circuit 2 as a first, an nth test circuit 4 as a (n−1) th, a test A mode detection circuit 3a and a terminal Pad1 are provided, and (n-1) test circuits that output a signal different from the first test circuit when an input signal changes are provided. The semiconductor device 20a is a volatile semiconductor integrated circuit. Here, illustration and description of the second to (n−2) th test circuits are omitted.

  The nth test circuit 4 receives an input signal INn output from the inside of the semiconductor device 20a or through the terminal, operates in accordance with the input signal INn, and outputs an output signal Outn.

  The test mode detection circuit 3 a is provided between the first test circuit 1, the second test circuit 2,... And the n th test circuit 4 and the terminal Pad 1, and is output from the first test circuit 1. The output signal Out1, the output signal Out2, output from the second test circuit 2, and the output signal Outn of the nth test circuit 4 are input, the output signal Out1, the output signal Out2,. When the signal Outn detects “active” or “inactive” and the first test circuit 1, the second test circuit 2,... And the nth test circuit 4 become active, the output signal Out1 and the output .. And the difference between the output signal Out1 and the output signal Outn are detected, and the detection output signal Tout is output to the terminal Pad1. Further, the test mode detection circuit 3a compares the input signal IN1, the input signal IN2,... And the input signal INn, and compares the output signal Out1, the output signal Out2,..., And the output signal Out1 and the output signal Outn. Differences can be amplified. For this reason, when an unexpected excessive stress is applied to the semiconductor device 20a for some reason, the first test circuit 1, the second test circuit 2,... And the nth test circuit 4 are used. Unexpected excessive stress can be detected.

  As shown in FIG. 8, the nth test circuit 4 includes a Pch MOS transistor PT1, a Pch MOS transistor PT2, Nch MOS transistors NT1 to NT4, an Nch MOS transistor NT31, an Nch MOS transistor NT3 (n−1), and an inverter INV1. Through 4 and resistors R1 through R4. Here, (n−1) Nch MOS transistors including Nch MOS transistor NT31,... Nch MOS transistor NT3 (n−1) are cascade-connected between the node N21 and the low potential side power supply Vss. In the m-th test circuit (m is (n−1) ≧ m ≧ 2), m Nch MOS transistors are cascade-connected between the node N21 and the low potential power source Vss.

  The resistor R1 has one end connected to the high potential side power supply Vdd and the other end connected to the node N21. N-channel MOS transistor NT1 has a drain connected to node N21, and an input signal INn input to the gate. One end of the resistor R2 is connected to the source of the Nch MOS transistor NT1, and the other end is connected to the low potential side power source Vss as the ground potential.

  The Pch MOS transistor PT1 has a source connected to the high potential side power supply Vdd, a gate connected to the node N21, and a drain connected to the node N22. The Nch MOS transistor NT2 is “ON” when the drain is connected to the node N22, the source is connected to the low potential power source Vss, the gate is connected to the high potential power source Vdd, and the high potential power source Vdd is supplied. "is doing.

  The inverter INV1 receives the signal of the node N22 and inverts the signal. Inverter INV2 receives the signal output from INV1, inverts the signal, and outputs a signal in phase with node N22 to node N23.

  The resistor R3 has one end connected to the high potential side power source Vdd and the other end connected to the node N24. Nch MOS transistor NT3 has a drain connected to node N24 and a gate connected to node N23. The resistor R4 has one end connected to the source of the Nch MOS transistor NT3 and the other end connected to the low potential power source Vss.

  The Pch MOS transistor PT2 has a source connected to the high potential side power supply Vdd, a gate connected to the node N24, and a drain connected to the node N25. The Nch MOS transistor NT4 has a drain connected to the node N25, a source connected to the low potential power source Vss, a gate connected to the high potential power source Vdd, and the high potential power source Vdd being supplied. "is doing.

  The inverter INV3 receives the signal of the node N25 and inverts the signal. Inverter INV4 receives the signal output from INV3, inverts the signal, and outputs a signal in phase with node N25 to node N26.

  Nch MOS transistor NT31 has a drain connected to node N21, a gate connected to node N26, and a source connected to the drain of an adjacent Nch MOS transistor (not shown) connected in cascade. Nch MOS transistor NT3 (n-1) has a drain connected to the source of a cascaded adjacent Nch MOS transistor (not shown), a gate connected to node N26, and a source connected to low potential side power supply Vss. .

Here, when the resistance value of the resistor R1 is Ra, the “ON” resistance value of the Nch MOS transistor NT31 is Rnt31, and the “ON” resistance value of the Nch MOS transistor NT3 (n−1) is Rnt31, the input signal INn is “High”. When the "level" (enable signal level) changes to the "Low" level (disable signal level), the Nch MOS transistor NT1 is turned "OFF", but the Nch MOS transistor NT31 ... and the Nch MOS transistor NT3 (n-1) Since a total of (n−1) Nch MOS transistors are “ON”, the signal level V (n−1) of the node N21 is
V (n−1) = Vdd × [{(n−1) × Rnt31} / {Ra + (n−1) × Rnt31}] Equation (10)
It can be expressed. The signal level Vm in the mth test circuit is
V (m) = Vdd × [{m × Rnt31} / {Ra + m × Rnt31}]... Equation (11)
It can be expressed. Here, m is 1 ≦ m ≦ (n−1).

When the gate voltage difference applied to the mth Pch MOS transistor PT1 and the m + 1th Pch MOS transistor PT1 is ΔV,
V (m) = Vdd− (n−1) × ΔV ........................... (12)
It can be expressed.

  Thus, by providing (n-1) test circuits in which the number of cascaded Nch MOS transistors is changed, (n-1) types of predetermined circuits are provided between the source and gate of the Pch MOS transistor PT1. A voltage can be applied, an absolute value change amount | ΔVthp | of the threshold voltage based on the NBTI phenomenon corresponding to the predetermined voltage can be generated, and the value can be calculated in the same manner as in the first embodiment.

  As described above, in the semiconductor device of this embodiment, the first test circuit 1, the second test circuit 2 as the first, the nth test circuit 4 as the (n-1) th, the test mode A detection circuit 3a and a terminal Pad1 are provided, and (n-1) test circuits that output a signal different from that of the first test circuit when an input signal changes are provided.

  The first test circuit 1 becomes active when the input signal IN1 is at the “High” level, and becomes inactive when the input signal IN1 is at the “Low” level and after changing from the “High” level to the “Low” level. The second test circuit 2 becomes inactive when the input signal IN2 is at the “Low” level, becomes active after changing from the “High” level to the “Low” when it is at the “High” level, and changes from the “High” level to the “High” level. After changing to "Low", bias application is continued to the gate of the Pch MOS transistor PT1 provided inside. The nth test circuit 4 becomes inactive when the input signal INn is at the “Low” level, becomes active after changing from the “High” level to the “Low” when it is at the “High” level, and changes from the “High” level to the “High” level. After changing to "Low", bias application is continued to the gate of the Pch MOS transistor PT1 provided inside. Then, after changing from the “High” level to “Low”, the absolute value of the voltage applied to the gate of the Pch MOS transistor PT1 of the nth test circuit 4 is the Pch MOS transistor PT1 of the second test circuit 2. It is set larger than the absolute value of the voltage applied to the gate.

  Therefore, the output signal Out1 output from the first test circuit 1, the output signal Out2 output from the second test circuit 2,..., The output signal Outn output from the nth test circuit 4 are set in the test mode. The detection circuit 3 detects and compares the output signal Out1 and the output signal Out2,... By comparing the output signal Out1 and the output signal Outn, thereby deteriorating the power supply voltage margin ΔVddmin. To degradation of the power supply voltage margin ΔVddmin. (N−1) types can be calculated, and from this value, the change amount | ΔVthp | of the absolute value of the threshold voltage due to the NBTI phenomenon of the Pch MOS transistor of the second test circuit 2 to the Pch MOS transistor of the nth test circuit 4 It is possible to calculate (n−1) types of the amount of change | ΔVthp | in the absolute value of the threshold voltage due to the NBTI phenomenon.

  Therefore, the burn-in device, DMBT (Dynamic Monitored Burn-In Test) device, etc. are used to determine whether the elements constituting the semiconductor device 20 are normally stressed or tested and whether the reliability level is satisfied. This can be performed in more detail than the first embodiment by using one test circuit 1 to nth test circuit 4. Further, it can be used to determine whether an excessive stress exceeding the rating (for example, an abnormal high voltage or an abnormal high voltage pulse signal) is applied in the actual use state of the semiconductor device 20. Furthermore, it is possible to determine whether or not the element fluctuates due to stress application or test, and whether or not the fluctuation amount still satisfies a predetermined standard.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiments, the case where the present invention is applied to a semiconductor device as a volatile semiconductor integrated circuit has been described. However, the present invention can also be applied to a SoC (system on a chip), a nonvolatile semiconductor integrated circuit, or the like.

1 is a block diagram showing a semiconductor device according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a first test circuit according to Embodiment 1 of the present invention. FIG. FIG. 3 is a circuit diagram showing a second test circuit according to the first embodiment of the invention. The figure which shows the state of the output signal of the test circuit with respect to the input signal which concerns on Example 1 of this invention. FIG. 3 is a diagram showing a change amount of an absolute value of a threshold voltage with respect to a source-gate voltage of a Pch MOS transistor in a test circuit according to Embodiment 1 of the present invention. FIG. 5 is a diagram showing a change amount of an absolute value of a threshold voltage with respect to a stress time of a source-gate voltage of a Pch MOS transistor in the test circuit according to the first embodiment of the present invention. FIG. 6 is a circuit diagram showing a first test circuit according to Embodiment 2 of the present invention. FIG. 6 is a circuit diagram showing an nth test circuit according to Embodiment 2 of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st test circuit 2 2nd test circuit 3, 3a Test mode detection circuit 4 nth test circuit 20, 20a Semiconductor device IN1, IN2, INn Input signal INV1-4 Inverters N1-3, N11-16, N21 ~ 26 Nodes NT1-5, NT31, NT3 (n-1) Nch MOS transistors Out1, Out2, Outn Output signal Pad1 Terminal PT1, PT2 Pch MOS transistors R1-4 Resistance Tout Detection output signal Vdd High potential side power supply Vss Low potential side Power supply

Claims (5)

A first test circuit that receives a first input signal, operates based on the first input signal, and outputs a first output signal;
A second test circuit that inputs a second input signal, operates based on the second input signal, and outputs a second output signal;
A transistor provided outside the first and second test circuits;
The first and second input signals are compared, the first and second output signals are detected, whether a predetermined screening or test is normally applied to the transistor, or unexpected noise is applied. A test mode detection circuit for determining whether or not
A semiconductor device comprising:   The second test circuit holds the second output signal in an active state even after the second input signal changes from the enable signal level to the disable signal level, and keeps the high potential side power supply below a predetermined voltage or 2. The semiconductor device according to claim 1, wherein the second output signal can be returned to an inactive state by turning off the high-potential side power supply.   The first test circuit is provided with a first Pch MOS transistor, the second test circuit is provided with a second Pch MOS transistor, and the second Pch MOS transistor has an NBTI phenomenon. The semiconductor device according to claim 1, wherein a gate voltage that increases an absolute value of the threshold voltage is applied. A first test circuit that receives a first input signal, operates based on the first input signal, and outputs a first output signal;
A second test circuit that inputs a second input signal, operates based on the second input signal, and outputs a second output signal;
An nth test circuit that inputs an nth (n is an integer of 3 or more) input signal, operates based on the nth input signal, and outputs an nth output signal;
A transistor provided outside the first to nth test circuits;
The first to n-th input signals are compared, the first to n-th output signals are detected, whether a predetermined screening or test is normally applied to the transistor, or unexpected noise is applied. A test mode detection circuit for determining whether or not
A semiconductor device comprising:   The second test circuit holds the second output signal in an active state even after the second input signal changes from the enable signal level to the disable signal level, and keeps the high potential side power supply below a predetermined voltage or By turning off the high potential side power supply, the second output signal can be returned to an inactive state, and the third to nth (n is an integer of 4 or more) test circuits include: Even after the third to n-th input signals change from the enable signal level to the disable signal level, the third to n-th output signals are held in an active state, and the high-potential-side power supply is kept below a predetermined voltage or The third to n-th output signals can be returned to an inactive state by turning off the high-potential side power supply, and the first Pch MOS transistor is included in the first test circuit. The second test circuit is provided with a second Pch MOS transistor, the third to nth test circuits are provided with third to nth Pch MOS transistors, and the second test circuit is provided with a second Pch MOS transistor. A first gate voltage (Vsg = Vdd, where Vgs is a gate-source voltage and Vdd is the high-potential side power supply voltage) that increases the absolute value of the threshold voltage most due to the NBTI phenomenon is applied to the Pch MOS transistor The third to nth Pch MOS transistors include second to (n-1) th gates that are sequentially relaxed with respect to the first gate voltage that increases the absolute value of the threshold voltage due to the NBTI phenomenon. Voltage (Vgs ≦ Vdd− (n−1) × ΔV where ΔV is the difference between the mth gate voltage and the m + 1th gate voltage, where 1 ≦ m ≦ (n−1)). The semiconductor device according to claim 4, characterized in that.

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