US20160358672A1 - Circuits, methods, and media for detecting and countering aging degradation in memory cells - Google Patents
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
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- G—PHYSICS
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
Definitions
- Static Random Access Memory (SRAM) devices have sensitive circuitry and often operate with high switching activity and at high temperature. This makes the transistors that make up their bitcells particularly vulnerable to various aging mechanisms including Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) degradation.
- NBTI and PBTI change transistor threshold voltages (V TH ) over time and are major reliability concerns in modern system on a chip (SoC) designs. Since such aging effects can degrade critical robustness and performance metrics, such as data retention voltage (DRV) and read access time (T ACC ), it is highly desirable to provide mechanism to enable monitoring and managing aging effects upon memory devices.
- DDRV data retention voltage
- T ACC read access time
- circuits for measuring threshold voltages of transistors in a memory device bitcell comprising: a multiplexer that has a plurality of pairs of inputs, each connected to a different pair of bitlines of the memory device, and that has an output connected to a pair of bitline terminals; a first plurality of interconnected switches that are connected to a ground, a test voltage, a sense voltage node (V SEN ), the pair of bitline terminals, and a pair of sensor terminals; a second plurality of interconnected switches that are connected to the test voltage, the ground, the sense voltage node (V SEN ), a positive voltage connection, an n-well connection, and a ground power connection of the bitcell; and a zero-V TH thick-oxide NMOS transistor having a gate, a drain, and a source, wherein the gate is connected to the source, the source is connected to the gate and one
- FIG. 1 is an example of a memory device include mechanisms for monitoring degradation effects on the memory device's bitcells in accordance with some embodiments.
- FIG. 2 is an example of a model of a configuration of four transistors of the memory device FIG. 1 when that device is in a certain configuration in accordance with some embodiments.
- FIG. 3 is an example of a diagram showing connections between power supply lines and sense amplifiers in even cycles and odd cycles in accordance with some embodiments.
- FIG. 4 is an example of a timing diagram of signals of the memory device of FIG. 1 during an even cycle in accordance with some embodiments.
- FIG. 5 is another example of a memory device include mechanisms for monitoring degradation effects on the memory device's bitcells in accordance with some embodiments.
- FIG. 6 is an example of a bitline multiplexer, a sensor switch network, and a sensor that can be used in the memory device of FIG. 5 in accordance with some embodiments.
- FIG. 7 is an example of a power switch network that can be used in conjunction with the memory device of FIG. 5 in accordance with some embodiments.
- FIG. 8 is an example of a bitline multiplexer that can be used in the memory device of FIG. 5 in accordance with some embodiments.
- FIG. 9 is an example of a model of the connections between a device under test and a sensor in a certain configuration of the memory device of FIG. 5 in accordance with some embodiments.
- FIG. 10 is an example of another model of the connections between a device under test and a sensor in a certain configuration of the memory device of FIG. 5 in accordance with some embodiments.
- FIG. 11 is an example of a block diagram of a data retention voltage (DRV) estimator that can be implemented in conjunction with the memory device of FIG. 5 in accordance with some embodiments.
- DVR data retention voltage
- FIG. 12 is an example of a block diagram of a read access time (T ACC ) estimator that can be implemented in conjunction with the memory device of FIG. 5 in accordance with some embodiments.
- T ACC read access time
- FIG. 13 is an example of a configurable delay line in accordance with some embodiments.
- mechanisms which can include circuits, methods, and media, for detecting and countering aging degradation in memory cells are provided.
- these mechanisms can include in-situ techniques that sense the threshold voltage (V TH ) of bitcell transistors and can operate in-field by sensing V TH values robustly across temperature and voltage variations.
- these techniques can: (1) be used to sense V TH values periodically (e.g., every several months) for evaluating the amount and the rate of NBTI and/or PBTI degradation; (2) be used to sense V TH values between two PMOSs in a bitcell to determine their strength skew and to estimate the minimum functional voltage (V MIN ) degradation; (3) use the sensed values to estimate data retention voltage (DRV) and read access time (T ACC ); and (4) use the information on V TH values and skews across bitcells to create recovery vectors which can be used to recover the aged PMOSs and thereby improve the robustness and performance of the bitcells.
- V MIN minimum functional voltage
- DDRV data retention voltage
- T ACC read access time
- the memory device includes an array 102 of bitcells, a sensor header 104 , an analog multiplexer 106 , an amplifier 108 , bitline drivers 110 (which can include drivers 158 , 160 , 162 , 164 , 166 , 168 , 170 , and 172 ), sense amplifiers switches 112 (which can include switches 174 , 176 , 178 , 180 , 182 , 184 , 186 , and 188 ), sense amplifiers 114 (which can include sense amplifiers 190 , 192 , and 194 ), output SR latch 116 , word line decoder 118 , control logic 120 , scan chain 122 , and V SS gating circuit 99 .
- bitline drivers 110 which can include drivers 158 , 160 , 162 , 164 , 166 , 168 , 170 , and 172
- sense amplifiers switches 112 which can include switches 174 , 176 , 178 , 180 , 182
- array 102 of bitcells can include any suitable number of bitcells.
- array 102 can include a 32 by 32 array of bitcells.
- Each bitcell can be any suitable type of bitcell.
- each bitcell can be a six transistor (6T) bitcell. More particularly, for example, such a bitcell C 3,6 can include a transistor PL 130 , a transistor PR 132 , a transistor AL 134 , a transistor AR 136 , a transistor NL 138 , and a transistor NR 140 , which can be connected as shown in FIG. 1 , in some embodiments.
- Voltage supply lines can be provided between columns of cells in array 102 to power to the cells in the corresponding columns.
- One side of these supply lines can be connected to a sensor header, which can include a header transistor HL or HR (e.g., transistors 142 , 146 , 150 , and 154 ) and a bypass switch (e.g., switches 144 , 148 , 152 , and 156 ) for each supply line.
- a header transistor HL or HR e.g., transistors 142 , 146 , 150 , and 154
- bypass switch e.g., switches 144 , 148 , 152 , and 156
- bypass switches 144 , 148 , 152 , and 156 can be closed to provide power from V DD to the supply lines.
- a bitcell (e.g., cell C 3,6 in FIG. 1 ) can be configured into two V TH sensors.
- the two bypass switches corresponding to the bitcell e.g., switches 148 and 152
- the bitlines corresponding to the cell e.g., BL 6 and BLB 6
- the bitlines corresponding to the cell can be connected to ground by suitable drivers (e.g., drivers 164 and 166 ) of bitline driver 110 .
- transistor PL 130 can represent transistor PL 130 of FIG. 1
- transistor PR 232 can represent transistor PR 132 of FIG. 1
- transistor HL 246 can represent transistor HL 146 of FIG. 1
- transistor HR 250 can represent transistor HR 150 of FIG. 1 .
- transistors HL and transistors HR can be formed from four fingers that are 480 nm long and 160 nm wide
- the transistors PL and PR can be formed from one finger that is 160 nm long and 80 nm wide.
- V L at node 196 (V DD6 ) and the voltage V R at node 198 (V DD7 ) are linear functions of the threshold voltage (Vi) of transistor PL 130 and transistor PR 132 , respectively, of bitcell C 3,6 .
- Analytical expressions for V L an V R can be derived based on the fundamentals of a compact voltage reference as described in M. Seok, et al., “A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5V,” IEEE Journal of Solid-State Circuits, vol. 47, no. 10, pp. 2534-2545, October 2012, which is hereby incorporated by reference herein in its entirety. More particularly, V L can be represented by:
- V L ⁇ V thPL ⁇ + n PL ⁇ [ ⁇ t ⁇ ⁇ l n ⁇ ( ⁇ HL ⁇ PL ⁇ n HL - 1 n PL - 1 ) + 1 n HL ⁇ ⁇ V thHL ⁇ ] .
- V R can be represented by:
- V R ⁇ V thPR ⁇ + n PR ⁇ [ ⁇ t ⁇ ⁇ l n ⁇ ( ⁇ HR ⁇ PR ⁇ n HR - 1 n PR - 1 ) + 1 n HR ⁇ ⁇ V thHR ⁇ ]
- V thPL is the threshold voltage of transistor PL 130 ;
- V thPR is the threshold voltage of transistor PR 132 ;
- V thHL is the threshold voltage of transistor HL 146 ;
- V thHR is the threshold voltage of transistor HR 150 ;
- n PI is a subthreshold slope factor of transistor PL 130 ;
- n PR is a subthreshold slope factor of transistor PR 132 ;
- n HL is a subthreshold slope factor of transistor HL 146 ;
- n HR is a subthreshold slope factor of transistor HR 150 ;
- ⁇ PL is u*Cox*W/L (where u is mobility, Cox is gate oxide capacitance density, W and L are width and length) of transistor PL 130 ;
- ⁇ PR is u*Cox*W/L (where u is mobility, Cox is gate oxide capacitance density, W and L are width and length) of transistor PR 132 ;
- ⁇ HL is u*Cox*W/L (where u is mobility, Cox is gate oxide capacitance density, W and L are width and length) of transistor HL 146 ;
- ⁇ HR is u*Cox*W/L (where u is mobility, Cox is gate oxide capacitance density, W and L are width and length)of transistor HR 150 ;
- n PL [ ⁇ t ⁇ ⁇ l n ⁇ ( ⁇ HL ⁇ PL ⁇ n HL - 1 n PL - 1 ) + 1 n HL ⁇ ⁇ V thHL ⁇ ] ⁇ ⁇ and ⁇ n PR ⁇ [ ⁇ t ⁇ ⁇ l n ⁇ ( ⁇ HR ⁇ PR ⁇ n HR - 1 n PR - 1 ) + 1 n HR ⁇ ⁇ V thHR ⁇ ]
- V L and V R are approximately equal in a typical bitcell, the difference between V L and V R can be represented as:
- V D V L ⁇ V R ⁇
- V L and V R are linear functions of the threshold voltages of transistor PL 130 (V thPL ) and transistor PR 130 (V thPR ), and not a strong function of temperature and voltage.
- V thPL threshold voltages of transistor PL 130
- V thPR transistor PR 130
- the sensor header transistors HL and HR can be sized, in some embodiments, so that the voltages V L and V R are sensitive mostly to V thPL and V thPR , respectively.
- the circuit can be configured to mitigate leakage current from nearby bitcells in some embodiments.
- a cell e.g., C 3,6
- the V SS voltages from the unselected rows can be gated during sensing. In some embodiments, this can be accomplished using V SS gating circuit 99 shown in FIG. 1 .
- bitlines in the adjacent columns can be pulled to V DD by the drivers (e.g., drivers 160 , 162 , 168 , and 170 ) in bitline drivers 110 to turn off the PMOS devices in the adjacent cells (e.g., cells C 3,5 and C 3,7 ). This can also help reduce pass-transistor leakage in the other rows of the column.
- the voltages V L and V R can be transferred via 32-to-1 analog multiplexer 106 through an amplifier 108 to an analog-to-digital conversion for digitization and subsequent processing by any suitable component (such as a microprocessor), in some embodiments.
- voltages V L , and V R can also be compared via sense amplifiers (SA) 114 that are normally part of an SRAM device.
- SA sense amplifiers
- sense amplifier switches e.g., switches 174 , 176 , 178 , and 180
- the voltage supply lines e.g., V DD5 , V DD6 , V DD7 , and V DD8
- the outputs of the sense amplifiers can be combined by sense amplifiers switches (e.g., switches 182 , 184 , 186 , and 188 ) so that a combined output of two or more sense amplifiers can be measured.
- FIG. 3 illustrates an example of how the two cycles can be implemented. As shown, during an even cycle, columns 0 , 2 , 4 , 6 , . . . , 30 can be measured. During an odd cycle, columns 1 , 3 , 5 , 7 , . . . , 31 can be measured.
- bitlines BL 6 , BLB 6 , BL 7 , and BLB 7 are disconnected from VDD (as shown by the switches at the top of the figure), bitline BL 6 is connected to VDD 5 , bitline BLB 6 is connected to VDD 6 , BL 7 is connected to VDD 7 , and BLB 7 is connected to VDD 8 .
- sense amplifier six SA 6
- SA 7 sense amplifier seven
- sense amplifier five would also be connected to VDD 5 and VDD 6 and that sense amplifier eight (SA 8 ) would also be connected to VDD 7 and VDD 8 .
- sense amplifiers five and six would be measuring the same two bitlines (i.e., VDD 5 and VDD 6 ) and sense amplifiers seven and eight would be measuring the same two bitlines (i.e., VDD 7 and VDD 8 ).
- the sense amplifier size can be increased by 1.5 ⁇ over what might be used in a similar memory device (not including the VL and VR measurement mechanisms described herein) for further offset mitigation.
- the operational waveforms during EC mode in some embodiments are shown FIG. 4 .
- the word line e.g., WL 3
- the word line can be asserted a half-cycle earlier than during normal operation to provide enough settling time for VDD 6 and VDD 7 before the SAs compare V L and V R .
- any suitable amplifier with accuracy better than the sense amplifiers can be coupled to the sense amplifier inputs via an analog multiplexer and used to measure the difference between V L and V R.
- a memory device 500 can include an array 102 of bitcells, bitline circuts 110 (which can include bitline pre-chargers, write drivers, sensing amplifiers and/or any other suitable components), a word line decoder 118 , control logic 120 , a scan chain 122 , a sensor switch network (SSN) 503 , and a zero-V TH thick-oxide NMOS transistor (referred to herein as a sensor) 505 , and a bitline multiplexer (BLMUX) 507 .
- FIG. 6 shows sensor switch network 503 , sensor 505 , and BLMUX 507 in more detail.
- bitlines BL 0 . . . BL 31 and bitlines BLB 0 . . . BLB 31 are received by BLMUX 507 .
- One of each of bitlines BL 0 . . . BL 31 and bitlines BLB 0 . . . BLB 31 are selected by BLMUX 507 in response to values on DIN.
- BMEN bitline multiplexer enable signal
- BLMUX outputs the selected ones of bitlines BL 0 . . . BL 31 and bitlines BLB 0 . . . BLB 31 as BLS and BLBS.
- BLMUX 507 can be implemented by providing a set (in the figure, 32) branches 771 that are connected in parallel to BLS node 641 , BLBS node 643 , and BMEN node 639 .
- One of each of BL 0 . . . BL 31 , BLB 0 . . . BLB 31 , and DIN 0 . . . DIN 31 are provided to transistor 773 , transistor 775 , and AND gate 777 , respectively, of each branch as shown.
- Sensor switch network 503 receives BLS and BLBS and connects them to sensor 505 , V SEN , V TEST , and/or ground based upon signals S 0 . . . S 7 and P 0 . . . P 3 , which turn on one or more of transistors S[ 0 ] 609 , S[ 1 ] 611 , S[ 2 ] 613 , S[ 3 ] 615 , S[ 4 ] 617 , S[ 5 ] 619 , S[ 6 ] 621 , and S[ 7 ] 623 and transistors P[ 0 ] 625 , P[ 1 ] 627 , P[ 2 ] 629 , and P[ 3 ] 631 , respectively.
- the V CELL , V NW , and V SS connections to each bitcell can be connected to power switch network (PSN) 757 as shown in FIG. 7 in some embodiments.
- the PSN can control whether V cELL is connected to V TEST or ground, whether V Nw is connected to V TEST or V SEN , and whether V SS is connected to V TEST or ground.
- PSN 757 includes transistors 763 , 765 , 767 , and 769 which are connected as shown and controlled by signals SP and SN (SNb).
- power gating switches 759 and 761 can be provided to control power to the memory device.
- V TEST can be set to 0.6V or any other suitable voltage in some embodiments.
- BLMUX 507 , SSN 503 , and PSN 757 can select one of transistor PL 130 , transistor PR 132 , transistor AL 134 , transistor AR 136 , transistor NL 138 , and transistor NR 140 as a device under test (DUT) as shown in the following table:
- DUT SSN conf. (ON) BMEN/SP/SNb PL S[0,3,4,7] P[1,2] 1/1/1 PR S[1,2,4,7] P[1,2] AL S[0,3,5,6] P[2,3] 1/0/1 AR S[1,2,5,6] P[2,3] NL S[0,3,5,6] P[0,3] 1/0/0 NR S[1,2,5,6] P[0,3]
- transistor NR 140 is selected as the device under test 779 and connected to sensor 505 .
- V BL (BL 6 ) is coupled to V TEST ;
- V BLB (BLB 6 ) becomes V D (the drain of the sensor);
- V S (the source of the sensor) becomes ground.
- the output voltage of the circuits, V SEN becomes a linear function of the V TH of transistor NR 140 , and also generally insensitive to temperature variation, based on the fundamentals of the voltage reference circuits. Because V SEN is a linear function of V TH , once a relationship between V SEN and V TH is determined (e.g., by testing), a measurement of V SEN can be used to estimate V TH .
- the inputs can be configured for sensing transistor PR 132 .
- transistor PR 132 becomes device under test 781 and is connected to sensor 505 as shown.
- the bias current of the V TH sensor circuits can be provided at the ⁇ A level to make sensing robust against gate and sub-threshold leakage of nearby devices. This also allows the BLMUX and the PSN to be implemented using thin-oxide devices, in some embodiments. When sensing PMOS, the PSN also connects the n-well of the array (V NW ) to V SEN for removing the body effect, improving robustness against temperature variation.
- data retention voltage can be estimated based on sensed values as input over a memory device's lifetime.
- DRV data retention voltage
- six sensor outputs 785 per bitcell can be taken as input and used to generate the estimates of DRV polarity (Y 1 ) and magnitude (Y 2 ) using a DRV estimator 783 .
- the DRV polarity (Y 1 ) represents the DRV's skew. For example, the polarity is negative if a bitcell is less likely to retain 0 than 1 at Q node at a low V DD value.
- X 1 ( V PL ⁇ V PR , V NL ⁇ V NR );
- V PL is the value of V SEN when transistor PL is the device under test
- V PR is the value of V SEN when transistor PR is the device under test
- V AL is the value of V SEN when transistor AL is the device under test
- V AR is the value of V SEN when transistor AR is the device under test
- V NL is the value of V SEN when transistor NL is the device under test.
- V NR is the value of V SEN when transistor NR is the device under test.
- the sensor outputs can be used to calculate X 1 and X 2 at 795 and 797 , respectively.
- X 1 , X 2 , A, and B can then be used to calculate Y 1 and Y 2 at 799 and 851 .
- Y 1 is then thresholded by 853 (so that the polarity is considered to be+if Y 1 is over a threshold and -otherwise) and the estimated DRV polarity Y 1 and the estimated DRV magnitude Y 2 are provided at 855 and 857 , respectively.
- read access time can also be estimated by taking sensed values as input over a memory device's lifetime.
- T ACC is a function of the relative strength between PU (i.e., transistor PL or PR), PD (i.e., transistor NL or NR), and AX (transistor AL or AR) of a bitcell and the sense amplifier's input-referred offset voltage (V OS ).
- PU i.e., transistor PL or PR
- PD i.e., transistor NL or NR
- AX transistor AL or AR
- V OS input-referred offset voltage
- T ACC In order to estimate T ACC , first, using a reference memory device, two matrices, C and D, can be found via linear regression using measured T ACCS , polarity feature vectors X 3 , and magnitude feature vectors X 4 of 100 bitcells from the reference memory device. The polarity feature vector and the magnitude feature vector for the cells can then be calculated as follows:
- X 3 ( V PL ⁇ V PR , V NL ⁇ V NR , V AL ⁇ V AR , V OS );
- X 4 (max( V PL , V PR ), max( V NL , N NR ), max( V AL , V NR ), max( V AL , V AR ), max( V OS )).
- the sensor outputs and sense amplifier offset information can be used to calculate X 3 and X 4 at 861 .
- X 3 , X 4 , C, and D can then be used to calculate Y 3 and Y 4 at 863 and 865 .
- the estimated T ACC polarity Y 3 and the estimated T ACC magnitude Y 4 can then be provided at 867 .
- a configurable delay line (e.g., as shown in FIG. 13 ) can be used to add delays to a sense amplifier's enable signal (sae) to provide a delayed sense amplifier enable signal (saed). The delay be this delay line can then be changed and T ACC measured repeatedly to observe the impact of different delays.
- an example of a configurable delay line 869 can include a plurality of buffer chains 871 , 875 , and 879 , where each buffer includes a certain delay factor (e.g., 1, 4, and 16 as illustrated for the buffers in chains 871 , 875 , and 879 , respectively).
- a certain delay factor e.g. 1, 4, and 16 as illustrated for the buffers in chains 871 , 875 , and 879 , respectively.
- multiplexers 873 , 877 , and 881 can be used to select a suitably delayed signal from a point in the preceding chain and provide it to the next chain or the output (saed).
- Strength skews of bitcells in an SRAM device can be measured using the mechanisms described herein. These measurements can show inherent skews incurred by process variations and/or any other skews. Based on the measured skew, recovery vectors can be determined and applied to some of the bitcells, in some embodiments.
- any suitable action can be taken. For example, in some embodiments, the bitcell can be flagged as not-to-be used.
- recovery vectors can be applied to a bitcell to counter NBTI degradation. These recovery vectors can be applied, for example, as described in S. V. Kumar, et al., “Impact of NBTI on SRAM Read Stability and Design for Reliability,” In International Symposium on Quality Electronic Design, pp. 210-218, 2006, which is hereby incorporated by reference herein in its entirety.
- these mechanisms can be used with other forms of bitcells in some embodiments.
- these mechanisms can be used with 4-transistor (4-T), 5-T, 8-T, 7-T, 8-T, 10-T, 12-T, 14-T, and many other SRAM circuit designs.
- the header devices e.g., transistors HL and HR and bypass switches
- the word lines e.g., WL 3
- the bitlines drivers e.g., for BL 6 , BLB 6
- the bitline circuits can be controlled by any suitable hardware, software, firmware, and/or look-up tables.
- a microprocessor running any suitable instructions can control the configuration of the sensors, measurements, and recovery processes described herein.
- any suitable computer readable media can be used for storing instructions for performing the processes described herein.
- computer readable media can be transitory or non-transitory.
- non-transitory computer readable media can include media such as magnetic media (such as hard disks, floppy disks, and/or any other suitable media), optical media (such as compact discs, digital video discs, Blu-ray discs, and/or any other suitable optical media), semiconductor media (such as flash memory, electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and/or any other suitable semiconductor media), any suitable media that is not fleeting or devoid of any semblance of permanence during transmission, and/or any suitable tangible media.
- transitory computer readable media can include signals on networks, in wires, conductors, optical fibers, circuits, any suitable media that is fleeting and devoid of any semblance of permanence during transmission, and/or any suitable intangible
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Abstract
Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.
Description
- The application is a continuation of U.S. patent application Ser. No. 15/018,834, filed Feb. 8, 2016, which claims the benefit of U.S. Provisional Patent Application No. 62/113,392, filed Feb. 7, 2015, each of which is hereby incorporated by reference herein in its entirety.
- This invention was made with government support under contract number 1453142 awarded by National Science Foundation. The government has certain rights in the invention.
- Static Random Access Memory (SRAM) devices have sensitive circuitry and often operate with high switching activity and at high temperature. This makes the transistors that make up their bitcells particularly vulnerable to various aging mechanisms including Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) degradation. NBTI and PBTI change transistor threshold voltages (VTH) over time and are major reliability concerns in modern system on a chip (SoC) designs. Since such aging effects can degrade critical robustness and performance metrics, such as data retention voltage (DRV) and read access time (TACC), it is highly desirable to provide mechanism to enable monitoring and managing aging effects upon memory devices.
- Circuit, methods, and media for detecting and countering aging degradation in memory cells are provided. In some embodiments, circuits for measuring threshold voltages of transistors in a memory device bitcell are provided, the circuits comprising: a multiplexer that has a plurality of pairs of inputs, each connected to a different pair of bitlines of the memory device, and that has an output connected to a pair of bitline terminals; a first plurality of interconnected switches that are connected to a ground, a test voltage, a sense voltage node (VSEN), the pair of bitline terminals, and a pair of sensor terminals; a second plurality of interconnected switches that are connected to the test voltage, the ground, the sense voltage node (VSEN), a positive voltage connection, an n-well connection, and a ground power connection of the bitcell; and a zero-VTH thick-oxide NMOS transistor having a gate, a drain, and a source, wherein the gate is connected to the source, the source is connected to the gate and one of the pair of sensor terminals; and the drain is connected to another of the pair of sensor terminals, wherein, when in a first configuration of the multiplexer, the first plurality of interconnected switches, and the second plurality of interconnected switches, a gate of a first transistor of the bitcell and one of a drain and a source of the first transistor of the bitcell are coupled to the test voltage, another of the drain and the source of the first transistor of the bitcell is coupled to the drain of the zero-VTH thick-oxide NMOS transistor, and the gate and the source of the zero-VTH thick-oxide NMOS transistor are coupled to ground.
-
FIG. 1 is an example of a memory device include mechanisms for monitoring degradation effects on the memory device's bitcells in accordance with some embodiments. -
FIG. 2 is an example of a model of a configuration of four transistors of the memory deviceFIG. 1 when that device is in a certain configuration in accordance with some embodiments. -
FIG. 3 is an example of a diagram showing connections between power supply lines and sense amplifiers in even cycles and odd cycles in accordance with some embodiments. -
FIG. 4 is an example of a timing diagram of signals of the memory device ofFIG. 1 during an even cycle in accordance with some embodiments. -
FIG. 5 is another example of a memory device include mechanisms for monitoring degradation effects on the memory device's bitcells in accordance with some embodiments. -
FIG. 6 is an example of a bitline multiplexer, a sensor switch network, and a sensor that can be used in the memory device ofFIG. 5 in accordance with some embodiments. -
FIG. 7 is an example of a power switch network that can be used in conjunction with the memory device ofFIG. 5 in accordance with some embodiments. -
FIG. 8 is an example of a bitline multiplexer that can be used in the memory device ofFIG. 5 in accordance with some embodiments. -
FIG. 9 is an example of a model of the connections between a device under test and a sensor in a certain configuration of the memory device ofFIG. 5 in accordance with some embodiments. -
FIG. 10 is an example of another model of the connections between a device under test and a sensor in a certain configuration of the memory device ofFIG. 5 in accordance with some embodiments. -
FIG. 11 is an example of a block diagram of a data retention voltage (DRV) estimator that can be implemented in conjunction with the memory device ofFIG. 5 in accordance with some embodiments. -
FIG. 12 is an example of a block diagram of a read access time (TACC) estimator that can be implemented in conjunction with the memory device ofFIG. 5 in accordance with some embodiments. -
FIG. 13 is an example of a configurable delay line in accordance with some embodiments. - In accordance with some embodiments, mechanisms, which can include circuits, methods, and media, for detecting and countering aging degradation in memory cells are provided. In some embodiments, these mechanisms can include in-situ techniques that sense the threshold voltage (VTH) of bitcell transistors and can operate in-field by sensing VTH values robustly across temperature and voltage variations. In some embodiments, these techniques can: (1) be used to sense VTH values periodically (e.g., every several months) for evaluating the amount and the rate of NBTI and/or PBTI degradation; (2) be used to sense VTH values between two PMOSs in a bitcell to determine their strength skew and to estimate the minimum functional voltage (VMIN) degradation; (3) use the sensed values to estimate data retention voltage (DRV) and read access time (TACC); and (4) use the information on VTH values and skews across bitcells to create recovery vectors which can be used to recover the aged PMOSs and thereby improve the robustness and performance of the bitcells.
- Turning to
FIG. 1 , amemory device 100 in accordance with some embodiments is shown. As illustrated, the memory device includes anarray 102 of bitcells, asensor header 104, ananalog multiplexer 106, anamplifier 108, bitline drivers 110 (which can includedrivers switches sense amplifiers output SR latch 116,word line decoder 118,control logic 120,scan chain 122, and VSS gating circuit 99. - In some embodiments,
array 102 of bitcells can include any suitable number of bitcells. For example, in some embodiments,array 102 can include a 32 by 32 array of bitcells. Each bitcell can be any suitable type of bitcell. For example, in some embodiments, each bitcell can be a six transistor (6T) bitcell. More particularly, for example, such a bitcell C3,6 can include atransistor PL 130, atransistor PR 132, atransistor AL 134, atransistor AR 136, atransistor NL 138, and atransistor NR 140, which can be connected as shown inFIG. 1 , in some embodiments. - Voltage supply lines (e.g., VDD5, VDD6, VDD7, and VDD8) can be provided between columns of cells in
array 102 to power to the cells in the corresponding columns. One side of these supply lines can be connected to a sensor header, which can include a header transistor HL or HR (e.g.,transistors switches memory device 102 is being used for normal memory purposes,bypass switches - As shown in
FIG. 1 , in some embodiments, a bitcell (e.g., cell C3,6 inFIG. 1 ) can be configured into two VTH sensors. In order to enable such a configuration, the two bypass switches corresponding to the bitcell (e.g.,switches 148 and 152) can be disabled (i.e., opened), a word line corresponding to the cell (e.g., WL3) can be asserted, and the bitlines corresponding to the cell (e.g., BL6 and BLB6) can be connected to ground. The bitlines corresponding to the cell can be connected to ground by suitable drivers (e.g.,drivers 164 and 166) ofbitline driver 110. - When
device 100 is configured as described above, the circuit containingtransistor PL 130,transistor PR 132,transistor HL 146, and transistor HR 150 can be represented by the circuit shown inFIG. 2 . As illustrated inFIG. 2 ,transistor PL 230 can representtransistor PL 130 ofFIG. 1 ,transistor PR 232 can representtransistor PR 132 ofFIG. 1 ,transistor HL 246 can representtransistor HL 146 ofFIG. 1 , andtransistor HR 250 can represent transistor HR 150 ofFIG. 1 . As shown inFIG. 2 , transistors HL and transistors HR can be formed from four fingers that are 480 nm long and 160 nm wide, and the transistors PL and PR can be formed from one finger that is 160 nm long and 80 nm wide. - Returning to
FIG. 1 , the voltage VL at node 196 (VDD6) and the voltage VR at node 198 (VDD7) are linear functions of the threshold voltage (Vi) oftransistor PL 130 andtransistor PR 132, respectively, of bitcell C3,6. Analytical expressions for VL an VR can be derived based on the fundamentals of a compact voltage reference as described in M. Seok, et al., “A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5V,” IEEE Journal of Solid-State Circuits, vol. 47, no. 10, pp. 2534-2545, October 2012, which is hereby incorporated by reference herein in its entirety. More particularly, VL can be represented by: -
- Likewise, VR can be represented by:
-
- where:
- VthPL is the threshold voltage of
transistor PL 130; - VthPR is the threshold voltage of
transistor PR 132; - VthHL is the threshold voltage of
transistor HL 146; - VthHR is the threshold voltage of transistor HR 150;
- nPI, is a subthreshold slope factor of
transistor PL 130; - nPR is a subthreshold slope factor of
transistor PR 132; - nHL is a subthreshold slope factor of transistor HL146;
- nHR is a subthreshold slope factor of transistor HR 150;
- φt is a thermal voltage (=kT/q where k is boltzman constant, T is temperature, q is electron charge);
- βPL is u*Cox*W/L (where u is mobility, Cox is gate oxide capacitance density, W and L are width and length) of
transistor PL 130; - βPR is u*Cox*W/L (where u is mobility, Cox is gate oxide capacitance density, W and L are width and length) of
transistor PR 132; - βHL is u*Cox*W/L (where u is mobility, Cox is gate oxide capacitance density, W and L are width and length) of
transistor HL 146; and - βHR is u*Cox*W/L (where u is mobility, Cox is gate oxide capacitance density, W and L are width and length)of transistor HR 150;
- Because
-
- are approximately equal in a typical bitcell, the difference between VL and VR can be represented as:
-
V D =V L −V R ≈|V thPL |−|V thPR|. - The analytical expressions for VL and VR are linear functions of the threshold voltages of transistor PL 130 (VthPL) and transistor PR 130 (VthPR), and not a strong function of temperature and voltage. Thus, the described configuration can be used to robustly monitor the VthPL and VthPR under operational temperature and voltage variations by monitoring VL and VR, respectively.
- The sensor header transistors HL and HR can be sized, in some embodiments, so that the voltages VL and VR are sensitive mostly to VthPL and VthPR, respectively.
- In some embodiments, the sensors can also estimate the VMIN changes due to NBTI degradation. If a bitcell has Q=1 and QB=0, transistor PL ages and the bitcell flips to Q=0 at a higher VMIN.
- To improve the accuracy of the threshold voltage estimates (based on VL, and VR) in a bitcell, the circuit can be configured to mitigate leakage current from nearby bitcells in some embodiments. For example, in some embodiments, when a cell (e.g., C3,6) is configured for sensing, it may be desirable to prevent cells from the unselected rows from contributing leakage currents to VL, and VR. To reduce those leakage currents, in some embodiments, the VSS voltages from the unselected rows can be gated during sensing. In some embodiments, this can be accomplished using VSS gating circuit 99 shown in
FIG. 1 . In some embodiments, it may also be desirable to mitigate leakage currents from adjacent cells of the same row (e.g., cells C3,5, C3,7), which may induce leakage currents depending on their stored bits. To mitigate such leakage currents, in some embodiments, bitlines in the adjacent columns (e.g., BL5, BLB5, BL7, BLB7) can be pulled to VDD by the drivers (e.g.,drivers bitline drivers 110 to turn off the PMOS devices in the adjacent cells (e.g., cells C3,5 and C3,7). This can also help reduce pass-transistor leakage in the other rows of the column. - The voltages VL and VR can be transferred via 32-to-1
analog multiplexer 106 through anamplifier 108 to an analog-to-digital conversion for digitization and subsequent processing by any suitable component (such as a microprocessor), in some embodiments. - In some embodiments, besides being digitized with an analog-to-digital converter, voltages VL, and VR can also be compared via sense amplifiers (SA) 114 that are normally part of an SRAM device. This approach can determine the PMOS strength skew of a line of bitcells at a higher throughput with the parallel use of any suitable number of sense amplifiers.
- In order to connect voltages VL and VR to the sense amplifiers, sense amplifier switches (e.g., switches 174, 176, 178, and 180) can be provided to connect the voltage supply lines (e.g., VDD5, VDD6, VDD7, and VDD8) to the sense amplifiers (e.g.,
sense amplifiers - To generate a word-size (32 bits in the device of
FIG. 1 ) recovery vector, the techniques described above can take two cycles: one for the even columns (EC) and the other for the odd columns (OC), since, as described above, measurements cannot be made from two adjacent bitcells simultaneously.FIG. 3 illustrates an example of how the two cycles can be implemented. As shown, during an even cycle,columns columns - When in an even cycle, the switches marked “EC” in
FIG. 3 are closed and the switches marked “OC” inFIG. 3 are open. Thus, in when in an even cycle, as shown inFIG. 3 , the bitlines BL6, BLB6, BL7, and BLB7 are disconnected from VDD (as shown by the switches at the top of the figure), bitline BL6 is connected to VDD6, bitline BLB6 is connected to VDD7, BL7 is connected to VDD6, and BLB7 is connected to VDD7. In this way, sense amplifier six (SA6) and sense amplifier seven (SA7) are each connected to VDD6 and VDD7. Thus, each of sense amplifiers six and seven is measuring the same two bitlines (i.e., VDD6 and VDD7). - Similarly, when in an odd cycle, the switches marked “OD” in
FIG. 3 are open and the switches marked “OC” inFIG. 3 are closed. Thus, in when in an odd cycle, the bitlines BL6, BLB6, BL7, and BLB7 are disconnected from VDD (as shown by the switches at the top of the figure), bitline BL6 is connected to VDD5, bitline BLB6 is connected to VDD6, BL7 is connected to VDD7, and BLB7 is connected to VDD8. In this way, sense amplifier six (SA6) is connected to VDD5 and VDD6 and sense amplifier seven (SA7) is connected to VDD7 and VDD8. Though not shown inFIG. 3 , it follows that sense amplifier five (SA5) would also be connected to VDD5 and VDD6 and that sense amplifier eight (SA8) would also be connected to VDD7 and VDD8. Thus, sense amplifiers five and six would be measuring the same two bitlines (i.e., VDD5 and VDD6) and sense amplifiers seven and eight would be measuring the same two bitlines (i.e., VDD7 and VDD8). - Using two sense amplifiers per column (one from its own column and the other from an adjacent column) in this way can reduce input-referred offset. In some embodiments, the sense amplifier size can be increased by 1.5× over what might be used in a similar memory device (not including the VL and VR measurement mechanisms described herein) for further offset mitigation.
- The operational waveforms during EC mode in some embodiments are shown
FIG. 4 . As illustrated, the word line (e.g., WL3) can be asserted a half-cycle earlier than during normal operation to provide enough settling time for VDD6 and VDD7 before the SAs compare VL and VR. - Additionally or alternatively to using sense amplifiers to compare VL and VR as described above, in some embodiments any suitable amplifier with accuracy better than the sense amplifiers can be coupled to the sense amplifier inputs via an analog multiplexer and used to measure the difference between VL and VR.
- Turning to
FIG. 5 , another approach to determining threshold voltage VTH degradation of memory cell transistors in accordance with some embodiments is shown. As illustrated, amemory device 500 can include anarray 102 of bitcells, bitline circuts 110 (which can include bitline pre-chargers, write drivers, sensing amplifiers and/or any other suitable components), aword line decoder 118,control logic 120, ascan chain 122, a sensor switch network (SSN) 503, and a zero-VTH thick-oxide NMOS transistor (referred to herein as a sensor) 505, and a bitline multiplexer (BLMUX) 507. -
FIG. 6 showssensor switch network 503,sensor 505, andBLMUX 507 in more detail. As illustrated, bitlines BL0 . . . BL31 and bitlines BLB0 . . . BLB31 are received byBLMUX 507. One of each of bitlines BL0 . . . BL31 and bitlines BLB0 . . . BLB31 are selected byBLMUX 507 in response to values on DIN. When a bitline multiplexer enable signal (BMEN) is asserted, BLMUX outputs the selected ones of bitlines BL0 . . . BL31 and bitlines BLB0 . . . BLB31 as BLS and BLBS. - An example of
BLMUX 507 is shown inFIG. 8 . As illustrated,BLMUX 507 can be implemented by providing a set (in the figure, 32)branches 771 that are connected in parallel toBLS node 641,BLBS node 643, andBMEN node 639. One of each of BL0 . . . BL31, BLB0 . . . BLB31, and DIN0 . . . DIN31 are provided totransistor 773,transistor 775, and ANDgate 777, respectively, of each branch as shown. -
Sensor switch network 503 receives BLS and BLBS and connects them tosensor 505, VSEN, VTEST, and/or ground based upon signals S0 . . . S7 and P0 . . . P3, which turn on one or more of transistors S[0] 609, S[1] 611, S[2] 613, S[3] 615, S[4] 617, S[5] 619, S[6] 621, and S[7] 623 and transistors P[0] 625, P[1] 627, P[2] 629, and P[3] 631, respectively. - The VCELL, VNW, and VSS connections to each bitcell can be connected to power switch network (PSN) 757 as shown in
FIG. 7 in some embodiments. The PSN can control whether VcELL is connected to VTEST or ground, whether VNw is connected to VTEST or VSEN, and whether VSS is connected to VTEST or ground. As illustrated,PSN 757 includestransistors SN (SNb). As also shown inFIG. 7 , power gating switches 759 and 761 can be provided to control power to the memory device. VTEST can be set to 0.6V or any other suitable voltage in some embodiments. - By configuring the inputs described above,
BLMUX 507,SSN 503, andPSN 757 can select one oftransistor PL 130,transistor PR 132,transistor AL 134,transistor AR 136, transistor NL138, andtransistor NR 140 as a device under test (DUT) as shown in the following table: -
DUT SSN conf. (ON) BMEN/SP/SNb PL S[0,3,4,7] P[1,2] 1/1/1 PR S[1,2,4,7] P[1,2] AL S[0,3,5,6] P[2,3] 1/0/1 AR S[1,2,5,6] P[2,3] NL S[0,3,5,6] P[0,3] 1/0/0 NR S[1,2,5,6] P[0,3] - More particularly, for example, to select
transistor NR 140 as the device under test: (1) the PSN connects the power nodes of the array (VCELL, VNW, and VSS) to VTEST (0.6V) by setting SP=0 and SNb=0; (2) the word-line (WL3), the input data bus (DIN), and the BLMUX enable signal (BMEN) are set to 1, 00000010 . . . 0, 1, respectively, to transfer the voltages of the bitlines of C3,6 (BL6, BLB6) to the SSN via the BLMUX; and (3) the SSN is configured by turning on S[1,2,5,6] and P[0,3]. As a result, as shown inFIG. 9 ,transistor NR 140 is selected as the device undertest 779 and connected tosensor 505. Specifically, as shown inFIG. 6 , VBL (BL6) is coupled to VTEST; VBLB (BLB6) becomes VD (the drain of the sensor); VS (the source of the sensor) becomes ground. The output voltage of the circuits, VSEN, becomes a linear function of the VTH oftransistor NR 140, and also generally insensitive to temperature variation, based on the fundamentals of the voltage reference circuits. Because VSEN is a linear function of VTH, once a relationship between VSEN and VTH is determined (e.g., by testing), a measurement of VSEN can be used to estimate VTH. - Similarly, as described above, the inputs can be configured for sensing
transistor PR 132. When the BLMUX, the PSN, and the SSN are properly configured, as shown inFIG. 10 ,transistor PR 132 becomes device undertest 781 and is connected tosensor 505 as shown. - In some embodiments, the bias current of the VTH sensor circuits can be provided at the μA level to make sensing robust against gate and sub-threshold leakage of nearby devices. This also allows the BLMUX and the PSN to be implemented using thin-oxide devices, in some embodiments. When sensing PMOS, the PSN also connects the n-well of the array (VNW) to VSEN for removing the body effect, improving robustness against temperature variation.
- In some embodiments, data retention voltage (DRV) can be estimated based on sensed values as input over a memory device's lifetime. As shown in
FIG. 11 , in order to estimate DRV, sixsensor outputs 785 per bitcell can be taken as input and used to generate the estimates of DRV polarity (Y1) and magnitude (Y2) using aDRV estimator 783. The DRV polarity (Y1) represents the DRV's skew. For example, the polarity is negative if a bitcell is less likely to retain 0 than 1 at Q node at a low VDD value. - In order to estimate DRV, first, using a reference memory device, two matrices, A and B, are found via
linear regression 793 using measuredDRVs 789, polarity feature vectors X1 at 883, and magnitude feature vectors X2 at 883 of 100 bitcells from the reference memory device using the equations shown inboxes -
X 1=(V PL −V PR , V NL −V NR); and -
X 2=(max(V PL V PR), max(V NL , V NR), max (V AL , V AR)), - where:
- VPL is the value of VSEN when transistor PL is the device under test;
- VPR is the value of VSEN when transistor PR is the device under test;
- VAL is the value of VSEN when transistor AL is the device under test;
- VAR is the value of VSEN when transistor AR is the device under test;
- VNL is the value of VSEN when transistor NL is the device under test; and
- VNR is the value of VSEN when transistor NR is the device under test.
- After aging a different memory device (e.g., through normal use or using an accelerated aging test) and measuring
sensor outputs 785 for the device, the sensor outputs can be used to calculate X1 and X2 at 795 and 797, respectively. X1, X2, A, and B can then be used to calculate Y1 and Y2 at 799 and 851. Y1 is then thresholded by 853 (so that the polarity is considered to be+if Y1 is over a threshold and -otherwise) and the estimated DRV polarity Y1 and the estimated DRV magnitude Y2 are provided at 855 and 857, respectively. - In some embodiments, read access time (TACC) can also be estimated by taking sensed values as input over a memory device's lifetime. As shown in
FIG. 12 , in order to estimate TACC, sixsensor outputs 785 per bitcell and sense amplifier offset information can be taken as input and used to generate the estimates of TACC polarity (Y3) and TACC magnitude (Y4) using TACC estimator 859. TACC is a function of the relative strength between PU (i.e., transistor PL or PR), PD (i.e., transistor NL or NR), and AX (transistor AL or AR) of a bitcell and the sense amplifier's input-referred offset voltage (VOS). TACC polarity is 0 if reading Q=0 has larger TACC than reading Q=1. - In order to estimate TACC, first, using a reference memory device, two matrices, C and D, can be found via linear regression using measured TACCS, polarity feature vectors X3, and magnitude feature vectors X4 of 100 bitcells from the reference memory device. The polarity feature vector and the magnitude feature vector for the cells can then be calculated as follows:
-
X 3=(V PL −V PR , V NL −V NR , V AL −V AR , V OS); and -
X 4=(max(V PL , V PR), max(V NL , N NR), max(V AL , V NR), max(V AL , V AR), max(V OS)). - After aging a different memory device (e.g., through normal use or using an accelerated aging test) and measuring
sensor outputs 785 for the device, the sensor outputs and sense amplifier offset information can be used to calculate X3 and X4 at 861. X3, X4, C, and D can then be used to calculate Y3 and Y4 at 863 and 865. The estimated TACC polarity Y3 and the estimated TACC magnitude Y4 can then be provided at 867. - The polarity of TACC (Y3), which is 0 if reading Q=0 has larger TACC than reading Q=1, and the magnitude of TACC (Y4) can be provided at 867.
- To estimate the impact of VOS on TACC, a configurable delay line (e.g., as shown in
FIG. 13 ) can be used to add delays to a sense amplifier's enable signal (sae) to provide a delayed sense amplifier enable signal (saed). The delay be this delay line can then be changed and TACC measured repeatedly to observe the impact of different delays. - As shown in
FIG. 13 , an example of aconfigurable delay line 869 can include a plurality ofbuffer chains chains multiplexers - Strength skews of bitcells in an SRAM device can be measured using the mechanisms described herein. These measurements can show inherent skews incurred by process variations and/or any other skews. Based on the measured skew, recovery vectors can be determined and applied to some of the bitcells, in some embodiments.
- In some embodiments, if a bitcell is identified as having a given level of degradation, any suitable action can be taken. For example, in some embodiments, the bitcell can be flagged as not-to-be used. As another example, in some embodiments, recovery vectors can be applied to a bitcell to counter NBTI degradation. These recovery vectors can be applied, for example, as described in S. V. Kumar, et al., “Impact of NBTI on SRAM Read Stability and Design for Reliability,” In International Symposium on Quality Electronic Design, pp. 210-218, 2006, which is hereby incorporated by reference herein in its entirety.
- Although the mechanisms described herein are illustrated using a six transistor bit cell, these mechanisms can be used with other forms of bitcells in some embodiments. For example, these mechanisms can be used with 4-transistor (4-T), 5-T, 8-T, 7-T, 8-T, 10-T, 12-T, 14-T, and many other SRAM circuit designs.
- Although not shown in the figures, the header devices (e.g., transistors HL and HR and bypass switches), the word lines (e.g., WL3), the bitlines drivers (e.g., for BL6, BLB6), the bitline circuits, the VSS gating, the analog multiplexer, an analog-to-digital converter, the sense amplifier switches, the sense amplifiers, the output SR latch, the DRV estimator, the TACC estimator, and/or any other components can be controlled by any suitable hardware, software, firmware, and/or look-up tables. For example, in some embodiments, a microprocessor running any suitable instructions can control the configuration of the sensors, measurements, and recovery processes described herein.
- In some embodiments, any suitable computer readable media can be used for storing instructions for performing the processes described herein. For example, in some embodiments, computer readable media can be transitory or non-transitory. For example, non-transitory computer readable media can include media such as magnetic media (such as hard disks, floppy disks, and/or any other suitable media), optical media (such as compact discs, digital video discs, Blu-ray discs, and/or any other suitable optical media), semiconductor media (such as flash memory, electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and/or any other suitable semiconductor media), any suitable media that is not fleeting or devoid of any semblance of permanence during transmission, and/or any suitable tangible media. As another example, transitory computer readable media can include signals on networks, in wires, conductors, optical fibers, circuits, any suitable media that is fleeting and devoid of any semblance of permanence during transmission, and/or any suitable intangible media.
- The provision of the examples described herein (as well as clauses phrased as “such as,” “e.g.,” “including,” and the like) should not be interpreted as limiting the subject matter to the specific examples; rather, the examples are intended to illustrate only some of many possible aspects.
- Although the invention has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and the numerous changes in the details of implementation of the invention can be made without departing from the spirit and scope of the invention, which is limited only by the claims that follow. Features of the disclosed embodiments can be combined and rearranged in various ways.
Claims (1)
1. A circuit for measuring threshold voltages of transistors in a memory device bitcell, comprising:
a multiplexer that has a plurality of pairs of inputs, each connected to a different pair of bitlines of the memory device, and that has an output connected to a pair of bitline terminals;
a first plurality of interconnected switches that are connected to a ground, a test voltage, a sense voltage node (VsEN), the pair of bitline terminals, and a pair of sensor terminals;
a second plurality of interconnected switches that are connected to the test voltage, the ground, the sense voltage node (VsEN), a positive voltage connection, an n-well connection, and a ground power connection of the bitcell; and
a zero-VTH thick-oxide NMOS transistor having a gate, a drain, and a source, wherein the gate is connected to the source, the source is connected to the gate and one of the pair of sensor terminals; and the drain is connected to another of the pair of sensor terminals,
wherein, when in a first configuration of the multiplexer, the first plurality of interconnected switches, and the second plurality of interconnected switches, a gate of a first transistor of the bitcell and one of a drain and a source of the first transistor of the bitcell are coupled to the test voltage, another of the drain and the source of the first transistor of the bitcell is coupled to the drain of the zero-VTH thick-oxide NMOS transistor, and the gate and the source of the zero-VTH thick-oxide NMOS transistor are coupled to ground.
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US15/243,664 Abandoned US20160358672A1 (en) | 2015-02-07 | 2016-08-22 | Circuits, methods, and media for detecting and countering aging degradation in memory cells |
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KR20240008471A (en) * | 2022-07-12 | 2024-01-19 | (주)피델릭스 | Aging mornitoring circuit in semiconductor memeory device for mornitoring aging with changing in threshold voltage |
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US10223197B2 (en) | 2015-08-06 | 2019-03-05 | Nxp B.V. | Integrated circuit device and method for applying error correction to SRAM memory |
US10437666B2 (en) * | 2015-08-06 | 2019-10-08 | Nxp B.V. | Integrated circuit device and method for reading data from an SRAM memory |
US9778983B2 (en) | 2015-08-06 | 2017-10-03 | Nxp B.V. | Integrated circuit device and method for reducing SRAM leakage |
CN116256624A (en) | 2017-11-15 | 2023-06-13 | 普罗泰克斯公司 | Integrated circuit margin measurement and fault prediction apparatus |
WO2019102467A1 (en) | 2017-11-23 | 2019-05-31 | Proteantecs Ltd. | Integrated circuit pad failure detection |
US11740281B2 (en) | 2018-01-08 | 2023-08-29 | Proteantecs Ltd. | Integrated circuit degradation estimation and time-of-failure prediction using workload and margin sensing |
WO2019135247A1 (en) | 2018-01-08 | 2019-07-11 | Proteantecs Ltd. | Integrated circuit workload, temperature and/or sub-threshold leakage sensor |
TWI828676B (en) | 2018-04-16 | 2024-01-11 | 以色列商普騰泰克斯有限公司 | Methods for integrated circuit profiling and anomaly detection and relevant computer program products |
US11132485B2 (en) | 2018-06-19 | 2021-09-28 | Proteantecs Ltd. | Efficient integrated circuit simulation and testing |
EP3903113A4 (en) | 2018-12-30 | 2022-06-08 | Proteantecs Ltd. | Integrated circuit i/o integrity and degradation monitoring |
CN110763972B (en) * | 2019-10-31 | 2021-10-15 | 上海华力集成电路制造有限公司 | Method for measuring threshold voltage of MOSFET |
TW202127252A (en) | 2019-12-04 | 2021-07-16 | 以色列商普騰泰克斯有限公司 | Memory device degradation monitoring |
EP4139697A4 (en) | 2020-04-20 | 2024-05-22 | Proteantecs Ltd. | Die-to-die connectivity monitoring |
US11815551B1 (en) | 2022-06-07 | 2023-11-14 | Proteantecs Ltd. | Die-to-die connectivity monitoring using a clocked receiver |
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US7936623B2 (en) * | 2006-12-14 | 2011-05-03 | Texas Instruments Incorporated | Universal structure for memory cell characterization |
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KR20240008471A (en) * | 2022-07-12 | 2024-01-19 | (주)피델릭스 | Aging mornitoring circuit in semiconductor memeory device for mornitoring aging with changing in threshold voltage |
KR102634447B1 (en) | 2022-07-12 | 2024-02-06 | 주식회사 피델릭스 | Aging monitoring circuit in semiconductor memeory device for mornitoring aging with changing in threshold voltage |
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US9424952B1 (en) | 2016-08-23 |
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