JP2007201889A - Bit error rate measuring instrument - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low cost bit error rate measuring instrument which shortens time required for auto search of a clock phase and is well balanced in terms of cost, regarding the bit error rate measuring instrument. <P>SOLUTION: In the bit error rate measuring instrument which delays a clock by a delay circuit 1, reproduces data at timing of the clock to calculate the number of big errors or bit error rate of the data, it is constituted by providing: a frequency monitor 10 which measures frequency of the clock to calculate its period; a phase operation part which calculates the optimal value of the phase of the clock by the period calculated by the frequency monitor 10 and the number of bit errors or the bit error rate; and a delay controller 2 which sets the amount of delay of the delay circuit 1 by the optimal value calculated by the phase operation part 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a bit error rate measuring device.

  In a system for transmitting data, for monitoring the performance of the data transmission system, BER (Bit Error Rate) is measured. FIG. 8 is a block diagram showing a configuration example of the bit error rate measuring device, which includes a clock phase auto search circuit (details will be described later). In the circuit shown in the figure, data (Data) and a clock (Clock) for timing the data are input.

  Here, data and a clock will be described. FIG. 9 is a diagram for explaining the relationship between data and a clock. A pulse pattern generator (PPG) 30 outputs pattern data and a clock synchronized with the pattern data. The pattern data output from the PPG 30 enters the device under test (DUT) 31, and the data passing through the DUT 31 is input to the bit error rate measuring device (ED) 32. On the other hand, the clock output from the PPG 30 is input to the ED 32 as it is or after passing through the DUT 31 (indicated by a broken line in the figure). The data and clock input to the ED 32 become the data and clock shown in FIG. The data entering the DUT 31 has its phase fluctuated or distorted with respect to the clock while passing through the DUT 31. The ED 32 will measure the degree of data transmission accuracy of this data.

  Returning to the description of FIG. In the figure, reference numeral 1 denotes a delay circuit that receives a clock and varies its delay amount, and 2 is a delay controller that controls the delay amount (timing) of the delay circuit 1. Here, the delay controller 2 constitutes a clock phase auto search circuit. 3 is a D type flip-flop (hereinafter abbreviated as D-FF) that receives data at its D input terminal and the output of the delay circuit 1 at its clock input terminal, and 4 is a reference corresponding to the data input to the D-FF 3. A reference data pattern generator for generating a data pattern. The D-FF 3 latches data input to the data input terminal at the rising edge of the clock. The reference data pattern generator 4 generates the same pattern data as the pattern data output from the PPG 30 (see FIG. 9).

  5 is an exclusive OR gate (hereinafter abbreviated as XOR gate) which takes the exclusive OR of the output of the D-FF 3 at one input terminal and the output of the reference data pattern generator 4 at the other input terminal, A bit error counter 6 counts the output of the XOR gate 5 to calculate a bit error rate (bit error rate: BER). The output of the bit error counter 6 is input to the delay controller 2. The output of the bit error counter 6 becomes the output of the bit error rate measuring device (BERT). The operation of the circuit thus configured will be described as follows.

  The operation of the circuit shown in the figure is basically that the input data is latched by the input clock in the D-FF 3 and the output is compared with the reference pattern by the XOR gate 5. In the bit error rate measuring device, data is input to the data input terminal of the D-FF3, and the clock is input to the clock input terminal of the D-FF3 after passing through the delay circuit 1 for adjusting the phase with the pattern data. .

The output of the D-FF 3 is input to one input terminal of the XOR gate 5, while the output of the reference data pattern generator 4 is input to the other input terminal of the XOR gate 5. Even when the input data and the reference data are the same (no error is added by the DUT), the output of the XOR gate 5 becomes “1” when the phase of the input data to the D-FF 3 is out of phase with the clock. The bit error counter 6 counts this “1”. The bit error counter 4 counts the output of the XOR 5 and calculates the BER. The calculation method of BER is as follows. If the output of the XOR gate 5 is, for example, 1 out of 10,000 clocks, the BER is 10 ⁻⁴ .

  In the variable range of the clock phase, determining and fixing the clock phase where the bit error is minimum is called clock phase auto search. The operation of the clock phase auto search is as follows. As shown in FIG. 10, the delay control 2 measures the BER while gradually changing the clock phase with respect to the input data such as Clock (a), Clock (b), Clock (c), Clock (d). . The measured BER is notified from the bit error counter 6 to the delay controller 2. The delay controller 2 obtains a clock phase that minimizes the BER given from the bit error counter 6 and sets the clock phase value in the delay controller 2 (clock phase auto search).

  In this way, when the phase of the clock at which the BER becomes the minimum value is determined, the actual device under test is connected and the BER is measured. That is, the operation described with reference to FIG. 8 indicates preprocessing for measuring the actual BER. Without such processing, accurate BER measurement cannot be performed.

  Since the bit error rate measuring device does not know the initial values of the input data and the phase condition of the clock, it is necessary to change the phase of the clock by two cycles or more in order to specify the location where the bit error is minimized. . If there are two clock cycles, one cycle of data can be measured.

As a conventional technique of this type, a technique for predicting an SNR (S / N ratio) in a reception determination circuit when BER is small and measurement is impossible is known (for example, see Non-Patent Document 1). In addition, a bit error rate measuring device having a built-in CDR (Clock and Data Recovery) function capable of BER measurement using only data has been developed (see, for example, Non-Patent Document 2).
Margin Measurement In Optical Amplifier (IEEE PHOTONICS TECHNOLOGY LETTERS, VOL.5, NO3, MARCH 1993) Yokogawa Technical Report, Vol 49, No. 2 (2005), p67-70

  In the prior art, as described above, since the BER is measured while the clock phase is variable by two cycles, there is a problem that the time required for the automatic search for the clock phase becomes long. As a means for changing the phase of the clock, there is a phase shifter (phase shifter), which is expensive. Since the variable range of a general phase shifter is one cycle, two phase shifters are required to change the clock phase by two cycles, leading to an increase in the price of the apparatus.

  The present invention has been made in view of such problems. By realizing the clock phase auto search in a variable range of the clock phase of one cycle, the time required for the clock phase auto search can be shortened and the cost can be reduced. An object of the present invention is to provide a bit error rate measuring device with a balanced cost.

  (1) According to the first aspect of the present invention, in the bit error rate measuring device, the clock is delayed by a delay circuit, the data is reproduced at the timing of the clock, and the number of bit errors or the bit error rate of the data is obtained. A frequency monitor that measures the frequency of the signal and obtains its period, a phase calculator that obtains the optimum value of the clock phase based on the period obtained by the frequency monitor and the number of bit errors or the bit error rate, and a phase calculator And a delay controller for setting a delay amount of the delay circuit according to the optimum value.

  (2) The invention according to claim 2 is a data reproduction circuit that receives data at an input terminal and reproduces the data by a clock, a delay circuit that delays the clock and supplies the data to a clock input terminal of the data reproduction circuit, A delay controller for controlling a delay amount of the delay circuit; a reference data pattern generator for generating a reference data pattern corresponding to input data; and an output of the data reproduction circuit at one input terminal of the reference data pattern generator Receives the reference data pattern from the other input terminal and obtains an exclusive OR thereof, a bit error counter that counts the output of the logic circuit, and receives the output of the bit error counter to optimize the clock phase A phase calculation unit that calculates a value and gives the output to the delay controller; and the clock. And calculating a period from the frequency found by, and having a frequency monitor giving its period to the delay controller and the phase calculating unit.

  (3) In the invention according to claim 3, the phase calculation unit calculates an optimum value of the clock phase based on a point where an approximate straight line of the bit error rate crosses a predetermined threshold value from top to bottom and from bottom to top. It is characterized by doing.

(4) The invention according to claim 4 is characterized in that the phase calculation unit calculates a Q value from a bit error rate and obtains a clock phase from the calculated Q value.
(5) In the invention according to claim 5, the phase calculation unit obtains two approximate lines that intersect with each other based on the Q value, and based on the clock phase at the point at which the obtained approximate lines of the two Q values intersect with each other. And calculating the optimum value of the clock phase.

  (1) According to the first aspect of the present invention, by realizing the clock phase auto search in the variable range of the clock phase in one cycle, the time required for the clock phase auto search can be shortened, and the low cost cost balance can be achieved. A taken bit error rate measuring device can be provided.

  (2) According to the invention described in claim 2, by realizing the clock phase auto search in a variable range of the clock phase of one cycle, the time required for the clock phase auto search can be shortened, and the low cost cost balance can be achieved. A taken bit error rate measuring device can be provided.

(3) According to the invention described in claim 3, the optimum value of the clock phase that minimizes the bit error rate can be calculated by the phase calculation unit.
(4) According to the invention described in claim 4, the clock phase at which the bit error rate is minimized can be obtained from the Q value.

  (5) According to the invention described in claim 5, the clock phase at which the bit error rate is minimized can be obtained from the approximate line of two Q values obtained by obtaining the Q value.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, the same components as those in FIG. 8 are denoted by the same reference numerals. In the figure, reference numeral 1 denotes a delay circuit that receives a clock and varies its delay amount, and 2 is a delay controller that controls the delay amount (data latch timing) of the delay circuit 1. Reference numeral 3 denotes a D-FF that receives data at its D input terminal and the output of the delay circuit 1 at its clock input terminal. Reference numeral 4 denotes a reference data pattern generator that generates a reference data pattern corresponding to the input data. The reference data pattern generated from the reference data pattern generator 4 is set in advance to be the same pattern data as the data pattern generated from the pulse pattern generator 30 (see FIG. 9). The D-FF 3 is configured to latch data input to the data input terminal at the rising edge of the clock.

  The XOR gate 5 receives the output of the D-FF 3 at one input terminal thereof, receives the output of the reference data pattern generator 4 at the other input terminal, and takes the exclusive OR thereof, and 6 outputs the output of the XOR gate 5. It is a bit error counter that calculates BER by counting. The output of the bit error counter 6 becomes the output of the bit error rate measuring device. The delay controller 2 changes the delay control signal given to the delay circuit 1 little by little, and changes the phase of the clock by one period.

  A frequency monitor 10 receives the input clock, measures the clock frequency f, and calculates the period T from the frequency f. Reference numeral 11 denotes a phase calculation unit that receives the output of the bit error counter 6 and the period that is the output of the frequency monitor 10 and calculates the clock phase for one period. The frequency monitor 10 provides the period T to the delay controller 2 and the phase calculation unit 11. The phase calculation unit 11 calculates an optimum clock phase from the bit error rate and the period obtained from the frequency monitor, and sets it in the delay controller 2.

  In the present invention, a frequency monitor 10 and a phase calculation unit 11 are added to the conventional circuit in addition to the conventional circuit shown in FIG. The phase calculation unit 11 can be realized by either hardware or software. The frequency monitor 10, the delay controller 2, and the phase calculation unit 11 constitute a clock phase auto search circuit. The operation of the circuit thus configured will be described as follows.

  Data is input to the data input terminal of the D-FF 3, and the clock is input to the clock input terminal of the D-FF 3 via the delay circuit 1. The output of the D-FF 3 is input to one input terminal of the XOR gate 5, while the output of the reference data pattern generator 4 is input to the other input terminal of the XOR gate 5. The reference data pattern generator 4 outputs reference data having the same value as the data input in advance. The output of the XOR gate 5 is counted by the bit error counter 6 to obtain the bit error rate.

  In such a series of operations, the delay controller 2 provides the delay circuit 1 with a control signal for gradually shifting the phase of the clock for one cycle based on the cycle T given from the frequency monitor 10. As a result, a clock whose phase is gradually changed is output from the delay circuit 1 and input to the D-FF 3 as a latch pulse.

  The output of the D-FF 3 latched by this delay clock is input to one input terminal of the XOR gate 5. On the other hand, the reference data pattern is supplied from the reference data pattern generator 4 to the other input terminal of the XOR gate 5. Then, the XOR gate 5 performs exclusive OR of these input data, and gives the result to the bit error counter 6. The BER is obtained from the bit error counter 6. Further, the output of the bit error counter 6 is given to the phase calculation unit 11, and the phase calculation unit 11 is based on the BER given from the bit error counter 6 and the period given from the frequency monitor 10. The clock phase that minimizes the BER is calculated, and the optimal clock phase value is set in the delay controller 2. With this initial setting process, the circuit shown in the figure can accurately measure the BER.

  FIG. 2 is a diagram showing a first example of the clock phase pair BER obtained in this way. The vertical axis represents BER, and the horizontal axis represents clock phase (Phase). Here, the minimum value of BER is set to 1.0E-10, and the threshold value is set to 1.0E-06. This threshold value is given to the phase calculator 11 in advance. Here, this threshold is set to 1.0E-06.

  When the BER is obtained while gradually changing the clock phase, the value of the BER changes as shown in FIG. The BER characteristic gradually decreases from the BER maximum value of 1.0E-02 and becomes a preset minimum value of 1.0E-10 or less. The BER takes the minimum value while the phase is in a certain width. As the clock phase further increases, the BER gradually increases as shown in the figure.

  As shown in FIG. 2, when the BER is smaller than the previous point when the point that first exceeded the threshold when viewed from the smaller clock phase, the point that first exceeded the threshold is defined as A. Then, when the BER is larger than the previous point when the point exceeding the threshold is viewed from the smaller clock phase, the point is set to B. The phase calculation unit 11 obtains the center of the measurement point between the points A and B, determines that the clock phase at the center is a value that minimizes the BER, and sets the clock phase as an optimum value in the delay controller 2. .

  Referring to the BER characteristic of FIG. 2, the curve including the point A changes so that the BER becomes smaller as the clock phase becomes larger, takes a minimum value at a certain point, and then gradually increases. Is expected to lead to Therefore, it can be predicted that the minimum value of BER is in the vicinity of an intermediate point between point A and point B. Based on the above principle, the clock phase optimum value is obtained. Thereafter, the circuit shown in the figure can accurately measure the bit error rate of the device under test.

  FIG. 3 is a diagram illustrating a second example of the clock phase pair BER. This example shows a characteristic that the BER is less than or equal to the minimum value while the clock phase is small and then gradually increases from the minimum value when reaching a certain value. When the BER reaches the maximum value (here, 1.0E-02), a predetermined interval maximum value is taken, and when the clock phase is further increased, the BER gradually decreases from the maximum value.

  Here, when the BER is larger than the previous point when the point first exceeding the threshold is viewed from the smaller clock phase, the point first exceeding the threshold is set to A. If the BER is smaller than the previous point when a point exceeding the threshold is viewed from the smaller clock phase, the point is set to B.

  Then, the phase calculator 11 obtains the center of the measurement point between points A and B. In this case, the center value is not the clock phase optimum value. Next, the clock phase optimum value is set in the delay controller 2 by setting the value obtained by subtracting 1/2 of the period T obtained from the frequency monitor 10 as the optimum phase value. However, when the value obtained by subtracting 1/2 of the period T is 0 or less, a value obtained by adding 1/2 of the period T is set in the delay controller 2 as the optimum value of the clock phase.

  Looking at the characteristics of FIG. 3, the curve including the point A changes in the direction in which the BER increases, and the clock phase where the actual BER is the minimum value is a region where the clock phase is smaller than the curve including the point A. It is predicted that Therefore, it can be predicted that there is a clock phase at which the BER has a minimum value in the vicinity of ½ of the period T in the direction where the clock phase is smaller than the center position of the measurement point between points A and B. Based on the above principle, the clock phase optimum value is obtained. Thereafter, the circuit shown in the figure can measure the bit error rate of the device under test more accurately.

  As described above, according to the present invention, the clock phase auto search is realized in the variable range of the clock phase in one cycle, thereby reducing the time required for the clock phase auto search and reducing the cost balance. A taken bit error rate measuring device can be provided.

  In the above-described embodiment, the case where the bit error rate is calculated by the bit error counter has been described as an example. However, the present invention is not limited to this, and a count value (number of bit errors) obtained by counting the outputs of the XOR gate 5 can also be used. For example, the count value is given from the bit error counter 6 to the phase calculator 11. The phase calculation unit 11 holds data to be the denominator of the count value of the bit error counter 6 in advance. The count value from the bit error counter 6 is input and the calculation using the denominator is performed from this count value. And the bit error rate can be calculated.

  FIG. 4 is a block diagram showing another embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the embodiment shown in FIG. 4, a Q factor converter 12 that receives the output of the bit error counter 6 and outputs a Q value is provided between the bit error counter 6 and the phase calculation unit 11 of FIG. is there. Other configurations are the same as those of the circuit shown in FIG. Here, the frequency monitor 10, the delay controller 2, the Q factor converter 12, and the phase calculator 11 constitute a clock phase auto search circuit.

  Here, the Q value of the Q factor will be described. The Q value is defined by the difference between the amplitude (standard deviation) of the binary signal and the average amplitude, although the amplitude of the binary signal “0” and “1” varies due to noise or the like. The Q factor converter 12 receives the output of the bit error counter 6 and performs conversion from BER to Q factor. The operation of the circuit thus configured will be described as follows.

  When the clock phase is varied by one cycle by the delay controller 2 and the bit error rate (BER) is measured and graphed, the result is as shown in FIG. (A) shows Example 1 and (b) shows Example 2. The horizontal axis is phase, and the vertical axis is BER. Depending on the input data and the phase condition of the clock, BERs having different characteristics are obtained as shown in (a) and (b).

  Such a BER characteristic is converted into a Q value by the Q factor converter 12. Conversion from BER to Q value was obtained with reference to Non-Patent Document 1. FIG. 6 is a diagram illustrating an example of the obtained Q value, and is a diagram illustrating an example of the clock phase pair Q value. The horizontal axis is the clock phase, and the vertical axis is the Q value. 6A corresponds to FIG. 5A, and FIG. 6B corresponds to FIG. 5B.

  The phase calculation unit 11 obtains a linear approximate straight line of the Q value obtained as described above. As shown in FIG. 6A, when the slope of the approximate line with the smaller clock phase is positive and the slope of the approximate line with the larger clock phase is negative, the intersection of the approximate lines (point M in the figure). ) Is set to the delay controller 2 as the optimal clock phase value.

  On the other hand, as shown in FIG. 6B, when the slope of the approximate line with the smaller clock phase is negative and the slope of the approximate line with the larger clock phase is positive, the intersection N of the approximate lines is The clock phase optimum value is set in the delay controller 2 using the value obtained by subtracting ½ of the period obtained from the frequency monitor 10 as the optimum clock phase value. However, when the value obtained by subtracting 1/2 of the period T becomes negative, the clock phase optimal value is set in the delay controller 2 with the value obtained by adding 1/2 of the period T as the optimal value of the clock phase. .

  If the Q value is used, even if the BER with respect to the clock phase is distorted as shown in FIG. 7A, if converted to the Q value as shown in FIG. Since fitting is possible, the optimum value of the clock phase can be calculated from the intersection.

  According to this embodiment, even when the BER with respect to the clock phase is distorted, since the BER is converted into the Q value, the fitting with the approximate straight line can be performed, so that the optimum value of the clock phase can be easily calculated. can do.

  In the above-described embodiment, the case where the BER is calculated in the case where data is transmitted in synchronization with the phase clock has been described. However, the present invention is not limited to this, and is applied to all circuits that reproduce data at the timing of the clock. can do.

  As described above, according to the present invention, the clock phase auto search can be realized by one delay circuit having one cycle of the variable range. Also, the clock phase auto search time can be shortened.

It is a block diagram which shows one embodiment of this invention. It is a figure which shows the 1st example of a clock phase pair BER. It is a figure which shows the 2nd example of a clock phase pair BER. It is a block diagram which shows the other embodiment of this invention. It is a figure which shows the example of a clock phase pair BER. It is a figure which shows the example of a clock phase pair Q value. It is a figure which shows the relationship between BER and Q value. It is a block diagram which shows the structural example of a bit error rate measuring device. It is a figure explaining the relationship between data and a clock. It is a figure which shows the timing of the data and clock which are input into D-FF.

Explanation of symbols

1 Delay circuit 2 Delay controller 3 D type flip-flop (D-FF)
4 Reference data pattern generator 5 XOR gate 6 Bit error counter 10 Frequency monitor 11 Phase calculator

Claims (5)

In a bit error rate measuring device that delays a clock by a delay circuit and reproduces data according to the timing of this clock and obtains the number of bit errors or the bit error rate of the data.
A frequency monitor that measures the frequency of the clock to determine its period;
A phase calculation unit for obtaining an optimum value of the phase of the clock based on the period obtained by the frequency monitor and the number of bit errors or the bit error rate;
A delay controller for setting a delay amount of the delay circuit according to the optimum value obtained by the phase calculation unit;
A bit error rate measuring device comprising: A data recovery circuit for receiving data at an input terminal and recovering the data by a clock;
A delay circuit that delays the clock and applies it to the clock input terminal of the data recovery circuit;
A delay controller for controlling a delay amount of the delay circuit;
A reference data pattern generator for generating a reference data pattern corresponding to the input data;
A logic circuit that receives the output of the data reproduction circuit at one of its input terminals, receives the reference data pattern from the reference data pattern generator at the other input terminal, and takes an exclusive OR thereof;
A bit error counter for counting the output of the logic circuit;
A phase calculator that receives the output of the bit error counter to calculate an optimum value of the clock phase and gives the output to the delay controller;
Calculating a period from the frequency obtained by inputting the clock, and a frequency monitor for giving the period to the delay controller and the phase calculation unit;
A bit error rate measuring device comprising:   3. The phase calculating unit calculates an optimum value of a clock phase based on a point where an approximate straight line of a bit error rate crosses a predetermined threshold value from top to bottom and from bottom to top. The bit error rate measuring instrument described.   The bit error rate measuring device according to claim 1, wherein the phase calculation unit calculates a Q value from a bit error rate and obtains a clock phase from the calculated Q value.   The phase calculation unit obtains two approximate lines that intersect with each other based on the Q value, and calculates an optimum value of the clock phase based on the clock phase at the point where the obtained approximate lines of the two Q values intersect with each other. 5. The bit error rate measuring device according to claim 4, wherein:

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