JP2007201440A - Method for manufacturing semiconductor device, semiconductor inspection device, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of efficiently inspecting whether a metal silicide layer is sufficiently formed. <P>SOLUTION: The method for manufacturing a semiconductor device is provided with the steps of: forming a metal layer over a semiconductor layer containing silicon; forming a metal silicide layer over a surface of the semiconductor layer by heating the semiconductor layer and the metal layer; generating image data by performing color imaging of the metal silicide layer from above the metal silicide layer; calculating saturation of the metal silicide layer by processing the image data; and judging the formation amount of the metal silicide layer on the basis of the calculated saturation. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, a semiconductor inspection device, and a program including a step of forming a metal silicide layer.

  As semiconductor devices are highly integrated and miniaturized, contact resistance to impurity regions (eg, a source region or a drain region of a transistor) formed in a semiconductor layer containing silicon is reduced, and the resistance of these impurity regions is reduced. Is required. In order to reduce the resistance, it is effective to form a metal silicide layer such as a titanium silicide layer, a cobalt silicide layer, or a nickel silicide layer on the surface of the semiconductor layer.

The method for forming the metal silicide layer is as follows. First, a metal layer such as a titanium layer, a cobalt layer, or a nickel layer is formed on a semiconductor layer containing silicon by, for example, a sputtering method. Next, the metal layer and the semiconductor layer are subjected to heat treatment (for example, 400 ° C.) by, for example, RTA. As a result, silicon diffuses into the metal layer, or the metal diffuses into the semiconductor layer containing silicon, and the metal and silicon react to form a metal silicide layer. Thereafter, the metal that is not silicided is removed by wet etching (see, for example, Patent Document 1).
JP-A-5-283696 (17th and 18th paragraphs)

  In the above-described process, there are cases where the metal silicide layer is not sufficiently formed in the entire area, for example, the film thickness of the metal silicide layer varies for some reason, or the metal silicide layer is not partially formed. In this case, the contact resistance and the sheet resistance of the semiconductor layer containing silicon are not sufficiently lowered.

  Therefore, it is necessary to inspect whether or not the metal silicide layer is sufficiently formed. As this inspection method, there is a method of actually measuring contact resistance or sheet resistance of a semiconductor layer using a probe terminal. However, in this method, it is necessary to form a pad connected to the probe terminal. That is, it is necessary to form an interlayer insulating film on the semiconductor layer on which the metal silicide layer is formed, and further form a connection hole and a wiring layer. For this reason, the measurement efficiency was bad.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a semiconductor device manufacturing method and semiconductor inspection capable of efficiently inspecting whether or not a metal silicide layer is sufficiently formed. An apparatus and a program are provided.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a metal layer on a semiconductor layer containing silicon,
Forming a metal silicide layer on the surface of the semiconductor layer by applying heat to the semiconductor layer and the metal layer;
From above the metal silicide layer, color imaging the metal silicide layer to generate image data;
Processing the image data to calculate the saturation of the metal silicide layer;
And determining the amount of formation of the metal silicide layer based on the calculated saturation.

  According to this method for manufacturing a semiconductor device, the formation amount of the metal silicide layer is determined based on the saturation of the metal silicide layer. Therefore, it can be efficiently inspected whether or not the metal silicide layer is sufficiently formed.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a metal layer on a semiconductor layer containing silicon,
Forming a metal silicide layer on the surface of the semiconductor layer by applying heat to the semiconductor layer and the metal layer;
From above the metal silicide layer, color imaging the metal silicide layer to generate image data;
Processing the image data to calculate the hue of the metal silicide layer;
And determining a formation amount of the metal silicide layer based on the calculated hue.

  According to this method for manufacturing a semiconductor device, the formation amount of the metal silicide layer is determined based on the hue of the metal silicide layer. Therefore, it can be efficiently inspected whether or not the metal silicide layer is sufficiently formed.

  The metal layer is, for example, a nickel layer, a titanium layer, or a cobalt layer, and the metal silicide layer is, for example, a nickel silicide layer, a titanium silicide layer, or a cobalt silicide layer. The semiconductor layer is, for example, a source or drain of a thin film transistor.

A semiconductor inspection apparatus according to the present invention includes an imaging unit that performs color imaging on a metal silicide layer formed on a surface of a semiconductor layer containing silicon to generate image data;
A saturation calculator that processes the image data to calculate the saturation of the metal silicide layer;
And a determination unit that determines the formation amount of the metal silicide layer based on the saturation calculated by the saturation calculation unit.

  When the determination unit holds an expression indicating the correlation between the sheet resistance of the metal silicide layer and the saturation, the saturation calculated by the saturation calculation unit is substituted into the expression to calculate the sheet resistance. When the calculated sheet resistance is equal to or less than the reference value, it is determined that the metal silicide layer is sufficiently formed. In addition, when the determination unit holds an expression indicating the correlation between the thickness of the metal silicide layer and the saturation, the saturation calculated by the saturation calculation unit is substituted into the expression to calculate the thickness. It may be determined that the metal silicide layer is sufficiently formed when the calculated film thickness is equal to or greater than a reference value.

  When the image data is RGB image data, the saturation calculation unit processes the RGB image data to process the metal silicide layer when the average value of G is larger than the average value of B in the RGB image data. May be calculated.

Another semiconductor inspection apparatus according to the present invention includes an imaging unit that performs color imaging on a metal silicide layer formed on a surface of a semiconductor layer containing silicon and generates image data;
A hue calculation unit that processes the image data to calculate the hue of the metal silicide layer;
And a determination unit that determines the formation amount of the metal silicide layer based on the hue calculated by the hue calculation unit.

  When the determination unit holds an equation indicating the correlation between the sheet resistance of the metal silicide layer and the hue, the hue calculated by the hue calculation unit is substituted into the equation to calculate the sheet resistance, and the calculation is performed. When the sheet resistance is equal to or lower than a reference value, it may be determined that the metal silicide layer is sufficiently formed. In addition, when the determination unit holds an expression indicating a correlation between the film thickness of the metal silicide layer and the hue, the hue calculated by the hue calculation unit is substituted into the expression to calculate the film thickness, If the film thickness is equal to or greater than a reference value, it may be determined that the metal silicide layer is sufficiently formed.

  When the image data is RGB image data, the hue calculation unit processes the RGB image data and processes the RGB image data when the average value of G is larger than the average value of B in the RGB image data. The hue may be calculated.

  The determination unit is a program installed in a computer system via a recording medium, for example. The saturation calculation unit is a program installed in a computer system via a recording medium, for example.

A program according to the present invention is a program that is executed by a computer and processes image data of a metal silicide layer to determine the formation amount of the metal silicide layer,
In the computer,
A function of processing the image data to calculate the saturation of the metal silicide layer;
And a function of determining a formation amount of the metal silicide layer based on the calculated saturation.

Another program according to the present invention is a program that is executed by a computer and processes image data of a metal silicide layer to determine the formation amount of the metal silicide layer,
In the computer,
A function of processing the image data to calculate a hue of the metal silicide layer;
And a function of determining the amount of formation of the metal silicide layer based on the calculated hue.

  As described above, according to the present invention, since the formation amount of the metal silicide layer is determined based on the saturation or hue of the metal silicide layer, it is efficiently inspected whether or not the metal silicide layer is sufficiently formed. can do.

(Embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram for explaining a configuration of a semiconductor inspection apparatus according to an embodiment of the present invention. This semiconductor inspection apparatus is an apparatus for inspecting whether or not a metal silicide layer is sufficiently formed on a semiconductor layer.

  This semiconductor inspection apparatus includes an optical system 10 for enlarging a metal silicide layer formed on a substrate 100, an imaging device 20 for performing color imaging of an image magnified by the optical system 10, a saturation hue calculation unit 30, and a determination unit 40. Have.

  The imaging device 20 includes, for example, a CCD type or MOS type imaging device, and generates RGB image data of an image enlarged by the optical system 10. Note that the imaging device 20 may generate complementary color image data of an image enlarged by the optical system 10.

  The saturation hue calculation unit 30 calculates the saturation (for example, corrected saturation) and hue of the metal silicide layer using the RGB image data generated by the imaging device 20. When the imaging device 20 generates complementary color system image data, the saturation hue calculation unit 30 converts the complementary color system image data into RGB image data, and then calculates the saturation and hue of the metal silicide layer. The determination unit 40 determines whether the metal silicide layer is sufficiently formed based on the saturation or hue calculated by the saturation hue calculation unit 30. Details of processing performed by the saturation hue calculation unit 30 and the determination unit 40 will be described later with reference to flowcharts.

  FIG. 2A is a graph showing the correlation between the saturation of the metal silicide layer and the sheet resistance. This graph shows the results of forming a plurality of samples having a metal silicide layer and measuring the saturation and sheet resistance of these samples. The plurality of samples used here are formed by forming a metal layer on a silicon layer and heat-treating the silicon layer and the metal layer. The formation conditions of the silicon layer are the same among the plurality of samples, but the film thickness of the metal layer is different among the plurality of samples. As shown in the figure, the saturation of the metal silicide layer and the sheet resistance have a correlation. The determination unit 40 shown in FIG. 1 holds a correlation formula between the saturation of the metal silicide layer and the sheet resistance. For this reason, the determination unit 40 substitutes the saturation of the metal silicide layer into the correlation between the saturation and the sheet resistance, thereby determining whether the sheet resistance of the metal silicide layer is lower than the reference value, that is, whether the metal silicide layer is It can be determined whether or not it is sufficiently formed. However, the imaging condition when the correlation formula is calculated needs to be the same as the imaging condition when determining whether or not the sheet resistance is lower than the reference value using the correlation formula.

  FIG. 2B is a graph showing the correlation between the hue of the metal silicide layer and the sheet resistance. This graph shows the results of forming a plurality of samples having a metal silicide layer and measuring the hue and sheet resistance of these samples. The plurality of samples used here are formed by forming a metal layer on a silicon layer and heat-treating the silicon layer and the metal layer. The formation conditions of the silicon layer are the same among the plurality of samples, but the film thickness of the metal layer is different among the plurality of samples. As shown in the figure, the hue of the metal silicide layer and the sheet resistance have a correlation. The determination unit 40 shown in FIG. 1 holds a correlation formula between the hue of the metal silicide layer and the sheet resistance. For this reason, the determination unit 40 substitutes the hue of the metal silicide layer into the correlation between the hue and the sheet resistance to determine whether the sheet resistance of the metal silicide layer is lower than the reference value, that is, the metal silicide layer is sufficiently It can be determined whether or not it is formed. However, the imaging condition when the correlation formula is calculated needs to be the same as the imaging condition when determining whether or not the sheet resistance is lower than the reference value using the correlation formula.

  FIG. 2C shows an image of a metal silicide layer taken by an imaging device, a value obtained by subtracting an average value of B from an average value of G in the generated RGB data (hereinafter referred to as GB), and sheet resistance. It is a graph which shows a correlation. This graph shows the result of measuring a metal silicide layer in which no pattern is formed. In the case of only a semiconductor layer (for example, a silicon layer), the sheet resistance is very high and cannot be measured. Therefore, in this graph, it is assumed to be 1000 [Ω / □]. When the sheet resistance is extremely high, that is, when the semiconductor layer is not silicided, GB becomes negative, but in other cases, that is, when a metal silicide layer is formed, it is positive. Therefore, by calculating GB, a sample in which the metal silicide layer is not formed can be selected.

  3 is a cross-sectional view for explaining a method of forming a metal silicide layer on the substrate 100. FIG. First, as illustrated in FIG. 3A, a base insulating film 101 is formed over a substrate 100 by a CVD method. The substrate 100 is, for example, a glass substrate, a quartz glass substrate, a substrate formed of an insulating material such as alumina, or a plastic substrate having heat resistance that can withstand a processing temperature in a subsequent process. The base insulating film 101 may have a single-layer structure of a silicon oxide film or a two-layer structure in which a silicon nitride film is formed over the silicon oxide film.

  Next, a semiconductor film is formed over the base insulating film 101 by, for example, a CVD method. This semiconductor film is formed of a material containing silicon and capable of forming a metal silicide, such as silicon and silicon-germanium-carbon. When the semiconductor film is a polysilicon film, as a method for forming the polysilicon film, there are a method of directly forming a polysilicon film on a substrate and a method of crystallizing after forming an amorphous silicon film. Next, a photoresist film (not shown) is applied on the semiconductor film, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the semiconductor film. Next, the semiconductor film is etched using this resist pattern as a mask. Thereby, the semiconductor layer 102 is formed over the base insulating film 101. The semiconductor layer 102 may have an island shape or a shape to be a wiring. Next, impurities are implanted into the semiconductor layer 102 to reduce resistance.

  Next, a metal film 103 is formed over the semiconductor layer 102 and the base insulating film 101 by a sputtering method. The metal film 103 is, for example, a nickel film, but may be a titanium film or a cobalt film. Next, the metal film 103 and the semiconductor layer 102 are heat-treated by an RTA method. The heating temperature is preferably 350 ° C. or higher and 700 ° C. or lower, and more preferably 400 ° C. or higher and 650 ° C. or lower. Thereby, a metal silicide layer 104 is formed on the surface of the semiconductor layer 102.

  Next, as shown in FIG. 3B, the non-silicided metal film 103 is removed by, for example, wet etching. Thereafter, the imaging device 20 of the semiconductor inspection apparatus shown in FIG. 1 is used to image the metal silicide layer 104 and generate RGB image data of the metal silicide layer 104. Then, the semiconductor inspection apparatus determines whether or not the metal silicide layer 104 is sufficiently formed using the saturation hue calculation unit 30 and the determination unit 40.

FIG. 4 is a flowchart for explaining a first example of processing performed by the saturation hue calculation unit 30 and the determination unit 40. When the imaging device 20 generates RGB image data of the metal silicide layer 104 (S10), the saturation hue calculation unit 30 calculates an average value of R, an average value of G, and an average value of B of the RGB image data. (S20). The average value of R is obtained by dividing the value obtained by adding the R value of each pixel constituting the obtained image by the number of pixels, and the average value of G constitutes the obtained image. The value obtained by adding the G value of each pixel is divided by the number of pixels, and the average value of B is obtained by adding the B value of each pixel constituting the obtained image. The value is divided by the number of pixels. Next, the saturation hue calculation unit 30 calculates the saturation Q _c of the metal silicide layer by substituting the calculated average values of R, G, and B into the generally known formula 1 below (S30). ).

Next, the determination unit 40 substitutes the saturation Q _c calculated by the saturation hue calculation unit 30 into the correlation equation between the sheet resistance and saturation of the metal silicide layer, and calculates the sheet resistance of the metal silicide layer 104 (S40). ). The correlation equation used here is calculated by the following method, for example. First, a metal film having a different thickness is formed for each sample on a silicon layer manufactured under the same conditions as the formation conditions of the metal silicide layer 104 to be measured, and the sample is heat-treated to form a metal silicide layer. In each of these samples, the correlation equation is obtained by measuring the sheet resistance and saturation of the metal silicide film. When the calculated sheet resistance is equal to or less than the reference value (S50: Yes), the determination unit 40 determines that the metal silicide layer 104 is sufficiently formed (S60), and when the calculated sheet resistance exceeds the reference value ( S50: No), it is determined that the metal silicide layer 104 is not sufficiently formed (S70).

  As described above, according to the first example, the saturation hue calculation unit 30 and the determination unit 40 process the RGB image data of the metal silicide layer 104 generated by the imaging device 20, so that the metal silicide layer 104 is sufficiently formed. It is possible to efficiently determine whether or not it has been done. In addition, it is possible to suppress variation in the determination result.

  FIG. 5 is a flowchart for explaining a second example of processing performed by the saturation hue calculation unit 30 and the determination unit 40. The second example is the first example except that the saturation hue calculation unit 30 performs the processing of S30 and subsequent steps of the first example only when the average value of G is larger than the average value of B (S25: Yes). It is the same. When the average value of G is smaller than the average value of B (S25: No), it can be determined that the metal silicide layer 104 is not formed as described with reference to FIG. 2C (S70). Hereinafter, the same steps as those in the first example are denoted by the same step numbers, and description thereof is omitted.

  According to the second example, the same effect as that of the first example can be obtained. Further, when the metal silicide layer 104 is not formed, the relationship between saturation and sheet resistance deviates from the correlation equation. On the other hand, in the present embodiment, only when the average value of G is larger than the average value of B (S25: Yes), the processing after S30 of the first example is performed, so that the metal silicide layer 104 is sufficiently formed with high accuracy. It can be determined whether or not. Further, it can be determined more efficiently whether or not the metal silicide layer 104 is sufficiently formed.

  FIG. 6 is a flowchart for explaining a third example of processing performed by the saturation hue calculation unit 30 and the determination unit 40. In the third example, the determination unit 40 determines whether or not the metal silicide layer is sufficiently formed using the hue.

  The imaging device 20 generates RGB image data of the metal silicide layer 104 (S10), and the saturation hue calculation unit 30 calculates the average value of R, the average value of G, and the average value of B of the RGB image data (S20). ) And the saturation hue calculation unit 30 calculates the hue H of the metal silicide layer by substituting the calculated average values of R, G, and B into the following generally known equation 2 (S32). .

  Next, the determination unit 40 substitutes the hue H calculated by the saturation hue calculation unit 30 into the correlation equation between the sheet resistance and the hue of the metal silicide layer, and calculates the sheet resistance of the metal silicide layer 104 (S42). The correlation equation used here is calculated by the following method, for example. First, a metal film having a different thickness is formed for each sample on a silicon layer manufactured under the same conditions as the formation conditions of the metal silicide layer 104 to be measured, and the sample is heat-treated to form a metal silicide layer. In each of these samples, a correlation equation is obtained by measuring the sheet resistance and hue of the metal silicide film. When the calculated sheet resistance is equal to or less than the reference value (S52: Yes), the determination unit 40 determines that the metal silicide layer 104 is sufficiently formed (S62), and when the calculated sheet resistance exceeds the reference value ( S52: No), it is determined that the metal silicide layer 104 is not sufficiently formed (S72).

  Also according to this embodiment, it is possible to efficiently determine whether or not the metal silicide layer 104 is sufficiently formed. In addition, it is possible to suppress variation in the determination result.

  FIG. 7 is a flowchart for explaining a fourth example of processing performed by the saturation hue calculation unit 30 and the determination unit 40. The fourth example is the third example except that the saturation hue calculation unit 30 performs the processing of S32 and subsequent steps of the third example only when the average value of G is larger than the average value of B (S25: Yes). It is the same. When the average value of G is smaller than the average value of B (S25: No), it can be determined that the metal silicide layer 104 is not formed as described with reference to FIG. 2C (S72). Hereinafter, the same steps as those in the third example are denoted by the same step numbers, and the description thereof is omitted.

  According to the fourth example, the same effect as the third example can be obtained. When the metal silicide layer 104 is not formed, the relationship between the hue and the sheet resistance deviates from the correlation equation. On the other hand, in the present embodiment, only when the average value of G is larger than the average value of B (S25: Yes), the processing after S32 of the third example is performed, and thus the metal silicide layer 104 is sufficiently formed with high accuracy. It can be determined whether or not. Further, it can be determined more efficiently whether or not the metal silicide layer 104 is sufficiently formed.

FIG. 8 is a flowchart for explaining a fifth example of processing performed by the saturation hue calculation unit 30 and the determination unit 40. The imaging device 20 generates RGB image data of the metal silicide layer 104 (S10), and the saturation hue calculation unit 30 calculates the average value of R, the average value of G, and the average value of B of the RGB image data (S20). ). If the average value of G is smaller than the average value of B (S25: No), it is determined that the metal silicide layer 104 is not formed. When the average value of G is larger than the average value of B (S25: Yes), the saturation hue calculation unit 30 substitutes the calculated average values of R, G, and B into the above formulas 1 and 2, respectively. Thus, the saturation _Qc and the hue H of the metal silicide layer are calculated (S34).

Next, the determination unit 40 substitutes the calculated saturation Q _c into the correlation equation between the sheet resistance and the saturation of the metal silicide layer, calculates the sheet resistance of the metal silicide layer 104, and calculates the calculated hue H as the metal The sheet resistance of the metal silicide layer 104 is calculated by substituting it into the correlation equation between the sheet resistance of the silicide layer and the hue (S44). These correlation equations are calculated by forming a large-area metal silicide film under the same method and conditions as the formation conditions of the metal silicide layer 104, and measuring the sheet resistance, saturation, and hue of the metal silicide film. The Next, the determination unit 40 calculates an average value of the two calculated sheet resistances, and determines whether or not the calculated average value is equal to or less than a reference value (S54). When the calculated average value is less than or equal to the reference value (S54: Yes), it is determined that the metal silicide layer 104 is sufficiently formed (S64), and when the calculated average value exceeds the reference value (S54: No) Then, it is determined that the metal silicide layer 104 is not sufficiently formed (S74).

  Also in this example, it is possible to efficiently determine whether or not the metal silicide layer 104 is sufficiently formed. In addition, it is possible to suppress variation in the determination result.

  FIG. 9 is a flowchart for explaining a sixth example of processing performed by the saturation hue calculation unit 30 and the determination unit 40. The imaging device 20 generates RGB image data of the metal silicide layer 104 (S10), and the saturation hue calculation unit 30 calculates the average value of R, the average value of G, and the average value of B of the RGB image data (S20). ). Next, the saturation hue calculation unit 30 calculates the hue H of the metal silicide layer 104 by substituting the calculated average values of R, G, and B into the above-described equation 2 (S32). Next, the determination unit 40 substitutes the calculated hue H into the correlation equation between the sheet resistance and the hue of the metal silicide layer, and calculates the sheet resistance of the metal silicide layer 104 (S42).

  When the sheet resistance calculated by the determination unit 40 exceeds the reference value (S52: No), the determination unit 40 determines that the metal silicide layer 104 is not sufficiently formed (S76) and ends the process.

In addition, when the sheet resistance calculated by the determination unit 40 is equal to or less than the reference value (S52: Yes), the saturation hue calculation unit 30 substitutes the calculated average values of R, G, and B into Equation 1 described above. Thus, the saturation Q _c of the metal silicide layer 104 is calculated (S56).

Then, determination unit 40, the calculated saturation Q _c, are substituted into the correlation equation of the sheet resistance and saturation of the metal silicide layer, to calculate the sheet resistance of the metal silicide layer 104. Then, the sheet resistance was calculated from the saturation Q _c, calculates the average value of the sheet resistance calculated from the hue H, the calculated average value is equal to or less than the reference value (S58). When the calculated average value is less than or equal to the reference value (S58: Yes), it is determined that the metal silicide layer 104 is sufficiently formed (S66), and when the calculated average value exceeds the reference value (S58: No) Then, it is determined that the metal silicide layer 104 is not sufficiently formed (S76).

  Also in this example, it is possible to efficiently determine whether or not the metal silicide layer 104 is sufficiently formed.

Further, when the metal silicide layer 104 is not formed, the relationship between saturation and sheet resistance deviates from the correlation equation. In contrast, in the present embodiment, first, the sheet resistance is calculated from the hue H, and it is determined whether or not the metal silicide layer 104 is sufficiently formed based on the sheet resistance. Then, only when the metal silicide layer 104 is sufficiently formed to calculate the sheet resistance based on the saturation Q _c, the mean value of the two sheet resistance values, and the value of the final sheet resistance.
Therefore, it can be determined whether or not the metal silicide layer 104 is sufficiently formed.

  Note that the saturation hue calculation unit 30 and the determination unit 40 are realized by installing a program having the above-described functions in a computer system. This program is installed in the computer system via a recording medium, for example. The recording medium for storing the program is, for example, a floppy disk (registered trademark), a removable disk such as a CD-ROM, a CD-R, a CD-R / W, a DVD-RAM, an MO, a semiconductor memory, or a hard disk. It may be other than. Further, this program may be installed in a computer system by being downloaded through a communication line such as the Internet.

  As described above, according to the present embodiment, it is possible to efficiently determine whether or not the metal silicide layer 104 is sufficiently formed, and it is possible to suppress variations in determination results. In addition, since it can be realized by adding the saturation hue calculation unit 30 and the determination unit 40 to the conventional device and can be inspected nondestructively, compared with the conventional evaluation method, the process is shortened, early detection of defects, Improve quality control and reduce costs.

  It is well known that the sheet resistance decreases as the metal silicide film thickness increases. For this reason, in the above embodiment, the determination unit 40 may use an expression indicating the relationship between the saturation and the film thickness of the metal silicide layer instead of the expression 1, or the metal silicide layer instead of the expression 2. An equation indicating the relationship between the hue and the film thickness may be used. In this case, the determination unit 40 calculates the film thickness instead of the sheet resistance of the metal silicide layer. If the calculated film thickness is greater than or equal to the reference value, it is determined that the metal silicide layer is sufficiently formed.If the calculated film thickness is less than or less than the reference value, the metal silicide layer is sufficiently formed. Judge that not.

Example 1
Here, a process of manufacturing the crystalline semiconductor film 201 over the substrate 400 and manufacturing a top gate TFT using the crystalline semiconductor film 201 will be described.

  First, as illustrated in FIG. 10A, a silicon nitride oxide film 401 and a silicon oxynitride film 402 are formed in this order over a substrate 400. Next, the semiconductor film 201 is formed over the silicon oxynitride film 402. As the substrate 400, for example, a glass substrate, a quartz glass substrate, a substrate formed of an insulating material such as alumina, a plastic substrate having heat resistance that can withstand a processing temperature in a later process, or the like can be used. Note that the substrate to be used is preferably a substrate that transmits visible light and has little wavelength dependency of transmittance or reflectance of visible light. The silicon nitride oxide film 401 and the silicon oxynitride film 402 are provided to prevent impurities such as sodium from diffusing from the substrate 400 into the semiconductor film 201.

  As the semiconductor film 201, a material capable of forming Ni silicide, such as silicon or silicon-germanium-carbon, can be used. The semiconductor film 201 may be an amorphous semiconductor film, a crystalline semiconductor film, or a single crystal semiconductor film.

  In the following description, the case where the crystalline semiconductor film 201 is used as the semiconductor film 201 is described. As a method for forming the crystalline semiconductor film 201, a method in which the crystalline semiconductor film 201 is directly formed over the silicon oxynitride film 402 or an amorphous semiconductor film is formed over the silicon oxynitride film 402 and then crystallized. A method is mentioned.

  As a method of crystallizing an amorphous semiconductor film, a method of irradiating a laser beam, a method of crystallizing by heat treatment using an element that promotes crystallization of a semiconductor film, an element that promotes crystallization of a semiconductor film After crystallization using heat treatment, a method of irradiating with laser light can be used.

  In this embodiment, a method of irradiating laser light after crystallizing by heat treatment using an element that promotes crystallization of an amorphous semiconductor film will be described.

  First, an amorphous silicon film is formed over the silicon oxynitride film 402 by a plasma CVD method.

  Next, a metal-containing layer is formed on the surface of the amorphous semiconductor film. The metal-containing layer is a metal element having a catalytic action for promoting crystallization of a semiconductor film (for example, one or more selected from Fe, Ni, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au) ). When the metal element is Ni, for example, a metal-containing layer is formed by applying (for example, spin coating) a nickel acetate solution containing 1 to 100 ppm of nickel in terms of weight. As a method for forming the metal-containing layer, there is a method of forming an extremely thin film by sputtering, vapor deposition, or plasma treatment, in addition to coating. Although an example in which the metal-containing layer is formed on the entire surface is shown here, the metal-containing layer may be selectively formed using a mask. The metal-containing layer may be formed before forming the amorphous semiconductor film, that is, below the amorphous semiconductor film.

Next, the substrate 400, the silicon nitride oxide film 401, the silicon oxynitride film 402, the amorphous semiconductor film, and the metal-containing layer are subjected to heat treatment. Then, an alloy of a metal element and a semiconductor is formed in the semiconductor, and crystallization of the amorphous semiconductor film proceeds with the alloy as a nucleus, so that a semiconductor film having a crystal structure, that is, a crystalline semiconductor film 201 is formed. Note that the concentration of oxygen contained in the crystalline semiconductor film 201 is preferably 5 × 10 ¹⁸ / cm ³ or less. Here, after heat treatment for dehydrogenation (450 ° C. to 500 ° C., 1 to 2 hours), heat treatment for crystallization (550 ° C. to 650 ° C. for 4 to 24 hours) is performed.

  Alternatively, the amorphous semiconductor film can be crystallized by irradiation with strong light instead of heat treatment. In this case, any one of infrared light, visible light, and ultraviolet light or a combination thereof can be used. Typically, a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure Light emitted from a sodium lamp or a high-pressure mercury lamp is used. The lamp light source is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to about 600 to 1000 ° C. Note that if necessary, heat treatment for releasing hydrogen contained in the amorphous semiconductor film having an amorphous structure may be performed before irradiation with strong light. Further, crystallization may be performed by performing both heat treatment and irradiation with strong light.

  Note that an oxide film is formed on the surface of the crystalline semiconductor film 201 in the above-described heat treatment or irradiation with strong light, but this oxide film is preferably removed by etching before the next step.

  Next, in order to increase the crystallization rate of the crystalline semiconductor film 201 (the ratio of the crystal component in the entire volume of the film) and repair defects remaining in the crystal grains, a large amount of laser light is applied to the crystalline semiconductor film 201. Irradiate under atmospheric pressure.

As the laser beam, a pulse oscillation type or continuous oscillation type excimer laser having a wavelength of 400 nm or less, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, sapphire laser, etc. should be used. Can do. Further, light emitted from an ultraviolet lamp may be used instead of these laser beams.

In the case of using the above-described laser, the laser light emitted from the laser oscillator may be collected linearly by an optical system and irradiated onto the crystalline semiconductor film 201. Crystallization conditions are appropriately selected by the practitioner. When a pulse oscillation type excimer laser is used, for example, the pulse oscillation frequency is set to 30 Hz and the laser energy density is set to 100 to 500 mJ / cm ² . When a pulse oscillation type YAG laser or YVO ₄ laser is used, the pulse oscillation frequency is set to 1 to 10 kHz using the second harmonic or the third harmonic, and the laser energy density is set to 300 to 600 mJ / cm ^2. good. Then, the entire surface of the crystalline semiconductor film 201 is irradiated with a laser beam condensed in a linear shape with a width of 100 to 1000 μm, for example, 400 μm. At this time, it is preferable to set the laser beam superposition ratio (overlap ratio) to 80 to 98%. In addition, it is possible to use laser light having an oscillation frequency of 1 to 10 MHz.

In the case of using a continuous wave laser (e.g. a continuous wave YVO ₄ laser), a harmonic by a nonlinear optical element of the laser light emitted from the YVO ₄ laser of a continuous oscillation output 10 W (second harmonic to a fourth Harmonics). In addition, there is a method in which a YVO ₄ crystal and a nonlinear optical element are placed in a resonator to emit harmonics. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the crystalline semiconductor film 201. At this time, the energy density of about 0.001~100MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 0.5 to 2000 cm / s.

  Next, an oxide film (called chemical oxide) is formed on the surface of the crystalline semiconductor film 201 by treating the surface of the crystalline semiconductor film 201 with an ozone-containing aqueous solution (typically ozone water). As a result, a barrier layer 202 made of an oxide film having a total thickness of 1 to 10 nm is formed. The barrier layer 202 functions as an etching stopper when only the gettering layer is selectively removed in a later step.

  Here, the same barrier layer 202 (chemical oxide) can be formed by treating with an aqueous solution containing hydrogen peroxide instead of the ozone-containing aqueous solution. Alternatively, the barrier layer 202 may be formed by irradiating ultraviolet rays in an oxygen atmosphere to generate ozone and oxidizing the surface of the crystalline semiconductor film 201 with the ozone. Alternatively, an oxide film with a thickness of about 1 to 10 nm may be formed as the barrier layer 202 by plasma CVD, sputtering, vapor deposition, or the like.

  Next, a gettering layer 203 containing a rare gas element is formed over the barrier layer 202 as a gettering site. Here, an amorphous semiconductor film containing an argon gas is formed as the gettering layer 203 by a sputtering method. When forming the gettering layer 203, sputtering conditions are adjusted as appropriate so that a rare gas element is added. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used.

  There are two meanings in which the gettering layer 203 contains a rare gas element ion which is an inert gas. One is to form a dangling bond to give distortion to the semiconductor film constituting the gettering layer 203, and the other is to give distortion between the lattices of the semiconductor film. In order to give strain between the lattices of the semiconductor film, it is preferable to use an element having an atomic radius larger than that of an element (for example, silicon) constituting the semiconductor film, such as argon (Ar), krypton (Kr), xenon (Xe). In addition, when a rare gas element is contained in the semiconductor film constituting the gettering layer 203, not only lattice distortion occurs but also dangling bonds are formed, so that the gettering capability of the gettering layer 203 is further improved. To do.

Note that when the gettering layer 203 is formed using a source gas containing phosphorus which is an impurity element of one conductivity type, or when the gettering layer 203 is formed using a target containing phosphorus, the rare gas element is used. In addition to gettering, gettering can be performed using the Coulomb force of phosphorus. Further, since metal element (for example, nickel) tends to move to a region having a high oxygen concentration during gettering, the oxygen concentration contained in the gettering layer 203 is, for example, 5 × 10 ¹⁸ / cm ³ or more. It is desirable.

  Next, the crystalline semiconductor film 201, the barrier layer 202, and the gettering layer 203 are subjected to heat treatment (for example, heat treatment or irradiation with intense light). Thus, gettering of a metal element (for example, nickel) is performed as shown by an arrow in FIG. 10A, and the metal element in the crystalline semiconductor film 201 is reduced in concentration or removed.

  Next, as shown in FIG. 10B, only the gettering layer 203 is selectively removed by etching using the barrier layer 202 as an etching stopper. Thereafter, the barrier layer 202 made of an oxide film is removed by, for example, an etchant containing hydrofluoric acid. Through the above steps, the crystalline semiconductor film 201 is obtained.

  Next, as illustrated in FIG. 11A, the crystalline semiconductor film 201 is selectively removed by a photolithography process, so that island-shaped crystalline semiconductor films 403 and 404 are formed.

  Next, as illustrated in FIG. 11B, after the surfaces of the crystalline semiconductor films 403 and 404 are washed with a hydrofluoric acid-containing etchant, a gate insulating film 405 is formed so as to cover the crystalline semiconductor films 403 and 404. . The gate insulating film 405 is formed using an insulating film containing silicon as a main component. The surface cleaning step and the gate insulating film 405 formation step are preferably performed continuously without exposure to the atmosphere.

  Next, after cleaning the surface of the gate insulating film 405, a metal film containing Al, Cu, W, or the like as a main component is formed over the gate insulating film 405. A photoresist film (not shown) is formed on the metal film, and the photoresist film is exposed and developed to form a resist pattern. Using this resist pattern as a mask, the metal film is etched to form electrodes 406 to 409 on the gate insulating film 405. FIG. 11B shows a gate electrode having a two-layer structure in which the second electrodes 407 and 409 are stacked over the first electrodes 406 and 408. The gate electrode may have a single layer structure or a stacked layer structure. Here, TaN is used for the first electrodes 406 and 408, and W (tungsten) is used for the second electrodes 407 and 409. Thereafter, the resist pattern is removed.

  Further, when a material capable of forming Ni silicide such as silicon is used for the gate electrode material, Ni silicide can also be formed on the gate electrode in the silicidation process described later. For example, a crystalline semiconductor film or an amorphous semiconductor film imparted with conductivity is formed over the entire surface of the gate insulating film, and then a gate electrode is formed on the conductive film using a known photolithography process. Then, Ni silicide is also formed on the gate electrode in a silicidation step described later.

  Next, as shown in FIG. 12A, a resist mask 410 is newly formed by photolithography. Subsequently, an impurity element imparting N-type (for example, phosphorus) is added to the crystalline semiconductor film 403 at a low concentration by an ion doping method using the mask 410 to form N-type impurity regions 411 and 412.

  Next, as shown in FIG. 12B, the mask 410 is removed, and a mask 413 made of a resist is newly formed by photolithography. Subsequently, an impurity element imparting P-type (eg, boron) is added to the crystalline semiconductor film 404 by ion doping using the mask 413 to form P-type impurity regions 414 and 415.

Next, as shown in FIG. 13A, the mask 413 is removed, and an insulating layer 416 is formed so as to cover the gate insulating film 405 and the electrodes 406 to 409. The insulating layer 416 is formed, for example, by depositing silicon oxynitride (SiOxNy) (x> y) to 100 nm by plasma CVD, and then forming 200 nm of silicon oxide (SiO ₂ film) by thermal CVD.

  Next, as shown in FIG. 13B, the insulating layer 416 is selectively etched by anisotropic etching mainly in the vertical direction so as to be in contact with the side surfaces of the electrodes 406 to 409 (hereinafter referred to as sidewalls). 417) (referred to as an insulating layer). The sidewall insulating layer 417 functions as a mask for doping an LDD region to be formed later, and is used to prevent silicidation up to the LDD region in a silicide process described later. Further, part of the gate insulating film is also removed by this etching, so that the N-type impurity regions 411 and 412 of the crystalline semiconductor film 403 and the P-type impurity regions 414 and 415 of the crystalline semiconductor film 404 are exposed.

  Next, as shown in FIG. 14A, a resist mask 418 is formed by photolithography. Subsequently, an impurity element imparting N-type conductivity (phosphorus) is added to the crystalline semiconductor film 403 using the sidewall insulating layer 417 as a mask, and first N-type impurity regions (also referred to as LDD regions) 421 and 422 are formed. , Second N-type impurity regions 419 and 420 are formed. The concentration of the impurity element contained in the first N-type impurity regions 421 and 422 is lower than the concentration of the impurity element in the second N-type impurity regions 419 and 420.

Thereafter, the mask 418 is removed. Next, the oxide film formed on the surface of the crystalline silicon film is removed by etching. The etching conditions here are preferably conditions that can remove the thin oxide film formed on the surface of the crystalline silicon film and can suppress the etching of the sidewall insulating layer 417 and the gate insulating film 405. . Here, a hydrofluoric acid solution mixed at a ratio of HF: H ₂ O = 1: 99 is dropped for 90 seconds while rotating the substrate to remove the oxide film. Thus, the sidewall insulating layer 417 is silicon oxynitride (SiOxNy) (x> y) and a silicon oxide film (SiO ₂ film), and the gate insulating film 405 is silicon oxynitride (SiOxNy) (x> y). In this case, etching of the sidewall insulating layer 417 and the gate insulating film 405 can be suppressed.

  Next, a Ni film 424 is formed on the entire surface by sputtering (FIG. 14B).

  Next, the silicon in the second N-type impurity regions 419 and 420 and the P-type impurity regions 414 and 415 are reacted with the Ni film 424 by heat treatment, GRTA method, LRTA method, etc. 425 is formed. Ni silicide may be formed by laser irradiation or light irradiation by a lamp.

Next, unreacted Ni is removed (FIG. 15A). Here, unreacted Ni is removed using an etching solution of HCl: HNO ₃ : H ₂ O = 3: 2: 1. Since the etching rate of this etching solution is about 100 nm / min for Ni and about 1 nm / min for W, the gate electrode is not damaged. By removing unreacted Ni, the Ni silicide layer 425 is exposed.

Next, using the method shown in the above-described embodiment, it is determined whether silicidation has sufficiently progressed and the Ni silicide layer 425 has been sufficiently formed. For example, when the method shown in FIG. 4 is used, average values of R, G, and B are calculated from image data generated by the imaging apparatus. Then, the equation 1 described above by substituting the R, G, and respective average values B, and calculates a saturation Q _c. Then, the calculated saturation Q _c, are substituted into the correlation equation of saturation and the sheet resistance of the metal silicide layer, to calculate the sheet resistance of the metal silicide layer 425. If the calculated sheet resistance is less than or equal to the reference value, it is determined that the metal silicide layer 425 is sufficiently formed. If the calculated sheet resistance exceeds the reference value, it is determined that the metal silicide layer 425 is not sufficiently formed. To do. This method can be realized by adding a saturation hue calculation unit 30 and a determination unit 40 to a conventional apparatus, and can be inspected nondestructively. Therefore, it can be efficiently determined whether or not the Ni silicide layer 425 is sufficiently formed.

  Through the above steps, basic structures of an N-type thin film transistor 426 and a P-type thin film transistor 427 are completed. The N-type thin film transistor 426 includes a crystalline silicon film including first N-type impurity regions 421 and 422, second N-type impurity regions 419 and 420, and a channel formation region 423, a gate insulating layer 405, an electrode 406, 407. Such a structure of the thin film transistor 426 is called an LDD structure.

  A P-type thin film transistor 427 includes a crystalline silicon film including P-type impurity regions 414 and 415 and a channel formation region 428, a gate insulating layer 405, and electrodes 408 and 409. Such a structure of the thin film transistor 427 is called a single drain structure.

  The channel length of the thin film transistor 426 and the thin film transistor 427 completed through the above steps is 0.5 to 5 μm, preferably 1 to 3 μm. Due to the above feature, the response speed can be increased. Note that the channel length may be made according to the circuit. For example, the channel length of a thin film transistor that constitutes a power supply circuit that does not require high-speed operation is 3 μm, and the channel length of thin film transistors in other circuits is 1 μm. .

  Next, as illustrated in FIG. 15B, an insulating layer 429 is formed so as to cover the thin film transistors 426 and 427. As the insulating layer 429, silicon oxynitride (SiOxNy) (x> y) is formed to a thickness of 50 nm by a plasma CVD method.

  After the insulating layer 429 is formed, heat treatment for the purpose of hydrogenating the silicon film is performed. This heat treatment also restores the crystallinity of the silicon film and activates the impurity element added to the silicon film.

  Next, a single-layer or stacked insulating layer is formed using an inorganic material such as silicon oxide or silicon nitride, or an organic material such as polyimide, polyamide, benzocyclobutene, acrylic, epoxy, or siloxane. The siloxane-based material is, for example, an organic group in which a skeleton structure is formed by a bond of silicon and oxygen, and a substituent includes at least hydrogen. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen as a substituent and a fluoro group may be used. In the illustrated cross-sectional structure, the insulating layer covering the thin film transistors 426 and 427 has a three-layer structure. For example, a layer containing silicon oxide is formed as the first insulating layer 429, a layer containing silicon nitride is formed as the second insulating layer 430, and silicon oxide is used as the third insulating layer 431. A layer containing may be formed.

  Next, the insulating layers 429 to 431 are etched by photolithography to form contact holes that expose the P-type impurity regions 414 and 415 and the second N-type impurity regions 419 and 420, that is, the Ni silicide layer 425. Subsequently, a conductive layer is formed so as to fill the contact hole, and the conductive layer is patterned to form conductive layers 432 to 434 functioning as a source wiring and a drain wiring.

  The conductive layers 432 to 434 are made of an element selected from titanium (Ti), aluminum (Al), and neodymium (Nd) by plasma CVD or sputtering, or an alloy material or compound material containing these elements as main components. A single layer or a stacked layer is formed. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive layers 432 to 434 are, for example, a structure in which a barrier layer, an aluminum silicon (Al—Si) layer, and a barrier layer are stacked in this order from the substrate side, or a barrier layer aluminum silicon (Al—Si) layer from the substrate side, A structure in which a titanium nitride (TiN) layer and a barrier layer are stacked in this order may be employed. Note that the barrier layer corresponds to a thin film formed of titanium, a nitride of titanium, molybdenum, or a nitride of molybdenum. Aluminum and aluminum silicon are optimal materials for forming the conductive layers 432 to 434 because they have low resistance and are inexpensive. In addition, when barrier layers are provided in the upper layer and the lower layer, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier layer is provided in the lower layer, favorable contact between aluminum or aluminum silicon and the crystalline semiconductor layer can be obtained. Titanium is a highly reducible element. Therefore, when a barrier layer made of titanium is formed, even if a thin natural oxide film is formed on the crystalline silicon film, the natural oxide film is reduced and crystalline. Good contact can be made with the silicon film. The TFT is completed through the above steps.

  In addition, if the layer formed on the Ni silicide layer 425 is transparent, the quality of silicidation can be determined using the evaluation method described in the above embodiment even after the TFT is completed. If the evaluation method shown in this embodiment is used, the conventional apparatus can be diverted, analysis can be completed in a short time, and non-destructive inspection can be performed. Discover, improve quality control and reduce costs.

  By using the present invention, the process can be shortened, defects can be detected early, quality control can be improved, and the cost can be reduced. Therefore, a TFT having a low sheet resistance and capable of high-speed operation can be efficiently manufactured. A TFT manufactured using the present invention is suitable for a driver IC, a CPU, an ID chip, and the like.

(Example 2)
As an electronic device to which the present invention is applied, a camera such as a video camera or a digital camera, a goggle type display, a navigation system, a sound reproduction device, a computer, a game device, a portable information terminal (mobile computer, cellular phone, portable game machine, Or an electronic book or the like), an image reproducing device including a storage medium (an apparatus including a display capable of reproducing a storage medium such as a digital versatile disc (DVD) and displaying the image). Specific examples of these electronic devices are shown in FIGS.

  FIG. 16A shows a module in which a display panel 5301 and a printed wiring board 5302 are combined. The printed wiring board 5302 and the display panel 5301 are connected by a flexible wiring board (FPC) 5313.

  The display panel 5301 includes a pixel portion 5303 provided with a plurality of pixels, a first scan line driver circuit 5304, a second scan line driver circuit 5305, and a signal line driver circuit that supplies a video signal to the selected pixel. 5306 is provided. A TFT is used for each of the pixel portion 5303, the first scan line driver circuit 5304, the second scan line driver circuit 5305, and the signal line driver circuit 5306. These TFTs are those described in Embodiment 1. It can be formed by the same method.

  The printed wiring board 5302 is provided with a controller 5307, a central processing unit (CPU) 5308, a memory 5309, a power supply circuit 5310, an audio processing circuit 5311, a transmission / reception circuit 5312, and the like. A capacitor element, a buffer circuit, and the like may be provided on the printed wiring board 5302 to prevent noise from being applied to a power supply voltage or a signal or a rise in signal from being slowed down. The controller 5307, the audio processing circuit 5311, the memory 5309, the CPU 5308, the power supply circuit 5310, and the like can be mounted on the display panel 5301 using a COG (Chip On Glass) method. The scale of the printed wiring board 5302 can be reduced by the COG method.

  Various control signals are input and output through an interface (I / F) unit 5314 provided in the printed wiring board 5302. An antenna port 5315 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 5302.

  FIG. 16B is a block diagram of the module shown in FIG. This module includes a VRAM 5316, a DRAM 5317, a flash memory 5318, and the like as the memory 5309. The VRAM 5316 stores image data to be displayed on the panel, the DRAM 5317 stores image data or sound data, and the flash memory stores various programs.

  The power supply circuit 5310 supplies power for operating the display panel 5301, the controller 5307, the CPU 5308, the sound processing circuit 5311, the memory 5309, and the transmission / reception circuit 5312. Depending on the specifications of the panel, the power supply circuit 5310 may be provided with a current source.

  The CPU 5308 includes a control signal generation circuit 5320, a decoder 5321, a register 5322, an arithmetic circuit 5323, a RAM 5324, an interface 5319 for the CPU 5308, and the like. Various signals input to the CPU 5308 through the interface 5319 are temporarily held in the register 5322 and then input to the arithmetic circuit 5323, the decoder 5321, and the like. The arithmetic circuit 5323 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 5321 is decoded and input to the control signal generation circuit 5320. The control signal generation circuit 5320 generates a signal including various instructions based on the input signal, and a location designated by the arithmetic circuit 5323, specifically, a memory 5309, a transmission / reception circuit 5312, an audio processing circuit 5311, a controller 5307, and the like. Send to.

  The memory 5309, the transmission / reception circuit 5312, the audio processing circuit 5311, and the controller 5307 operate according to the received commands. Hereinafter, operations of the controller 5307, the transmission / reception circuit 5312, and the sound processing circuit 5311 will be briefly described.

  A signal input from the input unit 5325 is sent to the CPU 5308 mounted on the printed wiring board 5302 via the I / F unit 5314. The control signal generation circuit 5320 converts the image data stored in the VRAM 5316 into a predetermined format according to a signal sent from the input unit 5325 such as a pointing device or a keyboard, and sends the image data to the controller 5307.

  The controller 5307 subjects the signal including the image data sent from the CPU 5308 to data processing according to the specifications of the panel and supplies the processed data to the display panel 5301. Further, the controller 5307 generates an Hsync signal, a Vsync signal, a clock signal CLK, an AC voltage (AC Cont), and a switching signal L / R based on the power supply voltage input from the power supply circuit 5310 and various signals input from the CPU 5308. Generated and supplied to the display panel 5301.

  In the transmission / reception circuit 5312, a signal transmitted / received as a radio wave in the antenna 5328 is processed. A signal including audio information among signals transmitted and received in the transmission / reception circuit 5312 is sent to the audio processing circuit 5311 in accordance with a command from the CPU 5308.

  A signal including audio information sent in accordance with a command from the CPU 5308 is demodulated into an audio signal by the audio processing circuit 5311 and sent to the speaker 5327. An audio signal sent from the microphone 5326 is modulated in the audio processing circuit 5311 and sent to the transmission / reception circuit 5312 in accordance with a command from the CPU 5308.

  A TFT manufactured using the method described in Embodiment 1 can be used for the CPU 5308, the controller 5307, the memory 5309, and the like of the module illustrated in FIG. A TFT manufactured using the present invention can operate at high speed and is suitable for the CPU 5308 and the like.

  FIG. 17A illustrates a liquid crystal display or an OLED display, which includes a housing 6001, a support base 6002, a display portion 6003, and the like. A TFT manufactured using the present invention has a low sheet resistance and can operate at high speed, and thus can be used for a CPU that processes data of an image to be displayed on a liquid crystal display or an OLED display. In addition, the structure of the liquid crystal module or the EL module, or the module illustrated in FIG. 16A can be applied to the display portion 6003.

  By applying the TFT manufactured using the method shown in Embodiment 1 to a liquid crystal display or an OLED display, a display capable of high-speed operation can be manufactured. In addition, when the evaluation method shown in the embodiment is used, a conventional apparatus can be diverted, analysis can be performed in a short time, and non-destructive inspection can be performed. Early detection, improved quality control, and reduced costs.

  FIG. 17B illustrates a computer, which includes a main body 6101, a housing 6102, a display portion 6103, a keyboard 6104, an external connection port 6105, a pointing mouse 6106, and the like. A TFT manufactured using the method described in Embodiment 1 has low sheet resistance and can operate at high speed, and thus can be used for a CPU that processes image data to be displayed on a computer. In addition, application to the display portion 6103 is possible using the structure of the liquid crystal module or the EL module, or the module illustrated in FIG.

  By applying a TFT manufactured using the method described in Embodiment 1 to a computer, a computer capable of high-speed operation can be manufactured. In addition, when the evaluation method shown in the embodiment is used, a conventional apparatus can be diverted, analysis can be performed in a short time, and non-destructive inspection can be performed. Early detection, improved quality control, and reduced costs.

  FIG. 17C illustrates a portable computer, which includes a main body 6201, a display portion 6202, a switch 6203, operation keys 6204, an infrared port 6205, and the like. A TFT manufactured using the method described in Embodiment 1 has low sheet resistance and can operate at high speed, and thus can be used for a CPU that processes image data to be displayed on a computer. In addition, application to the display portion 6202 is possible using a structure of a liquid crystal module or an EL module, or the module shown in FIG.

  By applying a TFT manufactured using the method described in Embodiment 1 to a computer, a computer capable of high-speed operation can be manufactured. In addition, when the evaluation method shown in the embodiment is used, a conventional apparatus can be diverted, analysis can be performed in a short time, and non-destructive inspection can be performed. Early detection, improved quality control, and reduced costs.

  FIG. 17D illustrates a portable game machine including a housing 6301, a display portion 6302, speaker portions 6303, operation keys 6304, a recording medium insertion portion 6305, and the like. A TFT manufactured using the method described in Embodiment 1 has low sheet resistance and can operate at high speed, and thus can be used for a CPU that processes data of an image to be displayed on a game machine. In addition, application to the display portion 6302 is possible using a structure of a liquid crystal module or an EL module, or the module shown in FIG.

  By applying a TFT manufactured using the method described in Embodiment 1 to a game machine, a game machine capable of high-speed operation can be manufactured. In addition, when the evaluation method shown in the embodiment is used, a conventional apparatus can be diverted, analysis can be performed in a short time, and non-destructive inspection can be performed. Early detection, improved quality control, and reduced costs.

  FIG. 17E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 6401, a housing 6402, a display portion A 6403, a display portion B 6404, and a recording medium (such as a DVD). A reading unit 6405, operation keys 6406, a speaker unit 6407, and the like are included. The display portion A 6403 mainly displays image information, and the display portion B 6404 mainly displays character information. A TFT manufactured using the method described in Embodiment 1 has low sheet resistance and can operate at high speed, and thus can be used for a CPU that processes image data to be displayed on an image reproduction device. In addition, application to the display portion A 6403 and the display portion B 6404 can be performed using a liquid crystal module or an EL module, or the structure of the module shown in FIG. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

  By applying the TFT manufactured using the method shown in Embodiment 1 to an image reproducing device, an image reproducing device capable of high-speed operation can be manufactured. Further, when the method shown in the embodiment is used, the conventional apparatus can be diverted, the analysis can be completed in a short time, and non-destructive inspection can be performed. Discover, improve quality control and reduce costs.

  Display devices used in these electronic devices can use not only a glass substrate but also a heat-resistant plastic substrate depending on the size, strength, or purpose of use. Thereby, further weight reduction can be achieved.

  It should be noted that the examples shown in the present embodiment are only examples and are not limited to these applications.

  In addition, this embodiment can be freely combined with any description of the above embodiment modes and embodiments.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

Schematic for demonstrating the structure of the semiconductor inspection apparatus which concerns on embodiment. (A) is a graph showing the correlation between the saturation of the metal silicide layer and the sheet resistance, (B) is a graph showing the correlation between the hue of the metal silicide layer and the sheet resistance, and (C) is the GB value of the metal silicide layer. And graph showing sheet resistance correlation. 9 is a cross-sectional view for explaining a method of forming a metal silicide layer on the substrate 100. FIG. The flowchart for demonstrating the 1st example of the process which the saturation hue calculation part 30 and the judgment part 40 perform. Flowchart for explaining a second example of processing performed by the saturation hue calculation unit 30 and the determination unit 40 Flowchart for explaining a third example of processing performed by the saturation hue calculation unit 30 and the determination unit 40 The flowchart for demonstrating the 4th example of the process which the saturation hue calculation part 30 and the judgment part 40 perform. The flowchart for demonstrating the 5th example of the process which the saturation hue calculation part 30 and the judgment part 40 perform. The flowchart for demonstrating the 6th example of the process which the saturation hue calculation part 30 and the judgment part 40 perform. Each figure is sectional drawing for demonstrating the method based on Example 1. FIG. Each figure is sectional drawing for demonstrating the next process of FIG. Each figure is a sectional view for explaining the next step of FIG. Each drawing is a sectional view for explaining the next step of FIG. Each figure is a sectional view for explaining the next step of FIG. Each figure is a sectional view for explaining the next step of FIG. (A) is a top view for demonstrating the module which concerns on Example 2, (B) is a circuit diagram of the module shown to (A). Each figure is a perspective view for explaining an electronic apparatus according to the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20 ... Imaging device, 30 ... Saturation hue calculation part, 40 ... Judgment part, 100 ... Substrate, 104 ... Metal silicide layer

Claims (16)

Forming a metal layer on the semiconductor layer containing silicon;
Forming a metal silicide layer on the surface of the semiconductor layer by applying heat to the semiconductor layer and the metal layer;
From above the metal silicide layer, color imaging the metal silicide layer to generate image data;
Processing the image data to calculate the saturation of the metal silicide layer;
Determining the formation amount of the metal silicide layer based on the calculated saturation;
A method for manufacturing a semiconductor device comprising: Forming a metal layer on the semiconductor layer containing silicon;
Forming a metal silicide layer on the surface of the semiconductor layer by applying heat to the semiconductor layer and the metal layer;
From above the metal silicide layer, color imaging the metal silicide layer to generate image data;
Processing the image data to calculate the hue of the metal silicide layer;
Determining the formation amount of the metal silicide layer based on the calculated hue;
A method for manufacturing a semiconductor device comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein the metal layer is a nickel layer, a titanium layer, or a cobalt layer, and the metal silicide layer is a nickel silicide layer, a titanium silicide layer, or a cobalt silicide layer.   The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is a source or a drain of a thin film transistor. Imaging means for color-imaging a metal silicide layer formed on the surface of a semiconductor layer containing silicon to generate image data;
A saturation calculator that processes the image data to calculate the saturation of the metal silicide layer;
A determination unit that determines a formation amount of the metal silicide layer based on the saturation calculated by the saturation calculation unit;
A semiconductor inspection apparatus comprising:   The determination unit holds an expression indicating a correlation between the sheet resistance of the metal silicide layer and the saturation, and calculates the sheet resistance by substituting the saturation calculated by the saturation calculation unit into the expression. The semiconductor inspection apparatus according to claim 5, wherein when the calculated sheet resistance is equal to or less than a reference value, it is determined that the metal silicide layer is sufficiently formed.   The determination unit holds an expression indicating a correlation between the thickness of the metal silicide layer and the saturation, and calculates the film thickness by substituting the saturation calculated by the saturation calculation unit into the equation. The semiconductor inspection apparatus according to claim 5, wherein when the calculated film thickness is equal to or greater than a reference value, it is determined that the metal silicide layer is sufficiently formed. The image data is RGB image data,
The saturation calculation unit calculates the saturation of the metal silicide layer by processing the RGB image data when an average value of G is larger than an average value of B in the RGB image data. The semiconductor inspection apparatus according to any one of the above. Imaging means for color-imaging a metal silicide layer formed on the surface of a semiconductor layer containing silicon to generate image data;
A hue calculation unit that processes the image data to calculate the hue of the metal silicide layer;
A determination unit that determines the formation amount of the metal silicide layer based on the hue calculated by the hue calculation unit;
A semiconductor inspection apparatus comprising:   The determination unit holds an expression indicating the correlation between the sheet resistance and the hue of the metal silicide layer, and calculates the sheet resistance by substituting the hue calculated by the hue calculation unit into the expression. The semiconductor inspection apparatus according to claim 9, wherein when the sheet resistance is less than or equal to a reference value, it is determined that the metal silicide layer is sufficiently formed.   The determination unit holds an expression indicating the correlation between the thickness of the metal silicide layer and the hue, and calculates the film thickness by substituting the hue calculated by the hue calculation unit into the expression. The semiconductor inspection apparatus according to claim 9, wherein when the film thickness is equal to or greater than a reference value, it is determined that the metal silicide layer is sufficiently formed. The image data is RGB image data,
The hue calculation unit calculates the hue of the metal silicide layer by processing the RGB image data when an average value of G is larger than an average value of B in the RGB image data. The semiconductor inspection apparatus according to claim 1.   The semiconductor inspection apparatus according to claim 5, wherein the determination unit is a program installed in a computer system via a recording medium.   The semiconductor inspection apparatus according to claim 5, wherein the saturation calculation unit is a program installed in a computer system via a recording medium. A program executed by a computer for processing image data of a metal silicide layer to determine the formation amount of the metal silicide layer,
In the computer,
A function of processing the image data to calculate the saturation of the metal silicide layer;
A program for executing a function of determining a formation amount of the metal silicide layer based on the calculated saturation. A program executed by a computer for processing image data of a metal silicide layer to determine the formation amount of the metal silicide layer,
In the computer,
A function of processing the image data to calculate a hue of the metal silicide layer;
A program for executing a function of determining a formation amount of the metal silicide layer based on the calculated hue.