JP2007201308A - Circuit board, semiconductor device, and method for manufacturing semiconductor device - Google Patents

Circuit board, semiconductor device, and method for manufacturing semiconductor device Download PDF

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Publication number
JP2007201308A
JP2007201308A JP2006020100A JP2006020100A JP2007201308A JP 2007201308 A JP2007201308 A JP 2007201308A JP 2006020100 A JP2006020100 A JP 2006020100A JP 2006020100 A JP2006020100 A JP 2006020100A JP 2007201308 A JP2007201308 A JP 2007201308A
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JP
Japan
Prior art keywords
wiring pattern
protruding electrode
insulating layer
semiconductor device
protruding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006020100A
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Japanese (ja)
Inventor
Naoki Komukai
直樹 小向
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
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Seiko Epson Corp
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Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2006020100A priority Critical patent/JP2007201308A/en
Publication of JP2007201308A publication Critical patent/JP2007201308A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To correspond to a miniaturization of an interconnection and to prevent a contact between protruding electrodes and interconnections arranged in staggering pattern. <P>SOLUTION: Conjugating the protruding electrode 5 formed on a semiconductor chip 4 on the interconnection pattern 2 face down bonds the semiconductor chip 4 on an insulating substrate 1, arranges the electrode 5 in staggering hsape, and forms an insulating layer 7 so as to cover an interconnection pattern 2a at the part adjacent to the bonding part of the protruding electrode 5b arranged at the outside on the semiconductor chip 4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は回路基板、半導体装置および半導体装置の製造方法に関し、特に、突出電極を
端子電極に接合させる方法に適用して好適なものである。 The present invention relates to a circuit board, a semiconductor device, and a method for manufacturing the semiconductor device, and is particularly suitable for application to a method of bonding a protruding electrode to a terminal electrode.

従来の半導体装置では、インナーリードのファインピッチ化を図るために、例えば、特
許文献１に開示されているように、突出電極を千鳥配列する方法がある。
特開２００４−１９３２２３号公報 In a conventional semiconductor device, there is a method in which protruding electrodes are arranged in a staggered manner as disclosed in Patent Document 1, for example, in order to achieve a fine pitch of inner leads.
JP 2004-193223 A

しかしながら、突出電極を千鳥配列する方法では、突出電極の接合時に突出電極が膨ら
み、突出電極間に配置された配線との間隔が狭くなることから、インナーリードのファイ
ンピッチ化の障害になるという問題があった。
そこで、本発明の目的は、配線の微細化に対応しつつ、千鳥配列された突出電極と配線
との接触を防止することが可能な回路基板、半導体装置および半導体装置の製造方法を提
供することである。 However, in the method of arranging the projecting electrodes in a staggered manner, the projecting electrodes swell when the projecting electrodes are joined, and the distance between the wirings arranged between the projecting electrodes is narrowed, which may hinder the fine pitching of the inner leads. was there.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a circuit board, a semiconductor device, and a semiconductor device manufacturing method capable of preventing contact between protruding electrodes arranged in a staggered pattern and wiring while corresponding to miniaturization of wiring. It is.

上述した課題を解決するために、本発明の一態様に係る回路基板によれば、突出電極が
接合される配線パターンが形成された絶縁性基材と、前記突出電極の接合部に隣接する部
分の配線パターンを覆うように形成された絶縁層とを備えることを特徴とする。
これにより、突出電極の接合時に突出電極が膨らみ、突出電極間に配置された配線パタ
ーンとの間隔が狭くなった場合においても、突出電極と配線パターンとが接触することを
防止することができ、配線の微細化に対応しつつ、千鳥配列された突出電極と配線とのシ
ョートを防止することが可能となる。 In order to solve the above-described problem, according to a circuit board according to an aspect of the present invention, an insulating base material on which a wiring pattern to which a protruding electrode is bonded is formed, and a portion adjacent to the bonding portion of the protruding electrode And an insulating layer formed to cover the wiring pattern.
Thereby, even when the protruding electrode swells when the protruding electrode is joined, and the interval between the wiring patterns arranged between the protruding electrodes is narrowed, the protruding electrode and the wiring pattern can be prevented from contacting each other. It is possible to prevent short-circuiting between the protruding electrodes arranged in a staggered pattern and the wiring while corresponding to the miniaturization of the wiring.

また、本発明の一態様に係る回路基板によれば、突出電極が接合される配線パターンが
形成された絶縁性基材と、前記突出電極の接合部に隣接する部分の配線パターンを覆うよ
うに形成された絶縁層と、前記突出電極の接合部との間隔に対して前記絶縁層との間隔が
広がるようにして前記配線パターン上に形成されたソルダーレジストとを備えることを特
徴とする。
これにより、配線パターンを覆うように絶縁層が形成されている場合においても、絶縁
層とソルダーレジストとの間の隙間を介して樹脂を流し込むことが可能となり、回路基板
上にフェースダウン実装された半導体チップの封止を安定して行うことが可能となる。 Moreover, according to the circuit board which concerns on 1 aspect of this invention, it covers so that the insulating base material in which the wiring pattern to which a protruding electrode was joined was formed, and the wiring pattern of the part adjacent to the junction part of the said protruding electrode may be covered. It is characterized by comprising a solder resist formed on the wiring pattern so that the distance between the insulating layer formed and the insulating layer is larger than the distance between the protruding electrode and the junction.
As a result, even when the insulating layer is formed so as to cover the wiring pattern, the resin can be poured through the gap between the insulating layer and the solder resist, and the circuit board is mounted face down. The semiconductor chip can be stably sealed.

また、本発明の一態様に係る半導体装置によれば、配線パターンが形成された回路基板
と、突出電極を介して前記配線パターンに接合された半導体チップと、前記突出電極の接
合部に隣接する部分の配線パターンを覆うように形成された絶縁層とを備えることを特徴
とする。
これにより、突出電極の接合時に突出電極が膨らみ、突出電極間に配置された配線パタ
ーンとの間隔が狭くなった場合においても、突出電極と配線パターンとが接触することを
防止することができ、配線の微細化に対応しつつ、千鳥配列された突出電極と配線とのシ
ョートを防止することが可能となる。 According to the semiconductor device of one embodiment of the present invention, the circuit board on which the wiring pattern is formed, the semiconductor chip bonded to the wiring pattern via the protruding electrode, and the bonding portion of the protruding electrode are adjacent to each other. And an insulating layer formed so as to cover a part of the wiring pattern.
Thereby, even when the protruding electrode swells when the protruding electrode is joined, and the interval between the wiring patterns arranged between the protruding electrodes becomes narrow, it is possible to prevent the protruding electrode and the wiring pattern from contacting each other. It is possible to prevent a short circuit between the protruding electrodes arranged in a staggered pattern and the wiring while corresponding to the miniaturization of the wiring.

また、本発明の一態様に係る半導体装置によれば、配線パターンが形成された回路基板
と、突出電極を介して前記配線パターンに接合された半導体チップと、前記突出電極の接
合部に隣接する部分の配線パターンを覆うように形成された絶縁層と、前記突出電極の接
合部との間隔に対して前記絶縁層との間隔が広がるようにして前記配線パターン上に形成
されたソルダーレジストと、前記半導体チップと前記回路基板との間を封止する封止樹脂
とを備えることを特徴とする。
これにより、配線パターンを覆うように絶縁層が形成されている場合においても、回路
基板上にフェースダウン実装された半導体チップ下に絶縁層とソルダーレジストとの間の
隙間を介して封止樹脂を流し込むことが可能となり、半導体チップの封止を安定して行う
ことが可能となる。 According to the semiconductor device of one embodiment of the present invention, the circuit board on which the wiring pattern is formed, the semiconductor chip bonded to the wiring pattern via the protruding electrode, and the bonding portion of the protruding electrode are adjacent to each other. A solder resist formed on the wiring pattern in such a manner that a gap between the insulating layer formed so as to cover a portion of the wiring pattern and a gap between the protruding electrode and the insulating layer is widened; A sealing resin for sealing between the semiconductor chip and the circuit board is provided.
As a result, even when the insulating layer is formed so as to cover the wiring pattern, the sealing resin is applied via the gap between the insulating layer and the solder resist under the semiconductor chip face-down mounted on the circuit board. Therefore, the semiconductor chip can be stably sealed.

また、本発明の一態様に係る半導体装置によれば、前記配線パターンに沿った絶縁層の
長さは前記突出電極の接合部の長さよりも大きいことを特徴とする。
これにより、突出電極の接合時に突出電極が膨らみ、突出電極間に配置された配線パタ
ーンとの間隔が狭くなった場合においても、突出電極と配線とのショートを防止すること
が可能となる。 In addition, according to the semiconductor device of one embodiment of the present invention, the length of the insulating layer along the wiring pattern is longer than the length of the joint portion of the protruding electrode.
As a result, even when the protruding electrodes swell when the protruding electrodes are joined and the interval between the wiring patterns arranged between the protruding electrodes becomes narrow, it is possible to prevent a short circuit between the protruding electrode and the wiring.

また、本発明の一態様に係る半導体装置の製造方法によれば、突出電極が接合される配
線パターンを絶縁性基材上に形成する工程と、インクジェット法にて樹脂を吐出させるこ
とにより、前記突出電極の接合部に隣接する部分の配線パターンを覆うように絶縁層を形
成する工程とを備えることを特徴とする。
これにより、突出電極の接合部に隣接する部分の配線パターンを覆うように絶縁層を精
度よく形成することができ、配線の微細化に対応しつつ、千鳥配列された突出電極と配線
とのショートを防止することが可能となる。 In addition, according to the method for manufacturing a semiconductor device according to one embodiment of the present invention, the step of forming a wiring pattern to which the protruding electrode is bonded on the insulating substrate, and discharging the resin by an inkjet method, And a step of forming an insulating layer so as to cover a portion of the wiring pattern adjacent to the joint portion of the protruding electrode.
As a result, the insulating layer can be formed with high precision so as to cover the wiring pattern of the portion adjacent to the joint portion of the protruding electrode, and the short circuit between the protruding electrodes and the wiring arranged in a staggered manner while corresponding to the miniaturization of the wiring. Can be prevented.

以下、本発明の実施形態に係る半導体装置およびその製造方法について図面を参照しな
がら説明する。
図１（ａ）は、本発明の第１実施形態に係る半導体装置の概略構成を示す断面図、図１
（ｂ）は、本発明の第１実施形態に係る半導体装置の概略構成を示す平面図、図１（ｃ）
は、図１（ｂ）の突出電極５の部分を拡大して示す平面図である。 Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a sectional view showing a schematic configuration of the semiconductor device according to the first embodiment of the present invention.
FIG. 1B is a plan view showing a schematic configuration of the semiconductor device according to the first embodiment of the present invention, and FIG.
These are the top views which expand and show the part of the protrusion electrode 5 of FIG.1 (b).

図１において、絶縁性基材１上には、配線パターン２が形成されるとともに、端部が露
出したまま配線パターン２が覆われるようにソルダーレジスト３が形成されている。また
、半導体チップ４には突出電極５が形成されている。そして、突出電極５を配線パターン
２上に接合させることにより、半導体チップ４が絶縁性基材１上にフェースダウン実装さ
れている。そして、半導体チップ４と絶縁性基材１との間には封止樹脂６が注入され、半
導体チップ４の表面が封止されている。ここで、図１（ｃ）に示すように、突出電極５は
千鳥配列されている。そして、半導体チップ４上で内側に配置された突出電極５ａに接続
される配線パターン２ａは、半導体チップ４上で外側に配置された突出電極５ｂの間を通
るようにして突出電極５ａに達するように構成されている。そして、半導体チップ４上で
外側に配置された突出電極５ｂの接合部に隣接する部分の配線パターン２ａを覆うように
絶縁層７が形成されている。 In FIG. 1, a wiring pattern 2 is formed on an insulating substrate 1, and a solder resist 3 is formed so that the wiring pattern 2 is covered with the end portions exposed. A protruding electrode 5 is formed on the semiconductor chip 4. Then, the semiconductor chip 4 is face-down mounted on the insulating substrate 1 by bonding the protruding electrode 5 onto the wiring pattern 2. A sealing resin 6 is injected between the semiconductor chip 4 and the insulating substrate 1 to seal the surface of the semiconductor chip 4. Here, as shown in FIG. 1C, the protruding electrodes 5 are staggered. Then, the wiring pattern 2a connected to the protruding electrode 5a disposed on the inner side on the semiconductor chip 4 reaches the protruding electrode 5a so as to pass between the protruding electrodes 5b disposed on the outer side on the semiconductor chip 4. It is configured. An insulating layer 7 is formed so as to cover a portion of the wiring pattern 2a adjacent to the joint portion of the protruding electrode 5b disposed outside on the semiconductor chip 4.

これにより、突出電極５ｂの接合時に突出電極５ｂが膨らみ、突出電極５ｂ間に配置さ
れた配線パターン２ｂとの間隔が狭くなった場合においても、突出電極５ｂと配線パター
ン２ｂとが接触することを防止することができ、配線パターン２ａ、２ｂの微細化に対応
しつつ、千鳥配列された突出電極５ａ、５ｂと配線パターン２ａ、２ｂとのショートを防
止することが可能となる。 As a result, when the protruding electrode 5b is joined, the protruding electrode 5b swells and the protruding electrode 5b and the wiring pattern 2b come into contact with each other even when the distance from the wiring pattern 2b arranged between the protruding electrodes 5b is narrowed. It is possible to prevent the short-circuit between the protruding electrodes 5a and 5b arranged in a staggered manner and the wiring patterns 2a and 2b while corresponding to the miniaturization of the wiring patterns 2a and 2b.

なお、絶縁性基材１としては、例えば、テープ基板またはフィルム基板を用いることが
でき、絶縁性基材１の材質としては、例えば、ポリイミド樹脂やアミドイミド樹脂、エス
テルイミド樹脂、エーテルイミド樹脂、シリコーン樹脂、アクリル樹脂、ポリエステル樹
脂、ポリエチレン樹脂あるいはこれらの変性樹脂などを用いることができる。また、突出
電極５の材料としては、例えば、銅Ｃｕ、ニッケルＮｉ、金Ａｕなどを用いることができ
る。また、銅Ｃｕで形成された突出電極５上には、ニッケルＮｉ、錫Ｓｎまたは金Ａｕな
どのキャップ層を形成してもよく、突出電極５上に形成されたキャップ層を介して半田層
を形成するようにしてもよい。 As the insulating substrate 1, for example, a tape substrate or a film substrate can be used, and as the material of the insulating substrate 1, for example, a polyimide resin, an amideimide resin, an esterimide resin, an etherimide resin, silicone Resins, acrylic resins, polyester resins, polyethylene resins, or modified resins thereof can be used. Moreover, as a material of the protruding electrode 5, for example, copper Cu, nickel Ni, gold Au, or the like can be used. Further, a cap layer such as nickel Ni, tin Sn or gold Au may be formed on the protruding electrode 5 made of copper Cu, and a solder layer is formed via the cap layer formed on the protruding electrode 5. You may make it form.

また、突出電極５を配線パターン２に接合させる場合、ＡＣＦ（Ａｎｉｓｏｔｒｏｐｉ
ｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合、ＮＣＦ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｆ
ｉｌｍ）接合、ＡＣＰ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）
接合、ＮＣＰ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接合などの圧接接合を用いる
ようにしてもよいし、半田接合や合金接合などの金属接合を用いるようにしてもよい。 When the protruding electrode 5 is bonded to the wiring pattern 2, an ACF (Anisotropi) is used.
c Conductive Film (NC) junction, NCF (Nonconductive F)
ilm) junction, ACP (Anisotropic Conductive Paste)
Pressure bonding such as bonding or NCP (Nonductive Paste) bonding may be used, or metal bonding such as solder bonding or alloy bonding may be used.

また、配線パターンが形成された絶縁性基材１は、例えば、ＴＡＢ（Ｔａｐｅ Ａｕｔ
ｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）、ＴＣＰ（Ｔａｐｅ Ｃａｒｒｉｅｒ Ｐａｃｋａｇｅ
）、ＣＯＦ（Ｃｈｉｐ Ｏｎ Ｆｉｌｍ）などに用いることができる。
また、絶縁層７の材質としては、例えば、レジストやアンダーフィルなどの樹脂を用い
ることができ、絶縁層７の形成方法としては、例えば、インクジェット法やフォトエッチ
ング技術を用いることができる。また、配線パターン２ａに沿った絶縁層７の長さは突出
電極５ｂの接合部の長さよりも大きいことが好ましい。 The insulating base material 1 on which the wiring pattern is formed is, for example, TAB (Tape Out).
automated Bonding), TCP (Tape Carrier Package)
), COF (Chip On Film), and the like.
Moreover, as a material of the insulating layer 7, for example, a resin such as a resist or an underfill can be used. As a method for forming the insulating layer 7, for example, an inkjet method or a photo etching technique can be used. The length of the insulating layer 7 along the wiring pattern 2a is preferably larger than the length of the joint portion of the protruding electrode 5b.

図２（ａ）は、本発明の第２実施形態に係る半導体装置の概略構成を示す断面図、図２
（ｂ）は、本発明の第２実施形態に係る半導体装置の概略構成を示す平面図、図２（ｃ）
は、図２（ｂ）の突出電極５の部分を拡大して示す平面図である。
図２において、図１の絶縁性基材１上にはソルダーレジスト３の代わりに、ソルダーレ
ジスト３´が形成されている。ここで、ソルダーレジスト３´は、半導体チップ４上で外
側に配置された突出電極５ｂの接合部との間隔に対して絶縁層７との間隔が広がるように
して配線パターン２ａ、２ｂ上に形成されている。 FIG. 2A is a sectional view showing a schematic configuration of a semiconductor device according to the second embodiment of the present invention.
FIG. 2B is a plan view showing a schematic configuration of the semiconductor device according to the second embodiment of the present invention, and FIG.
These are the top views which expand and show the part of the protrusion electrode 5 of FIG.2 (b).
In FIG. 2, a solder resist 3 ′ is formed on the insulating substrate 1 in FIG. 1 instead of the solder resist 3. Here, the solder resist 3 ′ is formed on the wiring patterns 2 a and 2 b so that the distance between the solder resist 3 ′ and the insulating layer 7 is wider than the distance between the protruding portion 5 b disposed on the semiconductor chip 4. Has been.

これにより、配線パターン２ａ、２ｂを覆うように絶縁層７が形成されている場合にお
いても、絶縁層７とソルダーレジスト３´との間の隙間を介して封止樹脂６を流し込むこ
とが可能となり、絶縁性基材１上にフェースダウン実装された半導体チップ４の封止を安
定して行うことが可能となる。
なお、上述した半導体装置は、例えば、液晶表示装置、携帯電話、携帯情報端末、ビデ
オカメラ、デジタルカメラ、ＭＤ（Ｍｉｎｉ Ｄｉｓｃ）プレーヤ、ＩＣカード、ＩＣタ
グなどの電子機器に適用することができ、電子機器の小型・軽量化を可能としつつ、電子
機器の信頼性を向上させることができる。 Thereby, even when the insulating layer 7 is formed so as to cover the wiring patterns 2a and 2b, the sealing resin 6 can be poured through the gap between the insulating layer 7 and the solder resist 3 '. The semiconductor chip 4 face-down mounted on the insulating base 1 can be stably sealed.
Note that the semiconductor device described above can be applied to electronic devices such as a liquid crystal display device, a mobile phone, a portable information terminal, a video camera, a digital camera, an MD (Mini Disc) player, an IC card, and an IC tag. The electronic device can be reduced in size and weight, and the reliability of the electronic device can be improved.

また、上述した実施形態では、半導体チップの実装方法を例にとって説明したが、本発
明は、必ずしも半導体チップの実装方法に限定されることなく、例えば、弾性表面波（Ｓ
ＡＷ）素子などのセラミック素子、光変調器や光スイッチなどの光学素子、磁気センサや
バイオセンサなどの各種センサ類などの実装方法に適用してもよい。 In the above-described embodiment, the semiconductor chip mounting method has been described as an example. However, the present invention is not necessarily limited to the semiconductor chip mounting method. For example, the surface acoustic wave (S
You may apply to mounting methods, such as ceramic elements, such as an AW) element, optical elements, such as an optical modulator and an optical switch, and various sensors, such as a magnetic sensor and a biosensor.

本発明の第１実施形態に係る半導体装置の概略構成を示す図。1 is a diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. 本発明の第２実施形態に係る半導体装置の概略構成を示す図。The figure which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment of this invention.

符号の説明Explanation of symbols

１ 絶縁性基材、２、２ａ、２ｂ 配線パターン、３、３´ ソルダーレジスト、４
半導体チップ、５、５ａ、５ｂ 突出電極、６ 封止樹脂、７ 絶縁層 1 Insulating substrate, 2, 2a, 2b Wiring pattern, 3, 3 'Solder resist, 4
Semiconductor chip, 5, 5a, 5b Projecting electrode, 6 Sealing resin, 7 Insulating layer

Claims (6)

突出電極が接合される配線パターンが形成された絶縁性基材と、
前記突出電極の接合部に隣接する部分の配線パターンを覆うように形成された絶縁層と
を備えることを特徴とする回路基板。 An insulating substrate on which a wiring pattern to which the protruding electrode is bonded is formed;
A circuit board comprising: an insulating layer formed so as to cover a portion of the wiring pattern adjacent to the joint of the protruding electrode. 突出電極が接合される配線パターンが形成された絶縁性基材と、
前記突出電極の接合部に隣接する部分の配線パターンを覆うように形成された絶縁層と
、
前記突出電極の接合部との間隔に対して前記絶縁層との間隔が広がるようにして前記配
線パターン上に形成されたソルダーレジストとを備えることを特徴とする回路基板。 An insulating substrate on which a wiring pattern to which the protruding electrode is bonded is formed;
An insulating layer formed so as to cover the wiring pattern of the portion adjacent to the joint portion of the protruding electrode;
A circuit board, comprising: a solder resist formed on the wiring pattern such that a distance between the protruding layer and the insulating layer is larger than a distance between the protruding part and the bonding part. 配線パターンが形成された回路基板と、
突出電極を介して前記配線パターンに接合された半導体チップと、
前記突出電極の接合部に隣接する部分の配線パターンを覆うように形成された絶縁層と
を備えることを特徴とする半導体装置。 A circuit board on which a wiring pattern is formed;
A semiconductor chip bonded to the wiring pattern via a protruding electrode;
A semiconductor device comprising: an insulating layer formed so as to cover a portion of the wiring pattern adjacent to the joint portion of the protruding electrode. 配線パターンが形成された回路基板と、
突出電極を介して前記配線パターンに接合された半導体チップと、
前記突出電極の接合部に隣接する部分の配線パターンを覆うように形成された絶縁層と
、
前記突出電極の接合部との間隔に対して前記絶縁層との間隔が広がるようにして前記配
線パターン上に形成されたソルダーレジストと、
前記半導体チップと前記回路基板との間を封止する封止樹脂とを備えることを特徴とす
る半導体装置。 A circuit board on which a wiring pattern is formed;
A semiconductor chip bonded to the wiring pattern via a protruding electrode;
An insulating layer formed so as to cover the wiring pattern of the portion adjacent to the joint portion of the protruding electrode;
A solder resist formed on the wiring pattern in such a manner that the gap between the insulating layer and the gap between the projecting electrodes and the insulating layer is widened;
A semiconductor device comprising: a sealing resin that seals between the semiconductor chip and the circuit board. 前記配線パターンに沿った絶縁層の長さは前記突出電極の接合部の長さよりも大きいこ
とを特徴とする請求項３または４記載の半導体装置。 5. The semiconductor device according to claim 3, wherein a length of the insulating layer along the wiring pattern is larger than a length of a joint portion of the protruding electrode. 突出電極が接合される配線パターンを絶縁性基材上に形成する工程と、
インクジェット法にて樹脂を吐出させることにより、前記突出電極の接合部に隣接する
部分の配線パターンを覆うように絶縁層を形成する工程とを備えることを特徴とする半導
体装置の製造方法。 Forming a wiring pattern to which the protruding electrode is bonded on the insulating substrate;
And a step of forming an insulating layer so as to cover a portion of the wiring pattern adjacent to the joint portion of the protruding electrode by discharging a resin by an inkjet method.
JP2006020100A 2006-01-30 2006-01-30 Circuit board, semiconductor device, and method for manufacturing semiconductor device Withdrawn JP2007201308A (en)

Priority Applications (1)

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JP2006020100A JP2007201308A (en) 2006-01-30 2006-01-30 Circuit board, semiconductor device, and method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006020100A JP2007201308A (en) 2006-01-30 2006-01-30 Circuit board, semiconductor device, and method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2007201308A true JP2007201308A (en) 2007-08-09

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Country Status (1)

Country Link
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