JP2007194799A - Operational amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To carry out protective operation in a short time by reducing voltage necessary for protection operation of a buffer circuit, and to reduce the number of elements while a current limitation is operated as in a conventional case. <P>SOLUTION: The operational amplifier includes a differential amplifier circuit 10 with an input protective circuit 11, an intermediate amplifier circuit 20, and a buffer circuit 30. In the buffer circuit 30, differential outputs of an intermediate amplifier are received by a pair of emitter followers having loads of a low current source, and passed through a level shift circuit, and at the same time a complementary output stage made up of transistors Q13, Q14 is provided. In addition, as for the current at the output stage, a buffer protective circuit made up of resistors R13, R14 connected to each emitter of Q13, Q14, and detection transistors QA1, QA2 is provided. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an operational amplifier designed to protect a buffer circuit when a large amplitude is input in a high-speed operation state.

  FIG. 2 shows a configuration example of a conventional operational amplifier. Q1, Q2, Q7 to Q9, Q12, Q13 and Q15 are NPN transistors, Q3 to Q6, Q10, Q11, Q14 and Q16 are PNP transistors, R1 to R4, R7, R8, R13 and R14 are resistors, and Cc is phase compensation. Capacitors DA1 to DA8, D1 to D10 are diodes, I1 to I3 are current sources, and B1 and B2 are bias sources.

  Here, the transistors Q1 to Q4, the resistors R1 to R4, the diodes DA1 to DA8, the bias source B1, and the current source I1 constitute a differential amplifier circuit 10. Transistors Q5 to Q8, resistors R7 and R8, diodes D1 and D2, capacitor Cc, and bias source B2 constitute intermediate amplifier circuit 20. Transistors Q9 to Q16, current sources I2 and I3, diodes D3 to D10, and resistors R13 and R14 constitute a buffer circuit 30A.

In the differential amplifier circuit 10, a series circuit of diodes DA1 to DA4 and a series circuit of diodes DA5 to DA8 are connected between the inverting input terminal IN− and the non-inverting input terminal IN + so as to be in antiparallel. An input protection circuit 11 is configured. The differential input withstand voltage VMAX of the differential amplifier circuit 10 is biased by the bias voltage from the current source I1 to the base-emitter voltage VBE2 and the resistors R2 and R1 of the transistor Q2 when viewed from the normal input terminal IN + of the differential amplifier circuit 10. It is obtained from the voltage drops VR2, VR1 generated by the current I1 / 2 flowing and the base-emitter reverse breakdown voltage VEB1 of the transistor Q1, and is as shown in the following equation.
VMAX = VBE2 + VR2 + VR1 + VEB1 (1)

On the other hand, when the operational amplifier of FIG. 2 is connected to the inverting input terminal IN− and the output terminal OUT to form a voltage follower as shown in FIG. 3, a low voltage is applied to the normal input terminal IN +. When the pulse signal S1 having a high voltage VH is input as the input voltage VIN +, the voltage VOUT at the output terminal OUT is fed back. Therefore, when the voltage at the inverting input terminal IN− is VIN−, VOUT = VIN−. It becomes. As a result, the voltage difference VERR between the input terminals applied between the input terminals IN− and IN + is as follows.
VERR = (VIN +) − (VIN−)
= (VIN +)-VOUT (2)

This input terminal voltage difference VERR is a variable that applies to all voltage signals from DC to pulse. In order for the operational amplifier not to be destroyed, the following equation must be maintained.
VERR ≦ VMAX (3)
As shown in Fig. 4 (VIN + is a broken line and VIN- is a solid line) during low-speed operation, equation (3) can be satisfied, but during high-speed operation, the delay of voltage VOUT increases, so equation (3) cannot be satisfied and input There is a case where the voltage difference VERR between terminals exceeds the differential input withstand voltage VMAX.

Therefore, conventionally, in order to avoid this, the above-described input protection circuit 11 is connected between the inverting input terminal IN− and the normal rotation input terminal IN +. When the forward voltages of the diodes DA1 to DA8 are VDA1 to VDA8, the differential input regulation voltage VID is
VID = VDA1 + VDA2 + VDA3 + VDA4
+ VDA5 + VDA6 + VDA7 + VDA8 (4)
It can be expressed as This differential input regulation voltage VID is different from the differential input withstand voltage VMAX.
VMAX ≧ VID (5)
Is set to By inserting the input protection circuit 11 in this way, as shown in FIG. 5, the voltage difference VERR between the input terminals of the inverting input voltage VIN− and the normal input voltage VIN + does not exceed the differential input withstand voltage VMAX. And the following equation can be satisfied.
VERR ≦ VID (6)

In the normal operation of the operational amplifier shown in FIG. 2, when the normal input voltage VIN + rises, the voltage VP at the internal node P rises while maintaining a certain slope of the slew rate SR. This slew rate SR is determined by the current source I1 and the capacitor Cc.
SR = I1 / Cc (7)
It is represented by Since the output voltage VOUT of the operational amplifier is transmitted through the buffer circuit 30A, the potential of the voltage VP at the node P rises at the same potential with the above slew rate gradient at the time of low speed operation. Therefore,
VOUT = VP (8)
(FIG. 4).

However, when the normal input voltage VIN + rises at a high speed, the input protection circuit 11 operates and VOUT = VIN− is maintained. At this time, since the voltage VP changes while maintaining the original slew rate SR at the node P, the feedback loop is cut between the node P and the output terminal OUT, and the above-described equation (8) Is not satisfied, and between the node P and the output terminal OUT,
VV0 = VOUT-VP (9)
Is generated. This voltage VV0 gives a reverse voltage timing to the junction between the base and emitter of the transistors Q9 to Q14. When the voltage VV0 increases, a voltage exceeding the base-emitter reverse breakdown voltage is applied. Will be. In particular, at time t2 in FIG. 5, the voltage VV0 reaches the maximum value V01, so that the transistor Q14 operates in a direction to draw a large current from the output terminal OUT. This means that an excessive current flows through the emitter junction of the transistor Q14, which leads to damage of the transistor Q14.

As described above, in the operational amplifier of FIG. 2, as a countermeasure for preventing the generation of the voltage VV0, the diodes D5 to D8 are connected in the reverse direction between the bases and emitters of the transistors Q11 to Q14, and the circulation path to the node P is obtained. This constitutes a buffer protection circuit in which is created. In addition, a current limiting circuit (for example, see Patent Document 1) using transistors Q15 and Q16 is inserted for limiting excessive current.
JP-A-4-127602

  However, in the operational amplifier shown in FIG. 2, the number of diodes increases as the number of internal stages of the buffer circuit 30A increases, and the voltage VV0 needs to reach a large value corresponding to the total diodes in order to operate the buffer protection circuit. There is. Further, a delay time for increasing the voltage by the number of diodes of the buffer protection circuit is generated, and the current limiting circuit continues to operate during that time. However, the stability design for the operation during this time is almost impossible because it deals with a sudden change in a short time, so this time should be short.

  An object of the present invention is to provide an operational amplifier in which a protection operation is performed in a short time by reducing a voltage necessary for a buffer protection operation, and the current limit is operated as before, and the number of elements is reduced. is there.

In order to achieve the above object, the invention according to claim 1 is directed to a differential amplifier circuit in which an input protection circuit for setting a differential input regulation voltage is connected between differential input terminals, and an output of the differential amplifier circuit. An operational amplifier comprising an intermediate amplifier circuit that amplifies a signal, a buffer circuit that amplifies an output signal of the intermediate amplifier circuit, and a buffer protection circuit that performs a protection operation of the buffer circuit, wherein the intermediate amplifier circuit includes: A PNP first transistor and an NPN second transistor that are differentially turned on in response to a differential output signal of the differential amplifier circuit, and charged by the first transistor and discharged by the second transistor. A phase compensation capacitor, wherein the buffer circuit transfers the voltage of the capacitor, and an output side of the crossover distortion prevention circuit. An NPN third transistor and a PNP fourth transistor that are push-pull connected via two resistors having a common connection point as an output terminal, and the buffer protection circuit includes an emitter of the third transistor The base is connected to the output terminal, the emitter is connected to the output terminal, the collector is connected to the capacitor, the NPN fifth transistor, the emitter of the fourth transistor is connected to the base, and the emitter is connected to the output terminal. And a PNP sixth transistor having a collector and a collector connected to the capacitor.
The invention according to claim 2 is the invention according to claim 1, wherein the intermediate amplifier circuit includes a first diode and a second diode between a collector of the first transistor and a collector of the second transistor. Forward-connected, the capacitor is connected to a common connection point of the first diode and the second transistor, and the fifth connection point is connected to a common connection point of the collector of the first diode and the first transistor. A collector of the transistor is connected, and a collector of the sixth transistor is connected to a common connection point between the second diode and the collector of the second transistor.
According to a third aspect of the present invention, in the second aspect of the present invention, the crossover distortion prevention circuit of the intermediate amplifier circuit includes a PNP seventh transistor having a base connected to a collector of the first transistor. , An NPN eighth transistor having a base connected to the emitter of the seventh transistor, an emitter connected to the base of the third transistor, and an NPN having a base connected to the collector of the second transistor. A ninth transistor, and a PNP tenth transistor having a base connected to the emitter of the ninth transistor and an emitter connected to the base of the fourth transistor.

  According to the present invention, the voltage necessary for the protection operation is a voltage obtained by adding the forward voltage of the diode between the base and collector of the fifth and sixth transistors of the buffer protection circuit or the diode connected to the capacitor. In addition, since the protection operation starts at a stage where the voltage VV0 is low, the protection is performed in a short time. In addition, the current limit operates as usual, and only two transistors are necessary. This is shared by the buffer protection operation and the current limit operation, so that the number of elements is greatly reduced.

  Hereinafter, embodiments of the operational amplifier of the present invention will be described. FIG. 1 is a diagram showing a configuration example of an operational amplifier according to the embodiment. Q1, Q2, Q7-Q9, Q12, Q13, QA1 are NPN transistors, Q3-Q6, Q10, Q11, Q14, QA2 are PNP transistors, R1-R4, R7, R8, R13, R14 are resistors, and Cc is phase compensation Capacitors DA1 to DA8, D1 to D10 are diodes, I1 to I3 are current sources, and B1 and B2 are bias sources.

  Here, the transistors Q1 to Q4, the resistors R1 to R4, the diodes DA1 to DA8, the bias source B1, and the current source I1 constitute a differential amplifier circuit 10. Transistors Q5 to Q8, resistors R7 and R8, diodes D1 and D2, capacitor Cc, and bias source B2 constitute intermediate amplifier circuit 20. Transistors Q9 to Q14, QA1 and QA2, current sources I2 and I3, diodes D3 and D4, and resistors R13 and R14 constitute a buffer circuit 30, of which transistors QA1 and QA2 constitute a buffer protection circuit, and transistors Q9 to Q9 Q12 and diodes D3 and D4 constitute a crossover distortion prevention circuit. The diodes D1 and D2 of the intermediate amplifier circuit 20 also constitute a crossover distortion prevention circuit.

  In relation to the claims, the first transistor is Q6, the second transistor is Q8, the third transistor is Q13, the fourth transistor is Q14, the fifth transistor is QA1, and the sixth transistor is QA2. The seventh transistor is Q10, the eighth transistor is Q12, the ninth transistor is Q9, and the tenth transistor is Q11.

  In the differential amplifier circuit 10, a series circuit of diodes DA1 to DA4 and a series circuit of diodes DA5 to DA8 are connected between the inverting input terminal IN− and the non-inverting input terminal IN + so as to be in antiparallel. The input protection circuit 11 is configured, and the differential input withstand voltage VMAX and the differential input regulation voltage VID of the differential amplifier circuit 10 satisfy the above-described equation (5).

  Now, as shown in FIG. 3, the voltage follower is configured by connecting the inverting input terminal IN− and the output terminal OUT of the operational amplifier, and the low voltage VL and the high voltage are applied to the normal rotation input terminal IN +. The operation when a VH pulse signal is input will be described.

  At the start of the operation, the normal input terminal IN + and the inverted input terminal IN− are at the same potential VL. Thereafter, when the voltage VH is applied to the non-inverting input terminal IN +, the transistor Q2 is turned on and the transistor Q1 is turned off. As a result, the transistor Q6 is turned on and Q5 is turned off. Q8 turns off. For this reason, the voltage VP at the node P rises toward the high potential VH, and the slew rate SR, which is the slope at that time, is expressed by the above equation (7). By delaying the output voltage VOUT with respect to the input voltage VIN +, a potential difference between input and output, that is, a voltage difference VERR between input terminals is generated (FIG. 4). At this time, the above equation (8) is satisfied.

  The above operation is a case where the rise of the input voltage VIN + is gradual. However, at the time of a higher speed operation with a steep rise, the input terminal voltage difference VERR reaches the differential input regulation voltage VID and the input protection circuit 11 operates. The inverting input terminal IN− is directly driven by the input signal source, and the output voltage VOUT becomes a voltage that changes while maintaining the difference of the voltage VERR with respect to the input voltage VIN +. For this reason, the feedback loop is broken between the node P and the output terminal OUT, the above equation (8) is not satisfied, the current of the output terminal OUT increases, and the transistors Q9 to Q14 of the buffer circuit 30 are increased. The reverse voltage VV0 shown in the equation (9) is applied between the base and the emitter of the first and second transistors.

  However, in this embodiment, since the buffer protection circuit composed of the transistors QA1 and QA2 is connected, when the above-described reverse voltage VV0 is generated between the node P and the output terminal OUT, the transistor QA1 is constituted by the base and collector. And the diode between the node P and the output terminal OUT is clamped with a voltage 2VBE (= V02) by the diode between the base and collector of the transistor QA1 and the diode D1 (FIG. 6). For this reason, the base-emitter junction of the transistors Q12 and Q13 can be prevented from being destroyed by application of a reverse voltage. At the same time as the reverse voltage VV0 is generated, the feedback loop is cut. At this time, since the transistor Q11 is turned on in the buffer circuit 30, the transistor Q14 is turned on to draw a large current, but this current is converted into a voltage by the resistor R14. The transistor QA2 is turned on and the current flowing into the transistor Q14 is shunted to limit the current. At the same time, the collector current of the transistor QA2 flows as the base current of the transistor Q9. VP is raised with respect to the output terminal OUT so as to be the potential difference of V02 described above.

  When a reverse voltage is generated when the input voltage VIN + falls, the transistor QA2 performs the same operation as the transistor QA1. FIG. 7 shows a simulation result of input / output characteristics during high-speed operation when the operational amplifier shown in FIG. 1 is operated with a voltage follower when the transistors QA1 and QA2 are not provided, and FIG. 8 shows the input when the transistors QA1 and QA2 are provided. The simulation results of output characteristics are given.

  The above is one embodiment, and various modifications are possible. For example, the crossover distortion prevention circuit including the transistors Q9 to Q14 of the buffer circuit 30 and the current sources I2 and I3 can be further provided in a plurality of stages.

1 is a circuit diagram of an operational amplifier according to one embodiment of the present invention. It is a circuit diagram of a conventional operational amplifier. It is the circuit diagram which comprised the operational amplifier as a voltage follower. It is an input-output characteristic figure at the time of low speed operation | movement at the time of making it operate | move by a voltage follower. It is the conventional input-output characteristic figure at the time of high-speed operation | movement at the time of making it operate | move by a voltage follower. It is an input-output characteristic figure of the present Example at the time of high-speed operation | movement at the time of making it operate | move by a voltage follower. FIG. 2 is an input / output characteristic diagram during high-speed operation when the operational amplifier of FIG. 1 is operated by a voltage follower when transistors QA1 and QA2 are not provided. FIG. 2 is an input / output characteristic diagram during high-speed operation when the operational amplifier of FIG. 1 is operated by a voltage follower when there are transistors QA1 and QA2.

Explanation of symbols

10: differential amplifier circuit, 11: input protection circuit, 20: intermediate amplifier circuit, 30A: buffer circuit

Claims (3)

A differential amplifier circuit in which an input protection circuit for setting a differential input regulation voltage is connected between the differential input terminals, an intermediate amplifier circuit for amplifying an output signal of the differential amplifier circuit, and an output signal of the intermediate amplifier circuit An operational amplifier including a buffer circuit that amplifies the buffer circuit and a buffer protection circuit that performs a protection operation of the buffer circuit,
The intermediate amplifier circuit is charged by the first transistor and the first transistor of the PNP and the second transistor of the NPN that are differentially turned on in response to the differential output signal of the differential amplifier circuit. A capacitor for phase compensation discharged by the second transistor,
An NPN in which the buffer circuit is push-pull connected via a crossover distortion prevention circuit that transfers the voltage of the capacitor and two resistors whose common connection point is an output terminal on the output side of the crossover distortion prevention circuit A third transistor and a PNP fourth transistor,
The buffer protection circuit includes an NPN fifth transistor having a base connected to an emitter of the third transistor, an emitter connected to the output terminal, and a collector connected to the capacitor; A PNP sixth transistor having a base connected to the emitter, an emitter connected to the output terminal, and a collector connected to the capacitor;
An operational amplifier characterized by that. The operational amplifier according to claim 1,
In the intermediate amplifier circuit, a first diode and a second diode are forward-connected between a collector of the first transistor and a collector of the second transistor, and the first diode and the second transistor The capacitor is connected to a common connection point, the collector of the fifth transistor is connected to the common connection point of the first diode and the collector of the first transistor, and the second diode and the second diode are connected. An operational amplifier, characterized in that the collector of the sixth transistor is connected to a common connection point with the collector of the transistor. The operational amplifier according to claim 2, wherein
The crossover distortion prevention circuit of the intermediate amplifier circuit includes a PNP seventh transistor whose base is connected to the collector of the first transistor, a base connected to the emitter of the seventh transistor, An NPN eighth transistor connected to the base of the third transistor, an NPN ninth transistor whose base is connected to the collector of the second transistor, and a base connected to the emitter of the ninth transistor And a PNP tenth transistor having an emitter connected to a base of the fourth transistor.

Images