JP2007194245A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a capacitor cell having a surface area expanded with high precision in the step for forming the capacitor cell constituting a semiconductor memory. <P>SOLUTION: The process for fabricating a semiconductor device comprises a step for forming a multilayer film 104 by depositing a silicon oxide film 104a and an organic inorganic hybrid film 104b represented by SiC<SB>w</SB>H<SB>x</SB>O<SB>y</SB>N<SB>z</SB>(w>0, x≥0, y>0, z≥0) alternately on a semiconductor substrate 100, a step for forming an opening 106 in the multilayer film 104, a step for transforming a predetermined portion of the organic inorganic hybrid film 104b represented by SiC<SB>w</SB>H<SB>x</SB>O<SB>y</SB>N<SB>z</SB>(w>0, x≥0, y>0, z≥0) and exposed to the side face of the opening 106 in the multilayer film 104 into an oxide layer 108, and a step for forming protrusions and recesses 109 on the side face of the opening 106 in the multilayer film 104 by removing the oxide layer 108 selectively. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention mainly relates to a semiconductor device that expands the storage capacity of a charge storage capacity portion when manufacturing a memory element such as a DRAM (Dynamic Random Access Memory), and a manufacturing method thereof.

  In recent years, the development of the information society has been remarkable, and the demand for semiconductor memory devices has been rapidly expanding. Functionally, a device having a large storage capacity (capacitor) and capable of high-speed operation is required. Along with this, technological development relating to high integration and high-speed response or high reliability of semiconductor memory devices has been advanced.

  Among semiconductor memory devices, a DRAM (Dynamic Random Access Memory) is generally known as a device that can write and read stored information at any time. This DRAM is composed of an array of memory cells for accumulating a large amount of stored information and peripheral circuits necessary for input / output with the outside. Usually, a memory cell is composed of a MOS (Metal Oxide Semiconductor) transistor and a single capacitor connected to the MOS transistor, so that it is widely known as a one-transistor one-capacitor type memory cell. Since the memory cell has a simple structure, it is easy to improve the degree of integration of the memory cell array, and it is widely used in large-capacity memory storage devices. In addition, as a technique for realizing high integration and large capacity of a memory cell, an attempt has been made to increase the surface area of the storage capacitor portion in order to increase the amount of charge stored in the memory cell.

As a technique for increasing the surface area of the memory cell portion, for example, Patent Document 1 discloses a technique for forming irregularities on the side surfaces by etching a laminated film in which two or more types of insulating films having different etching rates are alternately deposited. It has been published. FIGS. 10A and 10B are excerpts of a part of the memory cell formation process in Patent Document 1. First, as shown in FIG. 10A, for example, the etching rate is different on the semiconductor substrate 10. A PTEOS film 11 and a BPSG film 12 are alternately deposited to form a laminated film 13. Next, as shown in FIG. 10B, the opening 14 and the concavo-convex portion 15 are formed on the side surface of the opening 14 in the laminated film 13 by using a dry etching technique or a wet etching technique. Next, after forming a lower electrode 16 made of a doped silicon film, a Ta ₂ O ₅ film 17 serving as a capacitor capacitance insulating film is deposited on the upper surface of the lower electrode 16. Next, a capacitor cell structure is completed by depositing a TiN film 18 serving as an upper electrode on the upper surface of the tantalum oxide film 17. In this method, the surface area of the capacitor cell can be increased by forming the uneven portion 15 on the surface of the capacitor cell.
JP 2003-133436 A

  However, when the surface area of the capacitor cell is enlarged using the above-described conventional method, there are the following problems. First, when unevenness is formed on the side surface of the opening of the laminated film by dry etching, a reaction product generated by a reaction with a polymer generated in plasma or a film to be etched during dry etching adheres to the side surface of the opening. The polymer and reaction product adhering to the side surface of the opening function to suppress the etching in the horizontal direction with respect to the side surface of the opening part. However, if this polymer or reactive organism adheres excessively, the etching in the horizontal direction to the side surface of the opening part is performed. Therefore, it is impossible to form a concavo-convex shape having a sufficient size. Even if the adhesion amount of the polymer or the reaction product is suppressed, the adhesion amount becomes non-uniform on the side surface of the opening, and therefore, etching in the horizontal direction proceeds non-uniformly with respect to the side surface of the opening. That is, it becomes difficult to form a desired uneven shape on the side surface of the opening.

  Next, when the laminated film is dry-etched to form a vertical opening, and then an uneven shape is formed on the side surface of the opening by wet etching, an insulating film having a different wet etching rate, for example, a laminated layer of a thermal oxide film and a BPSG film Or use a membrane. In this case, the wet etching rate is BPSG film> thermal oxide film. This is because B and P existing in the BPSG film have a function of increasing the wet etching rate, and the wet etching rate varies depending on the B and P concentrations. According to the study by the present inventor, it has been found that the impurity concentration in the BPSG film or the PSG film is difficult to be uniform throughout the film, and has a concentration gradient in the film. For this reason, in the laminated film using the BPSG film and the PSG film, when an uneven shape is formed on the side surface of the opening by wet etching, it becomes difficult to control the wet etching amount in the horizontal direction with respect to the side surface of the opening. That is, it becomes difficult to form a desired uneven shape on the side surface of the opening.

  In addition, since the BPSG film and the PSG film have a high relative dielectric constant, the memory operation due to the parasitic capacitance between adjacent capacitor cells can be reduced in response to the miniaturization and high integration of the semiconductor memory. Malfunctions sometimes occurred.

  Accordingly, an object of the present invention is to solve the above-described conventional drawbacks, and in the process of forming a capacitor cell, the surface area of the capacitor cell can be expanded with good controllability, and a malfunction of the memory operation can be achieved. It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof that can prevent the occurrence of the above.

In order to achieve the above object, a semiconductor device according to claim 1 of the present invention is a semiconductor device in which a capacitor cell is formed in a region including an opening formed on a semiconductor substrate, wherein silicon is formed on the semiconductor substrate. An opening is formed in a laminated film in which an oxide film and an organic-inorganic hybrid film represented by SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) are alternately deposited. The side surface of the opening is formed in a concavo-convex shape in which the portion of the organic-inorganic hybrid film is retreated.

According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a silicon oxide film on a semiconductor substrate; and an organic material represented by SiC _w H _x O _y N _z A process of forming a laminated film by alternately depositing inorganic hybrid films, a process of forming an opening in the laminated film, and converting a predetermined portion of the organic-inorganic hybrid film exposed on the side surface of the laminated film into an oxide layer And a step of selectively removing the oxide layer to form irregularities on the side surface of the opening of the multilayer film, and a step of forming capacitor cells on the multilayer film having irregularities.

  The method for manufacturing a semiconductor device according to claim 3 is the method for manufacturing a semiconductor device according to claim 2, wherein the step of converting the predetermined portion of the organic-inorganic hybrid film exposed on the side surface of the opening of the laminated film into an oxide layer is a radical. This is performed by irradiating the organic-inorganic hybrid film exposed on the side surface of the opening of the laminated film with the seed.

  A method for manufacturing a semiconductor device according to a fourth aspect is the method for manufacturing a semiconductor device according to the third aspect, wherein the radical species include an oxygen radical or a nitrogen radical.

  According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the second aspect, wherein the step of selectively removing the oxide layer is performed using a chemical solution containing fluorine.

  According to a sixth aspect of the present invention, in the method of manufacturing the semiconductor device according to the second aspect, the step of selectively removing the oxide layer is performed using a gas containing fluorine.

The method of manufacturing a semiconductor device according to claim 7, wherein a silicon oxide film and an organic material represented by SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) are formed on a semiconductor substrate. The step of forming the laminated film by alternately depositing the inorganic hybrid film, the step of forming the opening in the laminated film, and the predetermined portion of the organic-inorganic hybrid film exposed on the side of the opening of the laminated film are retracted by the film contraction A step of forming irregularities on the side surface of the opening of the multilayer film, and a step of forming capacitor cells on the multilayer film having the irregularities.

  The method for manufacturing a semiconductor device according to claim 8 is the method for manufacturing a semiconductor device according to claim 7, wherein the predetermined portion of the organic-inorganic hybrid film exposed on the side surface of the opening of the laminated film is retracted in the horizontal direction by film contraction. Is performed by applying thermal energy to the organic-inorganic hybrid film exposed on the side surface of the opening of the laminated film.

According to the semiconductor device of the first aspect of the present invention, a silicon oxide film and SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) are represented on the semiconductor substrate. An opening is formed in the laminated film in which the organic / inorganic hybrid film is alternately deposited, and the side surface of the opening has an uneven shape in which the portion of the organic / inorganic hybrid film is retreated. The surface area can be enlarged. In addition, since the surface area of the capacitor cell can be expanded with good controllability by using the organic / inorganic hybrid film, the capacitor cell capacity can be increased, and the occurrence of characteristic defects caused by variations in the cell capacity can be prevented. be able to. Furthermore, the relative dielectric constant of the organic-inorganic hybrid film represented by SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) is 3 or less, and a normal silicon oxide film The relative dielectric constant (3.9 to 4.5) is low. For this reason, the parasitic capacitance generated between adjacent capacitor cells can be reduced in response to the reduction in the distance between capacitor cells corresponding to the miniaturization and high integration of the semiconductor memory, and the memory operation caused by the parasitic capacitance between the capacitor cells. Can be prevented from occurring.

According to the method for manufacturing a semiconductor device according to claim 2 of the present invention, a silicon oxide film and SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) are formed on the semiconductor substrate. A step of forming a laminated film by alternately depositing organic-inorganic hybrid films represented by the following: a step of forming an opening in the laminated film, and a predetermined portion of the organic-inorganic hybrid film exposed on the side of the opening of the laminated film. Since the step of converting to an oxide layer and the step of selectively removing the oxide layer and forming irregularities on the side surface of the opening of the laminated film are performed, the desired irregular shape that is controlled with high precision is formed on the side surface of the opening. Can be formed. That is, it is possible to form a concavo-convex shape with good controllability by accurately converting a predetermined portion of the organic-inorganic hybrid film into an oxide layer and removing the oxide layer. For this reason, since the surface area of the capacitor cell can be increased with good controllability, it is possible to increase the capacitor cell capacity and to prevent the occurrence of characteristic defects caused by variations in cell capacity.

  According to a third aspect of the present invention, in the method for manufacturing a semiconductor device according to the second aspect, the step of converting a predetermined portion of the organic-inorganic hybrid film exposed on the side surface of the opening of the laminated film into an oxide layer includes converting radical species into the opening of the laminated film. The irradiation is preferably performed by irradiating the organic-inorganic hybrid film exposed on the side surface. In this case, an oxide layer is formed by the reactivity of the radical itself. Moreover, the predetermined part of the organic-inorganic hybrid film can be accurately converted into an oxide layer by controlling the parameter for irradiating radicals.

  According to a fourth aspect of the present invention, in the method for manufacturing a semiconductor device according to the third aspect, the radical species preferably includes an oxygen radical or a nitrogen radical. In the case of irradiation with oxygen radicals or nitrogen radicals, an oxide layer is formed by the reactivity of the radicals themselves, so that the organic-inorganic hybrid film can be converted into an oxide layer at a low temperature of 200 ° C. or lower. Therefore, it is very effective for a fine element pattern process in which a comprehensive heat treatment history (thermal budget) during a semiconductor integrated circuit manufacturing process such as source / drain activation is severe. Furthermore, when forming an opening in a laminated film in which a silicon oxide film and an organic / inorganic hybrid film are alternately deposited, it can be used in combination with an ashing process for removing a resist mask pattern after dry etching. It becomes possible to simplify.

  According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, the step of selectively removing the oxide layer is preferably performed using a chemical solution containing fluorine. Since the removal rate of the chemical solution containing fluorine is much higher in the oxide layer than in the organic-inorganic hybrid film, the oxide layer can be selectively removed.

  According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, the step of selectively removing the oxide layer is preferably performed using a gas containing fluorine. Even a gas containing fluorine has an effect equivalent to that of the fifth aspect.

According to the method for manufacturing a semiconductor device according to claim 7 of the present invention, a silicon oxide film and SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) are formed on the semiconductor substrate. A step of forming a laminated film by alternately depositing organic-inorganic hybrid films represented by the following: a step of forming an opening in the laminated film, and a predetermined portion of the organic-inorganic hybrid film exposed at the side of the opening of the laminated film The film is retracted by film contraction, and the step of forming irregularities on the side surface of the opening of the laminated film is performed, so that a desired uneven shape controlled with high accuracy can be formed on the side surface of the opening. That is, by investigating the heat shrinkage characteristics of the organic-inorganic hybrid film, a desired film shrinkage amount can be determined, so that an uneven shape with good controllability can be formed. For this reason, since the surface area of the capacitor cell can be increased with good controllability, it is possible to increase the capacitor cell capacity and to prevent the occurrence of characteristic defects caused by variations in cell capacity.

  The method for manufacturing a semiconductor device according to claim 7, wherein the step of retracting a predetermined portion of the organic-inorganic hybrid film exposed on the side surface of the opening of the laminated film in the horizontal direction by film shrinkage is performed by the opening of the laminated film. It is preferable to carry out by applying thermal energy to the organic-inorganic hybrid film exposed on the side surface. For example, when heat energy is applied to the organic / inorganic hybrid film, a part of C, O, H, and N constituting the organic / inorganic hybrid film is discharged from the film as a single element or reaction gas from the side surface of the opening of the laminated film. Is done. For this reason, it is considered that the volume of the organic-inorganic hybrid film is reduced in a predetermined portion on the side surface of the opening of the laminated film and is retracted horizontally.

  A first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (e) and FIGS. 2 (a) and 2 (b) are process sectional views showing a manufacturing process of a memory cell portion of a DRAM or a semiconductor integrated circuit including the DRAM in the first embodiment of the present invention. is there.

The main point of the manufacturing method according to the first embodiment of the present invention is a method of manufacturing a semiconductor device in which a capacitor cell is formed in a region including an opening formed on a semiconductor substrate, and a silicon oxide film and a semiconductor substrate are formed on the semiconductor substrate. Forming an opening in a laminated film in which organic-inorganic hybrid films represented by the general formula SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) are alternately deposited; By irradiating the side surface of the opening with oxygen radicals or nitrogen radicals to convert a predetermined portion of the organic-inorganic hybrid film exposed on the side surface of the opening into an oxide layer, the oxide layer is selectively removed, thereby An uneven shape is formed.

  FIG. 1 shows the manufacturing process of the memory cell portion in the case of irradiating oxygen radicals. However, in the case of irradiating nitrogen radicals, only the step (d) is different, and the other steps are the case of irradiating oxygen radicals. The same. A cross-sectional view of the step (d) of irradiation with nitrogen radicals is shown in FIG.

  First, as shown in FIG. 1A, a first silicon oxide film 101 (for example, a film thickness of 400 nm is formed by a CVD method) is formed on a semiconductor substrate 100. The first silicon oxide film 101 includes Contact holes reaching the source / drain diffusion layers of the semiconductor substrate 100 are patterned. Next, a polysilicon film is deposited on the first silicon oxide film 101 by, for example, 500 nm by a low pressure CVD method, and the polysilicon film other than the patterning portion is removed by using a CMP (Chemical Mechanical Polish) method or an etch back method. Thus, the plug 102 for electrically connecting the lower electrode of the capacitor and the source / drain region (not shown) of the substrate 100 is formed.

Next, as shown in FIG. 1B, a silicon nitride film 103 is deposited by 50 nm by, for example, a low pressure CVD method. Next, a PTEOS film 104a is deposited as a silicon oxide film by a thickness of 150 nm by a plasma CVD method. Further, one of the organic-inorganic hybrid films described above is SiC _w H _x O _y (w> 0, x ≧ 0, y>). The MSQ film (methylsilsesquioxane) 104b represented by 0) is deposited by plasma CVD to a thickness of 150 nm. By alternately repeating the deposition of the PTEOS film 104a and the MSQ film 104b, a laminated film 104 composed of five layers is formed. Next, a resist pattern 105 is formed on the laminated film 104 by photolithography.

  Next, as shown in FIG. 1C, an opening 106 having a vertical shape is formed in the laminated film 104 and the silicon nitride film 103 by the dry etching method using the resist pattern 105 as a mask to damage the MSQ film 104b. The resist pattern 105 is removed by performing an ashing process using hydrogen gas that is not applied and cleaning with sulfuric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

Here, an example of conditions for dry-etching the stacked film 104 is shown. In dry etching, a plasma etching apparatus provided with two or more high-frequency power sources capable of independently controlling plasma generation and ion energy control was used.
<Dry etching conditions>
Processing pressure: 5Pa
Upper applied power (for plasma generation): 1000W
Lower applied power (for ion energy control): 500W
Gas: CF ₄ / CHF ₃ / Ar / N ₂ = 30/30/800/150 ml / min
Wafer temperature: 0 ° C
Next, as shown in FIG. 1D, for example, the oxygen radical 107 is irradiated to the MSQ film 104b exposed on the side surface of the opening 106, and a predetermined portion (about 50 nm in the horizontal direction) of the MSQ film 104b is oxidized. 108. This process is performed in the same manner even when nitrogen radicals are irradiated instead of oxygen radicals.

  Next, as shown in FIG. 1E, the oxide layer 108 formed on the side surface of the opening portion 106 is selectively removed using a chemical solution containing, for example, HF 5%, so that the side surface of the opening portion 106 has a thickness of about 50 nm. A stacked film 110 having the uneven portion 109 is formed.

Next, as shown in FIG. 2A, a TiN film 111 to be a lower electrode of the capacitor cell is deposited on the laminated film 110 by, for example, 30 nm by plasma CVD, and the TiN film 111 other than the opening 106 is CMP ( Chemical mechanical polish) method or etch back method is used for removal. Next, a Ta ₂ O ₅ film 112 serving as a capacitor capacitance insulating film is deposited by CVD, for example, 8 nm, and a TiN film 113 serving as an upper electrode of the capacitor cell is deposited thereon by CVD, for example, 50 nm. Next, a resist pattern 114 is formed using a photolithography method.

  Next, as shown in FIG. 2B, after the TiN film 114 is dry-etched using the resist pattern 114 as a mask, the resist pattern 114 is removed by performing an ashing process and a cleaning process. In this way, the basic structure of the capacitor cell constituting the semiconductor memory element is completed.

  The feature of the process of this embodiment is in the process of FIGS. 1D and 1E, and the method for forming the oxide layer 108 shown in FIG. 1D will be described more specifically. In order to form the oxide layer 108, a plasma processing apparatus as shown in FIG. 3 is used.

  In FIG. 3, the processing chamber 201 of the plasma processing apparatus is grounded, and a gas whose flow rate is controlled by a mass flow controller (not shown) is introduced into the plasma generation chamber 203 through the introduction pipe 202. A high frequency power source 204 is connected to the plasma generation chamber 203, and gas is converted into plasma by the power supplied from the high frequency power source 204 to generate ions and radicals. Since the processing chamber 201 and the plasma generation chamber 203 are separated from each other, ions disappear in the middle and only radicals reach the processing chamber 201. A sample stage 205 is installed in the processing chamber 201. Although not shown, the temperature of the sample stage 205 is controlled in the range of about 100 ° C. to 300 ° C. by a heater or the like inside the sample stage 205. A temperature control device is provided. Furthermore, the pressure in the processing chamber 201 is controlled to a range of about 50 Pa to 200 Pa by a dry pump (not shown).

  A semiconductor substrate on which a laminated film 104 having an opening 106 is formed is placed on a sample stage 205 inside the plasma processing apparatus, and the MSQ film 104b exposed on the side surface of the opening 106 is irradiated with oxygen radicals 107 to oxidize the layer 108. Convert to

As specific conditions, when oxygen radicals are used, for example, by applying a processing pressure in the processing chamber 201: 100 Pa, a high frequency power: 1000 W, an O ₂ flow rate: 1000 ml / min, and a temperature of the sample stage 205: 250 ° C. The MSQ film 104b exposed on the side surface of the opening 106 can be converted into an oxide layer 108 of about 50 nm. By irradiating oxygen radicals to the film represented by the formula SiC _w H _x O _y (w> 0, x ≧ 0, y> 0), which is a generalization of the MSQ film, the C, H and oxygen radicals of the MSQ film are React,
SiC _w H _x O _y + O ^* → SiO _v (v = 1 to 2) + CO ₂ ↑ + H ₂ O ↑
It is considered that an oxide layer is formed through the following reaction process.

In the case of irradiation with nitrogen radicals, a plasma processing apparatus as shown in FIG. 3 is also used. Specific conditions include, for example, processing pressure in the processing chamber 201: 100 Pa, high-frequency power: 1000 W, N ₂ flow rate: 1000 ml. / Min, the temperature of the sample stage 205: Applying the conditions of 250 ° C., an oxide layer 302 of about 50 nm is formed on the MSQ film 104b exposed on the side surface of the opening 106 by the nitrogen radicals 301 as shown in FIG. can do. When the MSQ film is irradiated with nitrogen radicals, C, H, and N of the MSQ film react with nitrogen radicals,
SiC _w H _x O _y + N ^* → SiO _v (v = 1 to 2) + HCN ↑ + CN ↑ + etc ↑
It is considered that an oxide layer is formed through the following reaction process.

In the process of irradiating the MSQ film with oxygen and nitrogen radicals as described above, C and H contained in the MSQ film are combined with oxygen or nitrogen in the intermediate stage of the reaction, and finally become gas and diffuse from the MSQ film to the processing chamber. Exhausted to the outside. It is considered that only the SiO component remains on the surface of the MSQ film and is converted into an oxide layer. Further, when the process in which the surface layer of the MSQ film 104b is converted into the oxide layers 108 and 302, the Si—CH ₃ bond constituting the MSQ film 104b is converted into a Si—O bond by a chemical reaction with oxygen radicals and nitrogen radicals. It is thought that it is formed by changing to a Si—OH bond.

Thus, one of the features of the configuration of the present invention is that after exposing the organic-inorganic hybrid film on the side surface of the opening of the laminated film, the surface portion of the organic-inorganic hybrid film is transformed into an oxide layer. Actually, for example, oxygen radicals are generated by O ₂ plasma, formed, and irradiated to an MSQ film which is one of the organic-inorganic hybrid films. As shown in FIG. 4, only the Si—O bond spectrum appears strongly and remains according to the oxygen radical irradiation time. This indicates that C, H, etc. of the MSQ film are removed by oxygen radical irradiation and actually converted into an oxide layer.

In this way, there are Si—O and Si—OH bonds in the oxide layer, but dangling that is not bonded to O and OH in the bonds after C and N are extracted by oxygen radicals. There are many bonds. For this reason, the oxide layer has a lower density than a CVD silicon oxide film, a thermal oxide film, and the like, and is easily bonded to F ⁻ in the HF-containing chemical solution used in the step of FIG. On the other hand, the MSQ film 104b has a property that it is difficult to react with F ⁻ because electrons are supplied to the Si atoms from the methyl group and the number of dangling bonds is reduced. For this reason, in the step of FIG. 1E, if an HF-containing chemical solution is used, this oxide layer can be easily and selectively removed from the remaining MSQ film. That is, since the removal rate by the chemical solution is much higher in the oxide layers 108 and 302 than in the MSQ film 104b, the oxide layers 108 and 302 can be selectively removed (selection ratio: about 10). .

  As described above, in the manufacturing method according to the present embodiment, if the parameter irradiated with oxygen radicals or nitrogen radicals is changed, for example, the tendency shown in FIG. By controlling, a desired region of the MSQ film can be accurately converted into an oxide layer. Then, by removing the oxide layer formed with good controllability by wet etching using a HF-containing chemical solution, it is possible to form a concavo-convex shape with good controllability on the side surface of the opening of the laminated film constituting the capacitor cell part. . That is, since the surface area of the capacitor cell can be expanded with good controllability, it is possible to increase the capacitor cell capacity and to prevent the occurrence of characteristic defects caused by the variation in cell capacity.

  The method of irradiating nitrogen radicals is effective when an oxide layer is not formed in a portion other than the MSQ film because an oxide layer is not formed in a portion other than the MSQ film.

  In the method of irradiating oxygen radicals and nitrogen radicals, an oxide layer is formed by the reactivity of the radical itself, so that the MSQ film can be converted into an oxide layer at a low temperature of 300 ° C. or lower. Therefore, it is very effective for a fine element pattern process in which a comprehensive heat treatment history (thermal budget) during a semiconductor integrated circuit manufacturing process such as source / drain activation is severe.

  In this embodiment, the opening 106 is formed in the laminated film 104 by dry etching, the resist pattern 105 is removed by ashing and cleaning processes, and then the MSQ film is converted into an oxide layer by irradiation with oxygen radicals and nitrogen radicals. In the resist pattern ashing process after dry etching, the resist ashing and the conversion to the oxide layer of the MSQ film may be simultaneously performed using oxygen radicals or nitrogen radicals.

  A second embodiment of the present invention will be described with reference to FIGS. 7 (a) to 7 (d) and FIGS. 8 (a) and 8 (b) are process sectional views showing a manufacturing process of a memory cell portion of a DRAM or a semiconductor integrated circuit including the DRAM in the second embodiment of the present invention. It is.

The main point of the manufacturing method according to the second embodiment of the present invention is a method of manufacturing a semiconductor device in which a capacitor cell is formed in a region including an opening formed on a semiconductor substrate, and includes a silicon oxide film and a general formula SiC _w. An opening is formed in the laminated film in which organic-inorganic hybrid films represented by H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) are alternately deposited, and thermal energy is applied. By doing so, a predetermined portion of the organic-inorganic hybrid film exposed on the side surface of the opening is retreated in the horizontal direction by film contraction, thereby forming an uneven shape on the side surface of the opening.

  First, as shown in FIG. 7A, a first silicon oxide film 501 (for example, the film thickness is 400 nm by a CVD method) is formed on the semiconductor substrate 500. The first silicon oxide film 501 includes Contact holes reaching the source / drain diffusion layers of the semiconductor substrate 500 are patterned. Next, a polysilicon film is deposited on the first silicon oxide film 501 by, for example, 500 nm by a low pressure CVD method, and the polysilicon film other than the patterning portion is removed by using a CMP (Chemical Mechanical Polish) method or an etch back method. Thus, the plug 502 for electrically connecting the lower electrode of the capacitor and the source / drain region (not shown) of the substrate 500 is formed.

Next, as shown in FIG. 7B, a silicon nitride film 503 is deposited to a thickness of 50 nm by, for example, a low pressure CVD method. Next, a PTEOS film 504a as a silicon oxide film is deposited by plasma CVD at a temperature of 400 ° C. or less, for example, 150 nm, and is one of the organic-inorganic hybrid films described above. SiC _w H _x O _y (w> 0 , X ≧ 0, y> 0), an MSQ film (methylsilsesquioxane) 504b is deposited by plasma CVD at a temperature of 400 ° C. or lower, for example, 150 nm. By alternately depositing the PTEOS film 504a and the MSQ film 504b, a laminated film 504 having five layers is formed. Next, a resist pattern 505 is formed on the stacked film 104 by photolithography.

Next, as shown in FIG. 7C, an opening 506 having a vertical shape is formed in the stacked film 504 and the silicon nitride film 503 by using the resist pattern 505 as a mask by dry etching, thereby damaging the MSQ film 504b. The resist pattern 505 is removed by performing an ashing process using hydrogen gas that is not applied and cleaning with sulfuric acid or a mixed solution of sulfuric acid and hydrogen peroxide. Here, an example of conditions for dry etching the stacked film 504 is shown. In dry etching, a plasma etching apparatus provided with two or more high-frequency power sources capable of independently controlling plasma generation and ion energy control was used.
<Dry etching conditions>
Processing pressure: 5Pa
Upper applied power (for plasma generation): 1000W
Lower applied power (for ion energy control): 500W
Gas: CF ₄ / CHF ₃ / Ar / N ₂ = 30/30/800/150 ml / min
Wafer temperature: 0 ° C
For example, the opening size is set to 400 nm, and the interval between adjacent openings is set to 150 nm.

  Next, as shown in FIG. 7D, the semiconductor substrate having the laminated film 504 is heat-treated at 400 ° C. or more, and the surface of the MSQ film 504b exposed on the side surface of the opening 506 is retracted by about 30 nm. Then, a laminated film 508 having an uneven portion 507 of about 30 nm is formed on the side surface of the opening 506.

Next, as shown in FIG. 8A, a TiN film 509 to be a lower electrode of the capacitor cell is deposited on the stacked film 508 by, for example, 30 nm by plasma CVD, and the TiN film 509 other than the opening 506 is deposited by CMP ( Chemical mechanical polish) method or etch back method is used for removal. Next, a Ta ₂ O ₅ film 510 serving as a capacitor capacitance insulating film is deposited by CVD, for example, 8 nm, and a TiN film 511 serving as an upper electrode of the capacitor cell is deposited thereon by CVD, for example, 50 nm. Next, a resist pattern 512 is formed using a photolithography method.

  Next, as shown in FIG. 8B, after the TiN film 511 is dry-etched using the resist pattern 512 as a mask, the resist pattern 512 is removed by performing an ashing process and a cleaning process. In this way, the basic structure of the capacitor cell constituting the semiconductor memory element is completed.

  The feature of the process of the present embodiment is in the process of FIG. 7D, and the method for forming the uneven portion 507 shown in FIG.

  FIG. 9 is a graph showing the relationship between the film shrinkage rate of the MSQ film and the processing temperature when performing the heat treatment. The vertical axis of the graph represents the film shrinkage rate of the MSQ film, and the horizontal axis represents the treatment temperature. From this graph, it can be seen that when thermal energy is applied to the MSQ film, the MSQ film contracts. As a temperature characteristic of the film shrinkage, the film shrinkage gradually occurs until the processing temperature is about 300 ° C., and when the temperature reaches 300 ° C. or higher, the gradient of the film shrinkage becomes sharp, and then the film shrinkage gradually decreases again at 400 ° C. or higher. Show the tendency to become. As a result of examination by the inventors, it has been found that when the MSQ film is subjected to heat treatment at 400 ° C. or higher, film shrinkage of about 20% occurs compared to the film thickness before heat treatment. In the above embodiment, since the interval between the adjacent openings is set to 150 nm, the film shrinkage of about 30 nm occurs by performing the heat treatment at 400 ° C. or higher.

This is because the thermal energy is applied to the film represented by the formula SiC _w H _x O _y (w> 0, x ≧ 0, y> 0), which is a generalization of the MSQ film, thereby forming the H, O, It is considered that this occurs because the bond between C and Si is broken and each element is released from the film as a single element or as a reaction gas.

  As described above, in the manufacturing method according to the present embodiment, as an example, the method of forming the concavo-convex portion 507 on the side surface of the opening 506 using the film shrinkage due to the heat treatment of the MSQ film 504b has been described. The same effect can be obtained also in the organic-inorganic hybrid film. Therefore, by investigating the heat shrinkage characteristics of the organic / inorganic hybrid film, it is possible to determine the desired film shrinkage amount, and therefore, an uneven shape with good controllability is formed on the side surface of the opening of the laminated film constituting the capacitor cell part. be able to. Therefore, since the surface area of the capacitor cell can be expanded with good controllability, it is possible to increase the cell capacity of the capacitor cell and to prevent the occurrence of characteristic defects caused by the variation in cell capacity.

  In this embodiment, the heat treatment at 400 ° C. or higher is performed to retract the MSQ film in the horizontal direction, thereby forming the uneven portion on the side surface of the opening. However, the heat treatment of FIG. A similar effect can be obtained by depositing a conductive film, for example, a TiN film, which will be the lower electrode, at a temperature of 400 ° C. or higher.

  The semiconductor device and the manufacturing method thereof according to the present invention have an effect of increasing the surface area of the charge storage capacitor portion with high accuracy, and are useful as a method for manufacturing the charge storage capacitor portion of a memory element such as a DRAM.

FIG. 5D is a process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment of the invention. FIG. 2 is a process cross-sectional view subsequent to FIG. 1. 1 is an apparatus schematic diagram of a plasma processing apparatus used in a first embodiment of the present invention. It is process sectional drawing explaining the process converted into an oxide layer with the nitrogen radical by the 1st Embodiment of this invention. It is a Fourier-transform infrared absorption spectrum figure. It is explanatory drawing which shows the relationship between the process parameter at the time of a plasma process, and an oxide layer film thickness. It is process sectional drawing explaining the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. FIG. 8 is a process sectional view subsequent to FIG. 7; It is a graph which shows the relationship between the film shrinkage rate of the MSQ film | membrane and heat processing temperature for demonstrating the 2nd Embodiment of this invention. It is process sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 PTEOS film 12 BPSG film 13 Laminated film 14 Opening part 15 Uneven part 16 Doped silicon film 17 Ta ₂ O ₅ film 18 TiN film 100, 500 Semiconductor substrate 101, 501 Silicon oxide film 102, 502 Plug 103, 503 Silicon nitride film 104a, 504a PTEOS film 104b, 504b MSQ film 104, 504 Laminated film 105, 505 Resist pattern 106, 506 Opening 107 Oxygen radical 108, 302 Oxide layer 109, 507 Uneven portion 110, 508 Uneven portion on the side of the opening laminated films 111,509 TiN film 112,510 T ₂ O ₅ film 113,511 TiN film 114,512 resist pattern 201 the process chamber 202 gas introduction port 203 plasma generation chamber 204 high frequency power source 205 sample stage 301 Chissora having Cal

Claims (8)

A semiconductor device in which a capacitor cell is formed in a region including an opening formed on a semiconductor substrate, wherein a silicon oxide film and SiC _w H _x O _y N _z (w> 0, x ≧ 0) are formed on the semiconductor substrate. , Y> 0, z ≧ 0), and the opening is formed in the laminated film alternately deposited with the organic-inorganic hybrid film, and the side surface of the opening recedes the portion of the organic-inorganic hybrid film. A semiconductor device having an uneven shape. A laminated film is formed by alternately depositing a silicon oxide film and an organic-inorganic hybrid film represented by SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) on a semiconductor substrate. A step of forming an opening in the laminated film, a step of converting a predetermined portion of the organic-inorganic hybrid film exposed on the side surface of the laminated film into an oxide layer, and the oxide layer selectively. And a step of forming irregularities on the side surface of the opening of the multilayer film and a step of forming capacitor cells on the multilayer film having the irregularities.   The step of converting a predetermined portion of the organic-inorganic hybrid film exposed on the opening side surface of the laminated film into an oxide layer is performed by irradiating the organic-inorganic hybrid film exposed on the opening side surface of the laminated film with the radical species. The method of manufacturing a semiconductor device according to claim 2 to be performed.   The method of manufacturing a semiconductor device according to claim 3, wherein the radical species includes an oxygen radical or a nitrogen radical.   3. The method for manufacturing a semiconductor device according to claim 2, wherein the step of selectively removing the oxide layer is performed using a chemical solution containing fluorine.   3. The method for manufacturing a semiconductor device according to claim 2, wherein the step of selectively removing the oxide layer is performed using a gas containing fluorine. A laminated film in which a silicon oxide film and an organic-inorganic hybrid film represented by SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) are alternately deposited on a semiconductor substrate Forming an opening in the laminated film, and retracting a predetermined portion of the organic-inorganic hybrid film exposed on the side surface of the laminated film by contraction, thereby opening the laminated film A method of manufacturing a semiconductor device, comprising: forming irregularities on a side surface; and forming a capacitor cell on a laminated film having the irregularities.   The step of retracting a predetermined portion of the organic-inorganic hybrid film exposed on the side surface of the opening of the laminated film by film contraction in the horizontal direction gives thermal energy to the organic-inorganic hybrid film exposed on the side of the opening of the laminated film. 8. A method of manufacturing a semiconductor device according to claim 7, wherein the manufacturing method is performed.

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