JP2007193829A - Logic circuit delay optimization system, logic circuit delay optimization method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new method to optimize circuit delay in a logic circuit. <P>SOLUTION: The logic circuit is constituted by connecting a plurality of circuit blocks. On the basis of the delay ratio of the circuit block showing the ratio in which a load capacity value given to the circuit block delays a signal propagating through the circuit block, the drive potential value of a prior stage circuit block which is the prior stage of a target circuit block and the load capacity value given to the target circuit block; a drive potential value calculation means 11 calculates the drive potential value to be required to the target circuit block. On the basis of the drive potential value obtained by the drive potential value calculation means 11, a change means 12 changes designation of the above element used by the target circuit block. This configuration enables, from a characteristic value regarding the circuit blocks connected as the prior and posterior stages of the target circuit block, to select the optimum element to be used in the target circuit block. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for optimizing a logic circuit, and more particularly to a technique for optimizing a delay generated in a signal propagating in a logic circuit in an initial stage of logic circuit design.

Conventionally, as a technique for causing a computer to optimize a circuit delay of a logic circuit, that is, to optimize a delay generated in a signal propagating in the logic circuit, for example, as disclosed in Patent Document 1 and Patent Document 2 Many proposals have been made to extract a critical path in a logic circuit and perform delay optimization on the extracted critical path.
JP-A-5-151310 JP-A-11-120222

The extraction of the critical path performed by the above-described conventional technique requires a large amount of processing, and thus it is necessary to operate a computer having a high processing capacity for a long time.
Also, in the conventional delay optimization processing to be performed by a computer, when a critical path is optimized, if there are multiple fanouts in the subsequent stage of the circuit block on the path, the critical The optimization process is performed only on the path, and the relationship between the plurality of driven blocks constituting the fan-out is not considered. For this reason, for example, the driving ability (the ability required for the driven block for driving the driven block) of those driven blocks on the critical path is enlarged, and the driving ability is reduced. In order to ensure, the mounting circuit area of the driven block may become excessively large.

  In the conventional processing, the external input / output terminal to which the logic circuit to be designed is connected to another circuit is regarded as a general buffer element connected to the external input / output terminal of the other circuit. We were optimizing. Furthermore, the driving capability of the input pins connected to the external input / output terminals in the logic circuit is fixed to a predefined one. To change the driving capability, use the circuit itself including the input pins. It was only allowed to stop and select another circuit instead.

  In the conventional processing, the load capacity of the net (wiring connecting circuit blocks) does not reflect the information obtained by the mounting design performed after the delay optimization processing, and is not taken into consideration in the optimization. Or it was to reflect the estimated value. Therefore, even if the circuit delay of the logic circuit is optimized, the circuit delay after the packaging design may not be improved.

  Further, in the conventional processing, for example, in order to set a block that does not perform optimization because the user does not want to perform delay optimization, the instruction is given for each element or each path. There was a need.

  In addition, in the conventional processing, when delay optimization is executed, the target circuit itself is automatically converted and output. In order to know the contents of element replacement by optimization, the logic before and after the execution is executed. I had to compare the circuits.

  In view of the above problems, it is an object of the present invention to provide a new method for optimizing the circuit delay of a logic circuit.

FIG. 1 is a diagram showing a principle configuration of the present invention.
In the present invention, for a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used for constituting the circuit block designated for each circuit block is the same as the element. A logic circuit delay optimization system or logic circuit delay optimization that optimizes the delay of a signal propagating in the logic circuit by changing to another primitive element having the function of and having a different driving capability value The method is assumed.

  Here, “primitive element” means a basic element in a logic circuit, specifically, various gates such as an inverter, a buffer, AND, OR, NAND, NOR, It is a general term for basic logic elements such as various flip-flops such as RS, JK, and D. In addition, the “drive capability value” is the high capability that can be driven when a signal is input to the element, that is, the inversion of the logic indicated by the output signal of the element is connected to the output of the element It is a value indicating the level of capability that can be performed against the load being applied.

First, the first configuration shown in FIG. This shows the first principle configuration of the logic circuit delay optimization system according to the present invention.
The drive capability value calculation means 11 includes a delay rate of the circuit block indicating a rate at which a load capacitance value given to the circuit block delays a signal propagating in the circuit block, and the target circuit block that is the target of the designation change. The driving capability value of the preceding circuit block determined by the element specified for the preceding circuit block connected to the target circuit block as the previous stage, and another circuit block connected to the subsequent stage of the target circuit block Based on the load capacity value given to the target circuit block, the drive capability value required for the target circuit block is calculated.

The changing unit 12 changes the designation of the element used in the target circuit block based on the driving capability value obtained by the driving capability value calculating unit 11.
According to this first configuration, it becomes possible to select an element optimal for use in the target circuit block from the characteristic values relating to the circuit block connected as the preceding and following stages of the target circuit block. Therefore, by selecting the optimum elements for all circuit blocks in the logic circuit, the delay optimization for the logic circuit can be performed without extracting the critical path. Therefore, the amount of processing required for the delay optimization Is reduced.

  In the first configuration described above, the changing unit 12 may make the change so as to select the element that requires the same mounting circuit area as that selected before the change.

According to this configuration, it is possible to prevent an increase in the mounting area of the logic circuit due to delay optimization.
In the first configuration described above, a signal input to the logic circuit or a signal output from a circuit block that is a flip-flop in the logic circuit passes through the circuit block for the target circuit block. A delay amount calculating means for calculating a delay amount that can occur until output as a delay amount to the preceding circuit block, and the target circuit block among a plurality of input pins for inputting a signal to the target circuit block A representative pin determining unit that uses the input pin connected to the circuit block having the maximum delay amount up to the preceding circuit block as a representative pin of the circuit block to be designated, And the drive capability value calculating means 11 is connected to the representative pin in the preceding circuit block for the target circuit block. It may perform the calculated unloading based on the driving ability value for the block.

According to this configuration, according to the present invention, it is possible to appropriately perform delay optimization of a circuit block having a plurality of inputs.
The first configuration described above further includes an external element driving capability value input means for inputting a driving capability value of an element connected to the external input terminal of the logic circuit, and the driving capability value calculation means 11 includes: When calculating the driving capability value required for the target circuit block connected to the external input terminal, the driving capability value input to the external element driving capability value input means is the driving capability value of the preceding circuit block. You may make it carry out.

According to this configuration, it is possible to accurately reflect the driving capability of the element connected to the external input terminal that is actually assumed by optimizing the delay of the logic circuit.
In the first configuration described above, the driving circuit further includes a preceding circuit block driving ability value input means for inputting the driving ability value of the preceding circuit block, and the driving ability value calculating means 11 includes the preceding circuit block driving ability value. The driving capability value input to the input means may be regarded as the driving capability value of the preceding circuit block, and the driving capability value required for the target circuit block may be calculated.

  According to this configuration, even if a design change is expected for the circuit configuration up to the preceding circuit block, if the provisional driving capability value of the preceding circuit block is input, the optimization of the succeeding circuit block precedes. Can be done.

  The first configuration described above further includes external element load capacitance value input means for inputting a load capacitance value applied to the logic circuit by an element connected to the external output terminal of the logic circuit, and has a driving capability. The value calculation means 11 calculates the drive capacity value required for the target circuit block connected to the external output terminal, and the load capacitance value input to the external element load capacitance value input means is input to the target circuit block. Alternatively, the load capacity value may be regarded as being given.

According to this configuration, it is possible to accurately reflect the load capacitance due to the element connected to the external output terminal that is actually assumed by optimizing the delay of the logic circuit.
Further, in the first configuration described above, the circuit further includes wiring capacity acquisition means for acquiring wiring capacity generated by wiring between the circuit blocks obtained by performing the mounting design of the logic circuit, and driving capacity value calculation means 11 may calculate the drive capacity value required for the target circuit block by adding the wiring capacity acquired by the wiring capacity acquisition means to the load capacity value.

According to this configuration, it is possible to reflect the wiring capacity that is more accurately obtained by mounting design in the delay optimization of the logic circuit.
Further, in the first configuration described above, there is further provided non-optimization attribute assigning means for assigning an attribute indicating that the designation is not changed to the circuit block, and the change means 12 includes the non-optimization attribute. The designation may not be changed for the target circuit block to which the attribute is assigned by the assigning unit.

  According to this configuration, since the circuit block that the user does not want to change can be excluded from the target of the circuit block that performs the specified change, the processing amount required for the delay optimization process is reduced, and Reduction in rework (repetitive work) in circuit design work can be expected.

  Further, the first configuration described above may further include a change content output unit that outputs the content of the change in the target circuit block in which the designated change has been made by the change unit 12.

  According to this configuration, the result of delay optimization can be reflected in the processing in another system such as a mounting design system, and the design efficiency can be improved. In addition, by outputting the result to a file, it becomes possible to clearly notify the user of the contents of the change, so that improvement in work efficiency in later work such as mounting design can be expected.

Next, the second configuration shown in FIG. This shows the second principle configuration of the logic circuit delay optimization system according to the present invention.
The slack value calculation means 21 calculates the slack value of the circuit block. The slack value of a circuit block is the difference between the maximum delay that can occur up to that circuit block and the arrival time allowed for that circuit block (allowable arrival time). It is shown.

  The drive capability value distribution means 22 is designated as the subsequent circuit block when one output of the circuit block in the logic circuit is connected to the subsequent circuit block which is a plurality of circuit blocks subsequent to the circuit block. The driving ability value for each subsequent circuit block before the designation change determined by the element that has been subjected to the calculation is calculated for each subsequent circuit block while maintaining the total driving ability value for each subsequent circuit block. Based on the difference in slack value, distribution is made to each of the subsequent circuit blocks. Note that “when one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block” means that the latter circuit block is in the logic circuit. It shows that a plurality of fan-outs are configured for one output of the circuit block.

  The post-stage circuit block drive capability value calculation unit 23 regards the drive capability value distributed by the drive capability value distribution unit 22 as the drive capability value of the circuit block preceding the post-stage circuit block and requests the post-stage circuit block. Calculate the value.

The post-stage circuit block changing means 24 changes the designation of the element used in the post-stage circuit block based on the driving ability value obtained by the calculation.
According to this second configuration, the driving capability value distribution means 22 distributes a larger amount of driving capability to the subsequent circuit block with a small timing margin based on the slack value of each circuit block, and the timing margin is large. By distributing the drive capability value to the subsequent circuit block in a small amount, optimization that gives priority to a signal path having a large signal delay amount is possible, and delay optimization with a good balance of drive capability becomes possible.

  In the second configuration described above, the circuit further has wiring capacity acquisition means for acquiring wiring capacity generated by wiring between the circuit blocks obtained by designing the mounting of the logic circuit. The value calculation unit 23 may be configured to perform the calculation in consideration of the wiring capacity acquired by the wiring capacity acquisition unit.

According to this configuration, it is possible to reflect the wiring capacity that is more accurately obtained by mounting design in the delay optimization of the logic circuit.
Next, the third configuration shown in FIG. This shows the third principle configuration of the logic circuit delay optimization system according to the present invention.

The slack value calculation means 31 calculates the slack value of the circuit block.
The drive capability ratio calculation means 32 is designated as the subsequent circuit block when one output of the circuit block in the logic circuit is connected to the subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block. The sum of the driving ability values for each subsequent circuit block before the change of designation determined by the element that has been changed, and the slack value of the subsequent circuit block that is shown to have the least timing margin The ratio of the driving ability values before the designation change is calculated.

  Based on the ratio of the driving ability values calculated by the driving ability ratio calculating means 32, the first driving ability value calculating means 33 is the latter circuit block and the slack value indicates that the timing margin is the smallest. A drive capability value required for the subsequent circuit block is calculated.

  The first rear-stage circuit block changing unit 34 is the rear-stage circuit block based on the driving ability value obtained by the calculation, and the rear-stage circuit block indicated by the slack value has the least timing margin. The designation is changed.

  According to the third configuration, the designation of the element for the subsequent circuit block is shown that the slack value has the least timing margin when the subsequent circuit block configures a plurality of fan-outs. At this time, since the characteristic values of the other subsequent circuit blocks that are driven simultaneously with the subsequent circuit blocks are taken into consideration, the elements can be selected appropriately.

  In the third configuration described above, the driving capacity value before the change of designation and the change of the first latter circuit block for the latter circuit block whose slack value indicates the least timing margin. Change rate calculation means for calculating the change rate of these drive capacity values from the drive capacity value of the element specified after the change by the means, and the subsequent circuit block having the least timing margin depending on the slack value Is calculated by the second driving capability value calculating means for calculating the driving capability value required for the subsequent circuit block other than those indicated by the second driving capability value calculating means based on the rate of change. Based on the driving capacity value, the latter stage circuit block whose slack value indicates the least timing margin is excluded. And Second subsequent circuit block changing means for performing the specified changes in the subsequent circuit blocks may be configured to further have a.

  According to this configuration, when the subsequent circuit block configures a plurality of fan-outs, the designation of the element is changed in consideration of the characteristic values of the other subsequent circuit blocks that are driven simultaneously. Excessive increase in the amount is suppressed.

  Further, in the third configuration described above, the circuit further includes wiring capacity acquisition means for acquiring wiring capacity generated by wiring between the circuit blocks obtained by performing the mounting design of the logic circuit, and the first driving capability value The calculation means 33 has acquired the calculation of the drive capacity value required for the subsequent circuit block, which is indicated by the slack value and has the least timing margin, by the wiring capacity acquisition means. You may make it carry out in consideration of wiring capacity.

According to this configuration, it is possible to reflect the wiring capacity that is more accurately obtained by mounting design in the delay optimization of the logic circuit.
It is also possible to create a program for causing a computer to perform the same functions as those realized by the elements constituting the logic circuit delay optimization system according to the present invention described above, and to cause the computer to execute the program. The above-described problems can be solved.

  With any of the configurations of the present invention, the circuit delay of the logic circuit can be optimized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 2 is a diagram showing the configuration of a logic circuit delay optimization device for implementing the present invention. In the figure, a CPU 101, a ROM 102, a RAM 103, an I / F unit 104, an input unit 105, a display unit 106, an output unit 107, and a storage unit 108 are all connected to a bus 109 and can exchange data with each other. .

A CPU (Central Processing Unit) 101 is a central processing unit that controls the operation of the entire logic circuit delay optimizing device (hereinafter referred to as “this device”).
A ROM (Read Only Memory) 102 is a memory in which a control program executed by the CPU 101 is stored in advance, and the operation of the entire apparatus is controlled by the CPU 101 executing this control program.

  A RAM (Random Access Memory) 103 is a memory that is used as necessary as a temporary storage area for various data and as a work memory when the CPU 101 executes a control program stored in the ROM 102.

An I / F (Interface) unit 104 controls transmission / reception of various data to / from other devices via a communication network.
The input unit 105 receives an input from the outside and passes the input to the CPU 101. For example, an input device that receives an instruction from the user of the apparatus, such as a keyboard or a mouse, or an FD (Floppy (registered trademark) Disk), A portable recording medium reading device such as a CD-ROM (Compact Disc-ROM), DVD-ROM (Digital Versatile Disc-ROM), or MO (Magneto-Optics) disc is provided.

  The display unit 106 performs display in accordance with an instruction from the CPU 101, and is a display device including, for example, a CRT (Cathode Ray Tube) or an LCD (Liquid Crystal Display).

  The output unit 107 performs display in accordance with an instruction from the CPU 101, and includes a printer device or a writing device for a portable recording medium such as the above-described FD or MO disk. Of course, a device having both a writing function and a reading function for a portable recording medium can be used as a device shared by the input unit 105 and the output unit 107.

  The storage unit 108 includes various programs including a part program to be evaluated by the apparatus, expected accuracy information indicating measurement accuracy expected for the part program to be evaluated, and stage accuracy information to be described later. Various types of data are stored, and for example, a hard disk device is provided. Instead of executing the control program stored in the ROM 102, the CPU 101 reads out the control program stored in advance in the storage unit 17, temporarily stores it in the RAM 103, and then reads out the control program from the RAM 103. It is also possible to control the overall operation of the present apparatus.

This apparatus is configured to include the above-described components.
Since the configuration of the present apparatus shown in FIG. 2 is possessed by many standard computers, the present invention can also be implemented by such a computer.

  Next, control processing performed by the CPU 101 shown in FIG. 2 will be described. Each process described below is realized by the CPU 101 executing a control program for controlling the apparatus.

First, FIG. 3 will be described. FIG. 3 is a flowchart showing the processing contents of the circuit delay optimization processing performed by the CPU 101.
First, in S101, a library of circuit blocks stored in advance in the storage unit 108 is referred to, and element areas, element attributes, identical logical element groups, elements defined as elements that can be used for each circuit block. Each value of the input pin drive capability, parasitic capacitance, and delay rate is read out and stored in a predetermined area of the RAM 103.

  In subsequent S 102, circuit network information indicating the logic circuit that is the target of the delay optimization processing is input to the input unit 105, for example, in the form of net information, and is acquired and stored in a predetermined area of the RAM 103.

  In S103, in the logic circuit, a circuit block in which the input pin of the circuit block is directly connected to the external input terminal and a circuit block that is a flip-flop (hereinafter, the circuit block is also simply referred to as “block”) , The number of stages in each block is detected.

  In S104, the maximum delay from the external input terminal or the clock pin of the flip-flop to each block is calculated in the logic circuit based on the number of stages detected in the previous step.

  In S105, an allowable arrival time from each block in the logic circuit to the external output terminal or flip-flop input pin in the logic circuit is calculated, and the obtained allowable arrival time and the maximum path delay to each block are calculated. The difference is calculated to obtain the slack value.

  Thereafter, in S106, it is determined whether or not optimization has been performed for all blocks existing in the logic circuit. Here, a block to which an element having a non-optimization attribute is assigned is determined as having been optimized. When the result of this determination process is Yes, that is, when it is determined that all blocks have been optimized, this circuit delay optimization process ends.

  On the other hand, if the result of the determination process in S106 is No, that is, it is determined that there is still an unoptimized block, the process proceeds to S107, and the block with the smaller number of stages is selected. Block optimization processing is performed.

Hereinafter, this block optimization process will be described.
FIG. 4 is a flowchart showing the processing contents of the first example of the block optimization processing.
In FIG. 4, in S111, a block (this block is hereinafter referred to as a “driver block”) preceding the block that is the object of the optimization process (this block is hereinafter referred to as a “block to be optimized”). And the drive capability of the device defined in the above-described library are collated to obtain the drive capability of the preceding block. Here, in the optimized block, if the input pin is connected to the external input terminal, the previous stage of the optimized block does not exist in the logic circuit. The processing proceeds as if it is driven by an inverter.

  In S112, for all the subsequent blocks that are to be driven by the optimized block, the elements that are currently designated for use in each block and the drive capability of the elements defined in the library described above are used. Are compared to detect the driving ability of each subsequent block, and the sum of those driving ability is calculated. This total value can be regarded as the load capacity for the optimized block. Here, among the blocks to be optimized, those whose output pins are directly connected to the external output terminals are standard unless otherwise specified because there is no block driven by the block to be optimized. The processing proceeds as if one inverter used in the above is driven.

  In S113, for the driver block and the optimization target block, each element currently designated to be used for each block, and the delay rate and parasitic capacitance of each element defined in the above-described library are obtained. By comparing, the delay rate and parasitic capacitance of each block are obtained.

  In S114, the optimum drive capability of the optimized block that minimizes the delay from the driver block to the optimized block is determined based on the drive capability, load capacity, and delay rate of each block acquired as described above. Desired.

  In S115, based on the optimum drive capability obtained in the previous step, among the elements belonging to the same logical element group as the element currently designated for use in the optimized block, the optimum drive capability of the optimized block is determined. The one with the optimum driving capability to satisfy is selected, and the designation for the block to be optimized is replaced to use the element. After this process is completed, the process returns to FIG.

A specific example in which the logic circuit is optimized by the CPU 101 performing the processes shown in FIGS.
FIG. 5 shows an example of a library in which element information is defined.

Here, the terms used in FIG. 5 will be described.
The parasitic capacitance of the input pin is a capacitance that is steadily provided in the element as viewed from the input pin of the element.

  The drive capability of the input pin is a capacitance connected to the output pin, and is the maximum value of the capacitance that can be driven when a signal is input to the input pin (the logic of the output signal can be inverted). Yes, this indicates the high ability to perform a transient operation of logic inversion.

The delay rate of an input pin refers to the delay of the input pin relative to the delay that occurs when the element is driven (the logic of the output signal is inverted) in the signal propagation from the input pin to the output pin of the element. It shows how much the driving capacity and the load capacity of the output pin affect the delay time.

Delay rate = (delay caused by unit load capacity) x (drive capacity) ÷
(Time for one cycle of the reference clock in the logic circuit to be optimized)

Is required. The load capacitance is a capacitance that can be applied to the output pin as a load when performing a transient operation (inverting the logic of the signal) that drives all the subsequent elements connected to the output pin.

The average delay rate, average drive capability, and average parasitic capacitance of an element are the average values of the delay rate, drive capability, and parasitic capacitance of each input pin of the element.
Referring to FIG. 5, an element whose element name is “AAA” is a 2-input NAND, and belongs to an element group “2NAND” group. Further, the optimization for this element is “possible”, and it does not have a non-optimization attribute. And mounting this element requires 50 areas, and the average delay rate is 1.3. This element has input pins A and B and an output pin X, and the input pin A is defined as a delay rate of 1.2, a driving capability of 33.5, and a parasitic capacitance of 9.0. For the input pin B, the delay rate is defined as 1.4, the driving capability is 32.0, and the parasitic capacitance is 10.5.

In the process of S101 in FIG. 3 described above, the library as shown in FIG. 5 is read.
Next, FIG. 6 will be described. This figure shows an example of a circuit network to which delay optimization processing is applied. In the circuit network shown in the figure, blocks F and I are flip-flops. In the process of S102 of FIG. 3 described above, information indicating the circuit network of FIG. 6 is acquired.

In the following description, the circuit network shown in FIG. 6 is referred to as “circuit network A”.
FIG. 7 is a diagram showing the result of the numbering performed on each block of the network A by executing the process of S103 of FIG. In the figure, the number given to each block indicates the number of stages of the block.

  In FIG. 7, for example, there are two blocks A and C before the block D. Of these two blocks, the number of stages of the block C having a large number of stages is 2, so that the number of stages of the block D is 3 stages obtained by adding one stage to the two stages of the block C. Similarly, for the other blocks E, H, and K, the number of stages obtained by adding one stage to the maximum number of stages of the preceding block is set as the number of stages of the block.

  FIG. 8 is an example of the result of delay calculation performed on each block of the network A by executing the process of S104 of FIG. In the figure, the number given to each block indicates the block delay from the input pin to the output pin of that block. The delay of each block is calculated by the following equation.

In the above equation, the load capacity is the sum of the drive capacities of all the subsequent blocks connected to the output pin of the own block.
When calculating the above formula, the average delay rate, average drive capability, and average parasitic capacitance of each block are used as the delay rate, drive capability, and parasitic capacitance. Also, the load capacitance is the average of all blocks in the subsequent stage. Use the sum of the driving capabilities.

  FIG. 9 is an example of the calculation result of the maximum delay performed on each block of the network A following the delay calculation shown in FIG. 8 by executing the process of S104 of FIG. In the figure, the number given to each block indicates the maximum delay that can occur until the output pin of that block.

  In FIG. 9, for example, in the block D, a value 35 obtained by adding the delay 5 of the block D itself to the maximum delay 30 of the block A having a large maximum delay up to the previous block A and block C. Is the maximum delay until block D. Note that the number of block stages is not considered here. Similarly, for the other blocks E, H, and K, a value obtained by adding the own delay to the maximum delay of the preceding block is set as the maximum delay until that block.

  FIG. 10 shows that each block is executed by executing the process of S105 of FIG. 3 described above, assuming that the allowable time until the block connected to the external output terminal or the input pin of the flip-flop in the network A is 80. It is an example of the calculation result of the allowable arrival time performed. In the figure, the numbers in parentheses attached to each block indicate the element delay of each block shown in FIG. 7, and the numbers without parentheses shown below the numbers indicate the allowable arrival time. , Respectively.

  In FIG. 10, for example, in the block J, the output pin is connected to the block K together with the external output terminal. Here, for block K, its allowable arrival time is 80 and its element delay is 10, so the difference is 70, and this value is the allowable arrival time of the path from block J to block K. Here, the allowable arrival time at the external output terminal of the path connected from the block J to the external output terminal is originally 80, but the limit of the allowable arrival time of the path to the block K is smaller, so the block J The allowable arrival time is 70. The same applies to the other blocks.

  FIG. 11 is an example of the calculation result of the slack value performed on each block of the circuit network A by executing the process of S105 of FIG. In the figure, the numbers given to each block indicate the slack value of that block.

  The slack value of a block is the difference between the maximum delay that can occur up to that block and the arrival time allowed for that block (allowable arrival time), and indicates the margin of timing in that block. In the present embodiment, a value obtained by subtracting the allowable arrival time for the block from the maximum delay for the block is defined as the slack value. Therefore, the positive sign of the slack value indicates that the degree of violation of the allowable arrival time is severe. On the other hand, the negative sign of the slack value is negative and the sign of the slack value is negative. The larger the absolute value), the larger the margin for the allowable arrival time.

  In FIG. 11, for example, in block J, the maximum delay is 15 from FIG. 9, and the allowable arrival time is 70 from FIG. 10. Therefore, −55 which is the difference is the slack value of this block.

Next, the block optimization process shown in FIG. 4 performed in S107 of FIG. 3 will be described.
The calculation of the optimum drive capability of the block to be optimized performed in S114 of FIG. 4 is performed as follows.

  The sum D of the delay generated in the driver block and the delay generated in the optimized block is obtained from the above-described [Equation 1]:

となる。なお、上式において、
ドライバブロックの遅延＋被最適化ブロックの遅延：Ｄ
ドライバブロックの駆動能力：Ｃ１
ドライバブロックの遅延率：Ｇ１
ドライバブロックの寄生容量：Ｐ１
被最適化ブロックの駆動能力（＝ドライバブロックの負荷容量）：ｃ２
被最適化ブロックの遅延率：Ｇ２
被最適化ブロックの寄生容量：Ｐ２
被最適化ブロックの負荷容量：Ｃ３
クロック単位時間：τ
である。

It becomes. In the above formula,
Driver block delay + optimized block delay: D
Driver block drive capacity: C1
Driver block delay rate: G1
Parasitic capacitance of driver block: P1
Drive capacity of the block to be optimized (= load capacity of the driver block): c2
Delay rate of optimized block: G2
Parasitic capacitance of optimized block: P2
Load capacity of optimized block: C3
Clock unit time: τ
It is.

  If the value obtained by differentiating the equation [2] by c2 is 0, the delay of this portion is minimized. Therefore, such a value of c2 is the optimum driving capability. That is,

となり、このｃ２を最適駆動能力とする。
次に、図４のＳ１１５で行なわれる、前述したようにして求められた最適駆動能力に基づく素子の選択の一例を説明する。

Thus, this c2 is set as the optimum driving capability.
Next, an example of element selection based on the optimum driving ability obtained as described above performed in S115 of FIG. 4 will be described.

  Here, it is assumed that the logical element group name to which the element of the block to be optimized belongs is “INVERTER”, and the element name included in this group and its driving capability are defined in the library as shown in the table below. To do.

  Here, for example, when the optimum drive capability of the optimized block obtained by the process of S114 of FIG. 4 described above is 14.0, the drive closest to the value is calculated from the above [Table 1]. “INV2” having capability 13.0 is selected. As a result, the selected element is replaced as the optimum element of the block to be optimized by the process of S115.

  Next, FIG. 12 will be described. This figure is a flowchart showing the processing contents of the second example of the block optimization processing. The second process is to suppress an excessive increase in the mounting area due to the optimization by adding a limit to the mounting area of the element.

  In FIG. 12, steps showing the same processing contents as those in FIG. 4 are denoted by the same reference numerals. As can be seen by comparing FIG. 12 with the flowchart showing the processing contents of the first example of the block optimization processing shown in FIG. 4, this second example is between the processing of S114 and S115 of FIG. The processing from S121 to S123 is added.

  In FIG. 12, in S121 following S115, it is checked whether or not an instruction not to change the circuit area is given to the optimized block in the circuit network information acquired in the processing of S102 of FIG. .

  If the determination result in S121 is Yes, that is, if the above-described instruction is made, in S122, the element for the element that is currently designated for use in the optimized block defined in the library described above. In step S123, an element belonging to the same logical element group as the element that is currently designated for use in the optimized block is an element having the same area as the element area of the optimized block. Then, the process proceeds to S115. In S115, the used elements are replaced such that the element selected as the selection candidate is designated as the element to be used in the optimized block.

On the other hand, if the determination result in S121 is No, that is, if the above-described instruction is not made, the process immediately proceeds to S115, and the same process as in FIG. 4 is performed.
A specific example in which the logic circuit is optimized by performing the processing shown in FIG.

  The logical element group name to which the element of the optimized block belongs is “INVERTER”, and the element name included in this group and its drive capability and element area are defined in the library as shown in the table below. And

  When the element currently designated for use in the optimized block is “INV4”, the element area is 30 according to the above table. In addition, in the “INVERTER” group, those with an element area of 30 are “INV3” and “INV4” according to the above table, so if there is an instruction not to change the circuit area, these two are It becomes a selection candidate for element replacement.

  Here, when the optimum drive capability of the block to be optimized obtained by calculation is 14.0, “INV3” close to the drive capability is selected and replaced as the optimum element of the block to be optimized. . As a result, the circuit area of the block to be optimized is maintained even if optimization is performed, and an excessive increase in the mounting area is suppressed.

  Next, FIG. 13 will be described. This figure is a flowchart showing the processing contents of the representative pin selection processing. This process is a process for performing optimization when the block to be optimized has a plurality of input pins. Instead of the conventional technique for performing input pins on the critical path, the block to be optimized is used. The drive capability is optimized for the input pin to which the block having the largest delay amount is connected.

The process of FIG. 13 is executed in the process of S111 in the block optimization process of FIG. 4 or 12 described above.
First, in S131, it is determined whether or not the optimization target block is a multi-signal input block, that is, a block having a plurality of input pins. Only when this determination result is Yes, in S132, the value of the maximum delay for each block in the previous stage to which each input pin is connected is acquired.

  In subsequent S133, the input pin connected to the block having the largest value among these values is selected as the representative pin of the optimized block. If the determination result in S131 is No, that is, if the optimized block has only one input pin, that pin is used as a representative pin.

A specific example in which the representative pin of the block to be optimized is selected by the CPU 101 performing the above representative pin selection processing.
In FIG. 9 described above, attention is focused on, for example, the block D as the optimized block.

  Block D has a and b input pins. The preceding blocks connected to these two input pins are the block A and the block C. FIG. 9 shows that the maximum delay values up to these blocks are 30 and 25, respectively, and the value of block A is larger. Therefore, in block D, pin a connected to block A is the representative pin.

Next, consider the case where, for example, block C is an optimized block. Since the only input pin of block C is a, this pin a becomes the representative pin of block C.
Next, FIG. 14 will be described. This figure is a flowchart showing the processing contents of the driving ability distribution processing. In this process, a plurality of blocks are connected in the subsequent stage, that is, after optimizing the optimized block having a plurality of fan-outs, the difference in driving ability specified for each block in the subsequent stage is determined. By leveling on the basis of the slack value (timing margin), it is possible to suppress an excessive expectation of the driving capability required in the optimization performed later for each of these blocks.

The process of FIG. 14 is executed immediately after the block optimization process of S107 in the circuit delay optimization process of FIG.
In FIG. 14, in S141, all the blocks subsequent to the block to be optimized whose input pins connected to the output pins of the block to be optimized are the representative pins of the block are detected. In the following description, the subsequent block detected by this processing is referred to as a “branch block”.

  In subsequent S142, it is determined whether or not a plurality of branch blocks are detected. If the determination result is Yes, the process proceeds to S143. On the other hand, if the determination result is No, the drive capacity distribution process is terminated as it is without distributing the drive capacity of the branch block.

In S143, the drive capability of the representative pins of each branch block is acquired from the definition in the library described above, and the total value thereof is calculated.
In S144, the slack value for each branch block that has already been calculated by the process of S105 of FIG. 3 described above is acquired, and the average value (slack average value) of the slack values acquired in subsequent S145 is calculated.

  In S146, based on the difference between the calculated slack average value and the slack value of each branch block, a driving capability that maintains the driving capability of the entire branch block is calculated for each branch block and distributed to each branch block. Is done.

  The drive capability obtained by the above drive capability distribution process is set as the drive capability before optimization for each branch block, and the optimization processing for these branch blocks is performed later.

A specific example will be shown in which drive capability distribution processing is performed by the CPU 101 to distribute drive capability to branch blocks.
FIG. 15 shows an example of a circuit network to which the driving capability distribution process is performed. In the figure, among the input pins a and b of each block, those marked with black circles indicate that they are representative pins of that block.

In the following description, the circuit network shown in FIG. 15 is referred to as “circuit network B”.
In the network B, when the block A is selected as the block to be optimized, the output pin x of the block A is connected to the input pin a in all of the block C, the block D, and the block E. Here, FIG. 15 shows that the input pins a of the block C, the block D, and the block E are all representative pins. Therefore, the branch blocks for the optimized block A are the block C, the block D, and the block E.

  Further, in the network B, when the block B is selected as the optimized block, the output pin x of the block A is connected to the input pin b and the input pin a of the block F in both the block D and the block E. It is connected. Here, FIG. 15 shows that the input pins b of the block D and the block E are not representative pins, and the input pin a of the block F is a representative pin. Therefore, the branch block for the optimized block B is only the block F.

  The description of the branch blocks C, D, and E for the optimized block A will be continued. Assume that the element names, representative pin drive capacities, and slack values of these branch blocks are as shown in the following table.

  In the above table, the total value of the drive capability of these branch blocks is 48.0, and the slack average value is −40.0.

  Here, for the branch block whose slack value is equal to or greater than the average value, that is, with a small timing margin, the drive capability is calculated as follows.

上式において、
駆動能力計算値：Ｃ’
そのブランチブロックについて現在指定されている駆動能力：Ｃ
そのブランチブロックのスラック値：Ｓ
ブランチブロック全体のスラック平均値：Ｓａｖ
補正係数：ｋ
例えば補正係数ｋを０．０１とすると、［表３］において、スラック値が平均値以上、すなわちタイミングの余裕の少ないブランチブロックであるブロックＣについてはＣ’＝１５．６となり、ブロックＣに対して現在指定されているものよりも高めに駆動能力が分配される。なお、補正係数ｋは経験や実験での実測結果等に基づいて適切に設定される。

In the above formula,
Driving capacity calculation value: C '
Currently specified drive capacity for the branch block: C
The slack value of the branch block: S
Slack average value of the entire branch block: Sav
Correction factor: k
For example, when the correction coefficient k is 0.01, in [Table 3], C ′ = 15.6 for the block C, which is a branch block with a slack value equal to or greater than the average value, that is, with little timing margin. Drive capacity is distributed higher than what is currently specified. The correction coefficient k is appropriately set based on experience, actual measurement results, and the like.

Next, for the branch block having a slack value smaller than the average value, that is, having a large timing margin, the drive capability is calculated as follows.
First, the following equation is calculated using the drive capability calculation value C ′ for the branch block whose slack value is smaller than the average value.

上式において、Ｃｄｉｆｆは駆動能力差分の和である。
［表３］においては、Ｃｄｉｆｆは２．６と算出される。

In the above equation, Cdiff is the sum of the driving ability differences.
In [Table 3], Cdiff is calculated to be 2.6.

  Next, the sum Sdiff of driving capacity × (slack average value−slack value) is calculated from the following equation for the branch block whose slack value is smaller than the average value.

  In [Table 3], the branch blocks whose slack values are smaller than the average value are the block D and the block E, and Sdiff at this time is calculated as 335.0.

  Based on the values of Cdiff and Sdiff acquired as described above, the drive capability of the block whose slack value is larger than the average value is calculated according to the following equation.

  In [Table 3], for block D and block E, which are branch blocks having a slack value smaller than the average value, that is, having a large timing margin, block D is C ′ = 18.3, and block E is C ′ = 14. 1 and the driving capability is distributed to blocks D and E lower than those currently specified. As described above, since the required driving capability of the block D and the block E is suppressed, a reduction in mounting area and the like can be expected.

  Next, FIG. 16 will be described. This figure is a flowchart showing the processing contents of the driving capacity ratio calculation processing. This process is a process of calculating the ratio (drive capacity ratio) between the drive capacity of the entire branch block for the block to be optimized and the minimum drive capacity among those specified for each branch block. In the process described later, the branch block is optimized by using the value of the driving ability ratio.

  In FIG. 16, steps showing the same processing contents as those in FIG. 14 are denoted by the same reference numerals. As can be seen by comparing FIG. 16 with the flowchart showing the processing contents of the driving ability distribution processing shown in FIG. 14, the processing shown in FIG. 16 is different from the processing of S145 and S146 in FIG. It has been replaced.

  This drive capacity ratio calculation process is a process performed on the branch block subsequent to the block to be optimized after the block optimization on the block to be optimized is completed. This process is executed after the block optimization process of S107 in the conversion process and immediately after the drive capacity distribution process of FIG.

  In FIG. 16, in S151 following the processing of S144, the branch block having the largest slack value, that is, the smallest timing margin is selected from among the branch blocks.

  In the subsequent S152, the ratio of the sum of the drive capacities of all the branch blocks already calculated and the drive capability of the branch block having the maximum slack value, that is, the drive capability ratio is calculated.

A specific example in which the drive capability ratio is calculated by the above-described drive capability ratio calculation processing being performed by the CPU 101 will be described.
In the above-described branch blocks C, D, and E for the block A in the circuit network B of FIG. 15, the respective element names, driving capabilities, slack values, and driving capability calculation values (calculated by the driving capability distribution process described above). Value) is as shown in the table below.

  From the above table, the sum of the drive capabilities of these branch blocks is 48.0, and the slack value is the largest among these branch blocks, that is, the block with the slack value −20.0 has the least timing margin. It is easy to see that it is C.

In [Table 4], the drive capacity calculation value of the block C is 15.6. Therefore, the driving capacity ratio m at this time is

m = 48.0 / 15.6 = 3.1

Is required.

  Next, branch block optimization using this drive capability ratio will be described. FIG. 17 is a flowchart showing the processing contents of the driving capability change rate reflection processing performed using this driving capability ratio.

  This drive capability change rate reflection process is a process performed on the branch block subsequent to the block to be optimized after the block optimization on the block to be optimized is completed. The circuit delay optimization of FIG. This process is executed after the block optimization process of S107 in the process and immediately after the drive capacity distribution process of FIG.

  In FIG. 17, steps showing the same processing contents as those in FIG. 16 are denoted by the same reference numerals. As can be seen by comparing FIG. 17 with the flowchart showing the processing contents of the driving capability ratio calculation processing shown in FIG. 16, the processing shown in FIG. 17 is performed from S153 to S158 following the processing of S152 in FIG. Processing is added.

  In S153 following S152, the optimum drive capacity of the branch block connected to the same drive block having the maximum slack value and the smallest timing margin is calculated. At this time, the drive capability ratio calculated by the process of S152 is used.

  In S154, based on the optimum drive capability obtained in the previous step, among the elements belonging to the same logical element group as the element currently used in the branch block, the optimum satisfying the optimum drive capability of the branch block is obtained. With the correct drive capability is selected and the designation for that branch block is replaced to use that device.

  In S155, for the branch block with the largest slack value, the change rate of the drive capability is calculated from the drive capability of the element replaced in the processing of S154 and the drive capability set before the replacement.

  Thereafter, in S156, it is determined whether or not optimization has been performed on all branch blocks connected to the same drive block. When the result of this determination process is Yes, that is, when it is determined that all branch blocks have been optimized, this drive capacity optimization reflection process ends.

On the other hand, if the result of the determination process in S156 is No, that is, it is determined that there are still branch blocks that have not been optimized, the process proceeds to S157.
In S157, the optimum driving capability for the branch block is calculated based on the driving capability of the branch block to be optimized and the driving capability change rate for the block with the largest slack value.

  In subsequent S158, based on the optimum drive capability obtained in the previous step, among the elements belonging to the same logical element group as the element currently used in the branch block, the optimum satisfying the optimum drive capability of the branch block is obtained. With the correct drive capability is selected and the designation for that branch block is replaced to use that device. After this process is completed, the process returns to S156, and the above-described process is repeated.

The above drive capability optimization reflection process will be further described in detail.
First, let m be the drive capacity ratio described above, that is, the value obtained by dividing the drive capacity of the entire branch block by the drive capacity of the branch block having the maximum slack value.

  When calculating the optimum driving capability for the branch block with the largest slack value in the processing of S153 in FIG. 17, the following formula is used instead of the formula [2] used for the processing of S114 in FIG. .

なお、上式において、
最適化済ブロックの遅延＋被最適化ブランチブロックの遅延：Ｄ
最適化済ブロックの駆動能力：Ｃ１
最適化済ブロックの遅延率：Ｇ１
最適化済ブロックの寄生容量：Ｐ１
被最適化ブランチブロックの駆動能力：ｃ２
被最適化ブランチブロックの遅延率：Ｇ２
被最適化ブランチブロックの寄生容量： Ｐ２
被最適化ブランチブロックの負荷容量： Ｃ３
クロック単位時間： τ
被最適化ブランチブロック分を除いた最適化済ブロックの負荷容量の和
（ネットの負荷容量も含む）：Ｃｏｔｈｅｒ
である。従って、最適化済ブロックの負荷容量は、ｃ２×ｍ＋Ｃｏｔｈｅｒで表されることになる。

In the above formula,
Delay of optimized block + delay of optimized branch block: D
Drive capacity of optimized block: C1
Delay rate of optimized block: G1
Parasitic capacitance of optimized block: P1
Drive capability of optimized branch block: c2
Delay rate of optimized branch block: G2
Parasitic capacitance of optimized branch block: P2
Load capacity of optimized branch block: C3
Clock unit time: τ
Sum of load capacity of optimized blocks excluding optimized branch blocks
(Including net load capacity): Cother
It is. Therefore, the load capacity of the optimized block is represented by c2 × m + Cother.

  If the value obtained by differentiating this [Equation 8] by c2 is 0, the delay of this portion is minimized. Therefore, such a value of c2 is the optimum driving capability. That is,

となり、このｃ２を被最適化ブランチブロックの最適駆動能力とする。
図１７のＳ１５５の処理における駆動能力の変化率の計算では、Ｓ１５４の処理において最適化によって置換された素子の駆動能力をその置換前の素子の駆動能力計算値で除算した結果の値を駆動能力変化率とする。なお、ここでは、駆動能力変化率を係数Ｇとして表すこととする。

Thus, this c2 is set as the optimum drive capability of the branch block to be optimized.
In the calculation of the change rate of the driving capability in the process of S155 of FIG. 17, the value obtained as a result of dividing the driving capability of the element replaced by the optimization in the processing of S154 by the calculated driving capability of the element before the replacement is the driving capability. Change rate. Here, the drive capability change rate is expressed as a coefficient G.

  In [Table 4], the driving ability calculation value before optimization of the block C is 15.6. Here, if the drive capability of the element replaced by the optimization applied to the block C is 16.0, the value of the coefficient G is 1.026.

  On the other hand, the optimum driving capability of other branch blocks whose slack values are not minimum is obtained by multiplying the driving capability calculation value by the coefficient G. For example, it can be seen from [Table 4] that the drive capacity calculation value of block D, which is a branch block whose slack value is not minimum, is 18.3. Here, when the coefficient G is 1.026, the optimum driving capacity of the block D is 18.8. Therefore, in the optimization of the block D, replacement with an element that belongs to the same logical element group as the element currently specified in the block D and has the driving ability closest to the optimum driving ability obtained by the above-described calculation is performed. Done.

  Next, FIG. 18 will be described. This figure is a flowchart showing the processing contents of the pin driving capability instruction detection processing. In this process, when delay optimization is performed, the drive capability value of the input pin of the external element connected to the input terminal of the logic circuit that is the object and the external element connected to the output terminal of the logic circuit network Instead of applying a predetermined value defined in the above-mentioned library or the like for the load capacity value of the input pin (that is, the drive capacity value) or the drive capacity value of the input pin of the block in the circuit, the user can use this It is possible to give instructions to the device arbitrarily, and it is possible to reproduce the connection to the external terminal that is actually assumed, and to optimize it in anticipation of the change at the place where the circuit configuration is scheduled to be changed. It is for.

  The processing of FIG. 18 is executed immediately after the information about the circuit network to be optimized is read by the processing of S101 and S102 in the circuit delay optimization processing of FIG.

  In FIG. 18, first, in S161, it is determined whether or not an external instruction for the pin driving capability has been given to the input unit 105. If the result of this determination is Yes, the process proceeds to S162. On the other hand, if the result of this determination is No, nothing is done as it is, and this pin drive capability instruction detection process is terminated.

In S162, the driving capability instructed to the input unit 105 is read.
In S163, it is determined whether or not the search processing in S164 described later has been performed for all the pins instructed to the input unit 105. If the result of this determination is Yes, the pin driving capability instruction detection processing is terminated. On the other hand, if the result of this determination is No, the process proceeds to S164.

  In S164, the pin instructed to the input unit 105 is searched from the logic circuit network to be optimized, and in subsequent S165, it is determined whether or not the pin exists in the logic circuit network. Only when the determination result in S165 is Yes, in S166, the drive capability value of the pin is changed to the value instructed to the input unit 105, and is reflected in the optimization process performed later. Thereafter, the process returns to S163 and the above-described process is repeated.

A specific example in which an instruction of the pin driving capability is reflected by the CPU 101 performing the processing shown in FIG.
First, in the above-described circuit network B of FIG. 15, it is assumed that the drive capability of each input pin is defined in the library as shown in the following table.

  At this time, when an instruction “block Ca = 10.0” is given by an external instruction, 13.0 is defined in the library for the block Ca pin, but instead, before the optimization. 10.0 is set as the drive capability value. Similarly, when an instruction “circuit network Ba = 13.0” is issued, 13.0 is set as the drive capability value in the circuit network Ba pin. This instruction means that the block A-a pin is driven by a block having a drive capability of 13.0.

If an instruction such as “Block B−b = 16.0” is given, the block B−b pin does not exist in the network B and is ignored.
Next, FIG. 19 will be described. This figure is a flowchart showing the contents of the net load capacity reflection process. This process is a process for enabling the optimization of the delay to reflect the net capacity, that is, the capacity caused by the wiring between the blocks. It should be noted that the net capacity can be partially obtained from information on the mounting design when, for example, circuit delay optimization is performed again after a certain amount of logic circuit mounting design has been performed.

  The processing of FIG. 19 is executed immediately after the information about the circuit network to be optimized is read by the processing of S101 and S102 in the circuit delay optimization processing of FIG.

  In FIG. 19, first, in S171, it is determined whether or not an instruction to reflect the load capacity of the net in the delay optimization is given to the input unit 105. If the result of this determination is Yes, the process proceeds to S172. On the other hand, if the result of this determination is No, the network load capacity reflection process is terminated without doing anything.

  In S172, the load capacity information of each net in the circuit network to be optimized is extracted from the database having the mounting information, and in S173, the information is read from the I / F unit 104 via the communication network.

  In S174, it is determined whether or not a search process in S175, which will be described later, has been performed for all acquired net capacity information. If the result of this determination is Yes, the net load capacity reflecting process is terminated. On the other hand, if the result of this determination is No, the process proceeds to S175.

  In S175, a net (wiring) corresponding to the acquired net capacity information is searched from the logic circuit network to be optimized, and in subsequent S176, it is determined whether or not the net exists in the logic circuit network. Only when the determination result in S176 is Yes, in S177, the load capacity of the net is changed from the value used as standard to the value indicated in the acquired information. Is reflected in the optimization process. Thereafter, the process returns to S174 and the above-described process is repeated.

A specific example in which the load capacity of the net is reflected by the CPU 101 performing the process shown in FIG.
First, it is assumed that there is a database DB1 having mounting information for the circuit network B shown in FIG.

This database DB1 has the mounting wiring information of the nets NetA and NetB in the circuit network B, and also has the load capacity information Cneta and Cnetb of those nets. When these pieces of information are extracted by the processing of S172 in FIG. 19, text information in the following format is sent from the database DB1 to the present apparatus.

NetCapacity {
NetA = Cneta;
NetB = Cnetb;
………
}

The CPU 101 reads and interprets the above information. A load capacity Cneta is set for NetA, and a load capacity Cnetb is set for NetB.

When these values are set, for example, the load capacity of the block A is the sum of the drive capacity of each of the block C-a, the block Da, and the block E-a and the net load capacity Cneta.
Next, FIG. 20 will be described. This figure is a flowchart showing the processing contents of the block non-optimization instruction detection processing. This process is a process that makes it possible not to perform optimization in response to a user instruction for a block in the logical circuit network that is the object of delay optimization. This is effective when, for example, there is a margin in the circuit mounting area and the signal delay, and the already designed one is used as it is without any new mounting design.

  The processing of FIG. 20 is executed immediately after the information about the circuit network to be optimized is read by the processing of S101 and S102 in the circuit delay optimization processing of FIG.

  In FIG. 20, first, in S181, it is determined whether or not an external instruction for non-optimization of a block, that is, an external instruction not to optimize a part of circuit blocks is given to the input unit 105. If the result is Yes, the process proceeds to S182. On the other hand, if the result of this determination is No, this block non-optimization instruction detection process is terminated without doing anything.

In S <b> 182, information indicating a block that is not subjected to optimization instructed to the input unit 105 is read.
In S183, it is determined whether or not a search process in S184 described later has been performed for all the blocks instructed to the input unit 105. If the result of this determination is Yes, the block non-optimization instruction detection process is terminated. . On the other hand, if the result of this determination is No, the process proceeds to S184.

  In S184, the block instructed to the input unit 105 is retrieved from the logic circuit network to be optimized, and in subsequent S185, it is determined whether or not the block exists in the logic circuit network. Only when the determination result in S185 is Yes, an attribute indicating non-optimization is set in the block in S186. Thereafter, the process returns to S183 and the above-described process is repeated.

When the above block non-optimization instruction detection process is executed, the processing content of the circuit delay optimization process of FIG. 3 described above is changed as shown in FIG.
As can be seen from FIG. 21, this change is performed as a process of S187 between the process of S106 and the process of S107 in FIG. 3, and whether or not the non-optimization attribute is set in the optimization target block. A determination process is inserted. As a result of this change, the block optimization process of S107 is executed only when the result of this determination process is Yes.

A specific example will be shown in which the CPU 101 performs the above processing so that the optimization is not performed for some blocks of the logic circuit to be optimized.
In the network B of FIG. 15 described above, for example, when the block D is externally designated as a non-optimized block, the non-optimized attribute is given to the block D. At this time, the drive capacity of the block Da is added as the load capacity in the block A, but the branch block for the block A does not include the block D, and only the blocks C and E are included. That is, the optimization process is not performed for the block D.

  Next, FIG. 22 will be described. This figure is a flowchart showing the processing contents of the element change information output processing. This process makes it possible to present the change contents to the user when a change occurs in the element to be used due to the delay optimization of the circuit, and the change contents can be clearly notified to the user later. The aim is to improve work efficiency in work such as mounting design.

This element change information output process is executed following the circuit delay optimization process of FIG. 3 described above, as shown in the process of S191.
In S192 following S191, it is determined whether or not the user has issued an instruction to output a change information file in which change information of the element to be used is input to the input unit 105. If the result of this determination is Yes, the process proceeds to S193. . On the other hand, if the result of this determination is No, this element change information output process is immediately terminated.

  In S193, it is determined whether or not the processing from S194 to S196, which will be described later, has been performed for all blocks in the logic circuit that is the target of delay optimization. If the result of this determination is Yes, this element change information output processing is performed. Exit. On the other hand, if the result of this determination is No, the process proceeds to S194.

  In S194, the name (unique name) given to the block to be processed is acquired, and in S195, the element name of the element that has been designated to be used before the optimization in the block and its name The element name of the element that is supposed to be used in the block by optimization is acquired.

  In S196, the unique name and the element name acquired by the processes in S195 and S196 described above are associated and stored in the change information file. Thereafter, the process returns to S193 and the above-described process is repeated.

A specific example in which the change information of the element to be used is output by the CPU 101 performing the process shown in FIG.
In the circuit network B of FIG. 15 described above, it is assumed that the elements are replaced as shown in the following table as a result of the circuit delay optimization process described above.

In the process of S196 in FIG. 22, the information shown in the above table is stored in a change information file in the following format, for example, and output.

Change Block A: INV4, INV5;
Change Block B: INV1, INV2;
Change block C: INV2, INV3;
Change block D: 2NAND4, 2NAND4;
Change Block E: 2NOR3, 2NOR2;
Change block F: INV3, INV1;

In order to implement the present invention on a standard computer, a control program for causing the computer to perform the same processing as that performed by the CPU 101 of the present apparatus in the embodiment of the present invention described above. Can be made by reading the control program into a computer and executing it.

  It is also possible to implement the present invention on a computer by recording such a control program on a computer-readable recording medium, causing the computer to read the program from the recording medium and executing the program.

  An example of a recording medium from which the recorded control program can be read by a computer is shown in FIG. As shown in the figure, as a recording medium, for example, a memory 202 such as a ROM or a hard disk device provided as an internal or external accessory device in the computer 201, a floppy (registered trademark) disk, an MO (magneto-optical disk) A portable storage medium 203 such as a CD-ROM or a DVD-ROM can be used. The recording medium may be a storage device 206 provided in a computer functioning as the program server 205 connected to the computer 201 via the line 204. In this case, a transmission signal obtained by modulating a carrier wave with a data signal representing a control program is transmitted from the program server 205 through a line 204 as a transmission medium, and the computer 201 demodulates the received transmission signal. Then, the control program can be executed by reproducing the control program.

  As described in detail above, for the logic circuit formed by connecting a plurality of circuit blocks, the designation of the primitive elements used to configure the circuit block designated for each circuit block is performed. When optimizing the delay of a signal propagating in the logic circuit by changing to another primitive element having the same function as the element and having a different driving capability value, the present invention The load capacity value given to the block is connected to the target circuit block as the preceding stage of the target circuit block that is the target of the designation change, and the delay rate of the circuit block indicating the rate at which the signal propagating in the circuit block is delayed The driving capability value of the preceding circuit block determined by the element designated for the circuit block, and another circuit in the subsequent stage of the target circuit block The drive capacity value required for the target circuit block is calculated based on the load capacity value given to the target circuit block when the lock is connected, and based on the drive capacity value obtained by the calculation The designation of the element used in the target circuit block is changed.

  By doing so, it is possible to select an optimum element for use in the target circuit block from the characteristic values relating to the circuit block connected as the preceding and following stages of the target circuit block. As a result, it is possible to perform the delay optimization for the logic circuit without extracting the critical path by selecting the optimum element for all the circuit blocks in the logic circuit, so that the processing necessary for the delay optimization is performed. The amount is reduced.

  Alternatively, in the present invention, the slack value of the circuit block is calculated, and one output of the circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block. Sometimes, the driving ability value for each subsequent stage circuit block before the designation change determined by the element designated for the succeeding stage circuit block is maintained while the total value of the driving ability values for each succeeding stage circuit block is maintained. Based on the difference in the slack value calculated for each subsequent circuit block, it is distributed to each of the subsequent circuit blocks, and the drive capability value distributed to each of the subsequent circuit blocks is assigned to the circuit block in the previous stage of the subsequent circuit block. The driving ability value required for the subsequent circuit block is calculated as a driving ability value, and the latter circuit block is calculated based on the driving ability value obtained by the calculation. Tsu to perform the specified modification of the device used in the click.

  In this way, based on the slack value of each circuit block, a large amount of driving capacity is distributed to the subsequent circuit block with a small timing margin, and a small amount of driving capacity is distributed to the subsequent circuit block with a large timing margin. Then, it is possible to optimize by giving priority to a signal path having a large signal delay amount, and it is possible to perform delay optimization with a good balance of driving ability.

  Alternatively, in the present invention, the slack value of the circuit block is calculated, and one output of the circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block. Sometimes, there is the least timing margin depending on the sum of the driving capability values for each subsequent circuit block before the designation change determined by the element specified in the subsequent circuit block and the slack value in the subsequent circuit block. The ratio of the driving capacity value before the change of designation is calculated, and based on the ratio, it is indicated that the circuit block in the subsequent stage has the least timing margin depending on the slack value. The driving ability value required for the subsequent circuit block is calculated, and the subsequent circuit is calculated based on the driving ability value calculated based on the ratio. A block to perform the specified change in the rear stage circuit blocks have been shown to have a decreased margin the most timing by slack value.

  By doing this, when changing the designation of the element for the subsequent circuit block, which is shown that the slack value has the least timing margin when the subsequent circuit block constitutes a plurality of fan-outs, Since the characteristic values of the other subsequent circuit blocks that are driven simultaneously with the subsequent circuit blocks are taken into account, the elements can be selected appropriately.

  As described above, the circuit delay of the logic circuit can be optimized by any configuration of the present invention.

(Supplementary Note 1) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of primitive elements used to configure the circuit block designated for each circuit block is the same as the element. A system for optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of
Connected to the target circuit block as a preceding stage of the target circuit block that is the target of the designation change, and a delay rate of the circuit block indicating a rate at which a load capacitance value given to the circuit block delays a signal propagating in the circuit block The driving capability value of the preceding circuit block determined by the element specified for the preceding circuit block being connected to the target circuit block by connecting another circuit block to the subsequent stage of the target circuit block Driving capacity value calculating means for calculating a driving capacity value required for the target circuit block based on a given load capacity value;
Changing means for changing the designation of the element used in the target circuit block based on the driving ability value obtained by the calculation;
A logic circuit delay optimizing system comprising:
(Supplementary note 2) The logic circuit delay according to supplementary note 1, wherein the change unit performs the change so as to select the element that requires the same mounting circuit area as that selected before the change. Optimization system.
(Supplementary Note 3) Occurs until a signal input to the logic circuit or a signal output from a circuit block that is a flip-flop in the logic circuit passes through the previous circuit block of the target circuit block and is output. A delay amount calculating means for calculating a delay amount to be obtained as a delay amount up to the preceding circuit block;
Among a plurality of input pins for inputting a signal to the target circuit block, the previous circuit block for the target circuit block that has the maximum delay amount to the previous circuit block is connected. Representative pin determination means for setting an input pin as a representative pin of a circuit block to be changed,
Further comprising
The drive capability value calculating means performs the calculation based on a drive capability value for a preceding circuit block connected to the representative pin among the preceding circuit blocks for the target circuit block.
The logic circuit delay optimizing system according to appendix 1, wherein
(Supplementary Note 4) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of primitive elements used to configure the circuit block designated for each circuit block is the same as the element. A system for optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of
Slack value calculating means for calculating the slack value of the circuit block;
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. Based on the difference in the slack value calculated for each subsequent stage circuit block while maintaining the total driving capacity value for each subsequent stage circuit block, the driving capacity value for each subsequent stage circuit block before the designation change. Drivability value distribution means for distributing to each subsequent circuit block;
The driving ability value distributed by the driving ability value distributing means is regarded as the driving ability value of the preceding circuit block of the succeeding circuit block, and the driving ability value required for the succeeding circuit block is calculated. A calculation means;
Subsequent circuit block changing means for changing the designation of the element used in the subsequent circuit block based on the driving ability value obtained by the calculation;
A logic circuit delay optimizing system comprising:
(Supplementary Note 5) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used to configure the circuit block designated for each circuit block is the same as the element. A system for optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of
Slack value calculating means for calculating the slack value of the circuit block;
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. The driving ability value before the designation change for the sum of the driving ability values for each subsequent stage circuit block before the designation change and the slack value of the latter stage circuit block showing that the timing margin is the smallest. Driving capacity ratio calculating means for calculating the ratio of
Based on the ratio of the driving ability values calculated by the driving ability ratio calculating means, the driving ability required for the succeeding circuit block which is the latter circuit block and has the least timing margin according to the slack value. First driving ability value calculating means for calculating a value;
Based on the driving ability value obtained by the calculation, the first rear stage circuit that performs the designation change for the rear stage circuit block that has the least timing margin according to the slack value. Block changing means;
A logic circuit delay optimizing system comprising:
(Supplementary Note 6) The driving capacity value before the designation change and the designation after the change by the first latter-stage circuit block changing means for the latter-stage circuit block whose slack value indicates that the timing margin is the smallest. A change rate calculating means for calculating a change rate of these drive capability values from the drive capability values of the elements,
Second driving for calculating a driving capability value required for other subsequent circuit blocks excluding the subsequent circuit block whose slack value indicates the least timing margin based on the rate of change Ability value calculation means;
Other subsequent circuit blocks excluding the latter circuit block that is indicated by the slack value to have the least timing margin based on the driving ability value calculated by the second driving ability value calculating means Second post-stage circuit block changing means for changing the designation of
The logic circuit delay optimization system according to appendix 5, further comprising:
(Additional remark 7) It further has an external element drive capability value input means into which the drive capability value of the element connected to the external input terminal of the said logic circuit is input,
The drive capability value calculation means calculates the drive capability value required for the target circuit block connected to the external input terminal, and the drive capability value input to the external element drive capability value input means is the pre-stage circuit. It is performed assuming that it is the drive capacity value of the block.
The logic circuit delay optimizing system according to any one of appendices 1 to 3, characterized in that:
(Additional remark 8) It further has a preceding stage circuit block driving ability value input means for inputting the driving ability value of the preceding stage circuit block,
The driving ability value calculating means regards the driving ability value input to the preceding circuit block driving ability value input means as the driving ability value of the preceding circuit block and calculates a driving ability value required for the target circuit block. ,
The logic circuit delay optimizing system according to any one of appendices 1 to 3, characterized in that:
(Additional remark 9) It further has an external element load capacitance value input means for inputting a load capacitance value given to the logic circuit by an element connected to the external output terminal of the logic circuit,
The drive capacity value calculating means calculates the drive capacity value required for the target circuit block connected to the external output terminal, and the load capacity value input to the external element load capacity value input means is the target circuit. It is assumed that it is the load capacity value given to the block,
The logic circuit delay optimizing system according to any one of appendices 1 to 3, characterized in that:
(Additional remark 10) It further has wiring capacity acquisition means which acquires wiring capacity which arises by wiring between the circuit blocks obtained by mounting design of the logic circuit,
The drive capability value calculation means calculates the drive capability value required for the target circuit block by adding the wiring capacitance acquired by the wiring capacitance acquisition means to the load capacitance value.
The logic circuit delay optimizing system according to any one of appendices 1 to 3, characterized in that:
(Additional remark 11) It further has the wiring capacity acquisition means which acquires the wiring capacity which arises by wiring between the circuit blocks obtained by performing mounting design of the logic circuit,
The latter-stage circuit block drive capability value calculation means performs the calculation in consideration of the wiring capacity acquired by the wiring capacity acquisition means.
The logic circuit delay optimization system according to appendix 4, wherein:
(Additional remark 12) It further has wiring capacity acquisition means for acquiring wiring capacity generated by wiring between the circuit blocks obtained by performing mounting design of the logic circuit,
The first drive capability value calculation means obtains the wiring capacity by calculating the drive capability value required for the subsequent circuit block which is the latter circuit block and has the least timing margin according to the slack value. Take into account the wiring capacity acquired by the means,
The logic circuit delay optimizing system according to appendix 5, characterized in that:
(Additional remark 13) It further has the wiring capacity acquisition means which acquires the wiring capacity which arises by the wiring between the said circuit blocks obtained by mounting design of the said logic circuit,
The first drive capability value calculation means obtains the wiring capacity by calculating the drive capability value required for the subsequent circuit block which is the latter circuit block and has the least timing margin according to the slack value. Take into account the wiring capacity acquired by the means,
The second drive capability value calculation means calculates a drive capability value required for the other subsequent circuit block except for the latter circuit block, which is indicated by the slack value to have the least timing margin. In consideration of the wiring capacity acquired by the wiring capacity acquisition means,
The logic circuit delay optimization system according to appendix 6, wherein:
(Additional remark 14) It further has a non-optimization attribute provision means to provide the attribute which shows not changing the said designation | designated with respect to the said circuit block,
The changing means does not change the designation for the target circuit block to which the attribute is given by the non-optimized attribute giving means,
The logic circuit delay optimizing system according to any one of appendices 1 to 3, characterized in that:
(Supplementary note 15) Any one of Supplementary notes 1 to 3, further comprising change content output means for outputting the content of the change in the target circuit block in which the designated change has been made by the change means. The logic circuit delay optimization system according to one item.
(Supplementary Note 16) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used to configure the circuit block designated for each circuit block is the same as the element. A method for optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of
Connected to the target circuit block as a preceding stage of the target circuit block that is the target of the designation change, and a delay rate of the circuit block indicating a rate at which a load capacitance value given to the circuit block delays a signal propagating in the circuit block The driving capability value of the preceding circuit block determined by the element specified for the preceding circuit block being connected to the target circuit block by connecting another circuit block to the subsequent stage of the target circuit block Based on the given load capacity value, the drive capacity value required for the target circuit block is calculated,
The designation of the element used in the target circuit block is changed based on the driving capability value obtained by the calculation.
A logic circuit delay optimizing method characterized by the above.
(Supplementary Note 17) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used for configuring the circuit block designated for each circuit block is the same as the element. A method for optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of
Calculate the slack value of the circuit block,
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. Based on the difference in the slack value calculated for each subsequent stage circuit block while maintaining the total driving capacity value for each subsequent stage circuit block, the driving capacity value for each subsequent stage circuit block before the designation change. Distributed to each of the subsequent circuit blocks,
The driving ability value distributed to each of the subsequent circuit blocks is regarded as the driving ability value of the preceding circuit block of the succeeding circuit block, and the driving ability value required for the succeeding circuit block is calculated.
The designation of the element used in the subsequent circuit block is changed based on the driving ability value obtained by the calculation.
A logic circuit delay optimizing method characterized by the above.
(Supplementary Note 18) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used for configuring the circuit block designated for each circuit block is the same as the element. A method for optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of
Calculate the slack value of the circuit block,
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. The driving ability value before the designation change for the sum of the driving ability values for each subsequent stage circuit block before the designation change and the slack value of the latter stage circuit block showing that the timing margin is the smallest. The ratio of
Based on the ratio, the driving ability value required for the subsequent circuit block that is the latter circuit block and has the least timing margin indicated by the slack value;
The designation change is made for the subsequent circuit block which is the latter circuit block based on the driving capacity value calculated based on the ratio and whose slack value indicates the least timing margin.
A logic circuit delay optimizing method characterized by the above.
(Supplementary Note 19) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of primitive elements used for configuring the circuit block designated for each circuit block is the same as the element. A program for causing a computer to perform a process of optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of ,
Connected to the target circuit block as a preceding stage of the target circuit block that is the target of the designation change, and a delay rate of the circuit block indicating a rate at which a load capacitance value given to the circuit block delays a signal propagating in the circuit block The driving capability value of the preceding circuit block determined by the element specified for the preceding circuit block being connected to the target circuit block by connecting another circuit block to the subsequent stage of the target circuit block A process for calculating a drive capacity value required for the target circuit block based on a given load capacity value;
A process of changing the designation of the element used in the target circuit block based on the driving ability value obtained by the calculation;
A program for causing the computer to execute.
(Supplementary Note 20) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of primitive elements used to configure the circuit block designated for each circuit block is the same as the element. A program for causing a computer to perform a process of optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of ,
Processing for calculating the slack value of the circuit block;
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. Based on the difference in the slack value calculated for each subsequent stage circuit block while maintaining the total driving capacity value for each subsequent stage circuit block, the driving capacity value for each subsequent stage circuit block before the designation change. Processing distributed to each of the subsequent circuit blocks;
A process of calculating a driving capability value required for the subsequent circuit block by regarding the driving capability value distributed to each of the subsequent circuit blocks as the driving capability value of the preceding circuit block of the subsequent circuit block;
A process of changing the designation of the element used in the subsequent circuit block based on the driving ability value obtained by the calculation;
A program for causing the computer to execute.
(Supplementary Note 21) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used for configuring the circuit block designated for each circuit block is the same as the element. A program for causing a computer to perform a process of optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of ,
Processing for calculating the slack value of the circuit block;
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. The driving ability value before the designation change for the sum of the driving ability values for each subsequent stage circuit block before the designation change and the slack value of the latter stage circuit block showing that the timing margin is the smallest. Processing to calculate the ratio of
Based on the ratio, a process for calculating a driving ability value required for the subsequent circuit block, which is indicated by the slack value and has the least timing margin based on the ratio,
A process of changing the designation of the subsequent circuit block which is the latter circuit block and has the least timing margin based on the slack value based on the drive capacity value calculated based on the ratio; ,
A program for causing the computer to execute.
(Supplementary Note 22) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of primitive elements used to configure the circuit block designated for each circuit block is the same as the element. A carrier including a program for causing a computer to perform a process for optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of The computer data signal embodied in the program causes the computer to:
Connected to the target circuit block as a preceding stage of the target circuit block that is the target of the designation change, and a delay rate of the circuit block indicating a rate at which a load capacitance value given to the circuit block delays a signal propagating in the circuit block The driving capability value of the preceding circuit block determined by the element specified for the preceding circuit block being connected to the target circuit block by connecting another circuit block to the subsequent stage of the target circuit block A process for calculating a driving capability value required for the target circuit block based on a given load capacitance value, and designation of the element used in the target circuit block based on the driving capability value obtained by the calculation The process of making changes.
(Supplementary Note 23) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of primitive elements used to configure the circuit block designated for each circuit block is the same as the element. A carrier including a program for causing a computer to perform a process for optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of The computer data signal embodied in the program causes the computer to:
Processing for calculating the slack value of the circuit block;
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. Based on the difference in the slack value calculated for each subsequent stage circuit block while maintaining the total driving capacity value for each subsequent stage circuit block, the driving capacity value for each subsequent stage circuit block before the designation change. Processing to distribute to each of the subsequent circuit blocks,
A process for calculating a driving capability value required for the subsequent circuit block by regarding the driving capability value distributed to each of the subsequent circuit blocks as a driving capability value of a circuit block preceding the subsequent circuit block; and A process of changing the designation of the element used in the subsequent circuit block based on the obtained driving ability value.
(Supplementary Note 24) For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used to configure the circuit block designated for each circuit block is the same as the element. A carrier including a program for causing a computer to perform a process for optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a function of The computer data signal embodied in the program causes the computer to:
Processing for calculating the slack value of the circuit block;
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. The driving ability value before the designation change for the sum of the driving ability values for each subsequent stage circuit block before the designation change and the slack value of the latter stage circuit block showing that the timing margin is the smallest. Processing to calculate the ratio of
Based on the ratio, a process for calculating a driving capability value required for the subsequent circuit block which is the latter circuit block and has the least timing margin according to the slack value, and calculated based on the ratio A process of changing the designation of the subsequent circuit block that is indicated by the slack value to have the least timing margin based on the driven capacity value.

It is a figure which shows the principle structure of this invention. It is a figure which shows the structure of the logic circuit delay optimization apparatus which implements this invention. It is a flowchart which shows the processing content of a circuit delay optimization process. It is a flowchart which shows the processing content of the 1st example of a block optimization process. It is a figure which shows the example of the library in which element information is defined. It is a figure which shows the example of the circuit network which performs a delay optimization process. FIG. 6 is a diagram showing the result of stage number detection performed for each block of circuit network A. FIG. 6 is a diagram illustrating delay calculation performed on each block of the network A. 6 is a diagram illustrating an example of a calculation result of a maximum delay performed for each block of the circuit network A. FIG. 6 is a diagram illustrating an example of a calculation result of an allowable arrival time performed for each block of the circuit network A. FIG. 6 is a diagram illustrating an example of a result of calculating a slack value performed on each block of the circuit network A. FIG. It is a flowchart which shows the processing content of the 2nd example of a block optimization process. It is a flowchart which shows the processing content of a representative pin selection process. It is a flowchart which shows the processing content of a driving capability distribution process. It is a figure which shows an example of the circuit network which performs a driving capability distribution process. It is a flowchart which shows the processing content of a driving capability ratio calculation process. It is a flowchart which shows the processing content of a driving capability change rate reflection process. It is a flowchart which shows the processing content of a pin drive capability instruction | indication detection process. It is a flowchart which shows the processing content of a net load capacity instruction | indication reflection process. It is a flowchart which shows the processing content of a block non-optimization instruction | indication detection process. It is a figure which shows a change when a block non-optimization instruction | indication is performed in the circuit optimization process shown in FIG. It is a flowchart which shows the processing content of an element change information output process. It is a figure which shows the example of the recording medium which can read the recorded control program with a computer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Drive ability value calculation means 12 Change means 21, 31 Slack value calculation means 22 Drive ability value distribution means 23 Subsequent circuit block drive ability value calculation means 24 Subsequent circuit block change means 32 Drive ability ratio calculation means 33 First drive ability value calculation Means 34 First post-stage circuit block changing means 101 Input unit 102 ROM
103 RAM
104 I / F unit 105 Input unit 106 Display unit 107 Output unit 108 Storage unit 109 Bus 201 Computer 202 Memory 203 Portable storage medium 204 Line 205 Program server 206 Storage device

Claims (6)

For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used to configure the circuit block designated for each circuit block has the same function as the element. And a system for optimizing the delay of a signal propagating in the logic circuit by changing to another primitive element having a different driving capability value,
Slack value calculating means for calculating the slack value of the circuit block;
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. Based on the difference in the slack value calculated for each subsequent stage circuit block while maintaining the total drive capacity value for each subsequent stage circuit block, the driving capacity value for each subsequent stage circuit block before the designation change Driving capability value distribution means for distributing to each of the subsequent circuit blocks;
The driving ability value distributed by the driving ability value distributing means is regarded as the driving ability value of the preceding circuit block of the succeeding circuit block, and the driving ability value required for the succeeding circuit block is calculated. A calculation means;
Subsequent circuit block changing means for changing the designation of the element used in the subsequent circuit block based on the driving ability value obtained by the calculation;
A logic circuit delay optimizing system comprising: For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used to configure the circuit block designated for each circuit block has the same function as the element. And a logic circuit delay optimization method performed by a logic circuit delay optimization system for optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a different driving capability value. There,
The slack value calculating means of the logic circuit delay optimization system calculates the slack value of the circuit block,
Drive capability value distribution means of the logic circuit delay optimization system when one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block However, while maintaining the drive capability value for each subsequent circuit block before the designation change determined by the element specified for the subsequent circuit block, the total value of the drive capability values for each subsequent circuit block is maintained, and , Based on the difference in the slack value calculated for each subsequent circuit block, distributed to each of the subsequent circuit blocks,
The subsequent circuit block drive capability value calculating means of the logic circuit delay optimization system regards the drive capability value distributed to each of the subsequent circuit blocks as the drive capability value of the previous circuit block of the subsequent circuit block. Calculate the drive capability value required for the subsequent circuit block,
The subsequent circuit block changing means of the logic circuit delay optimization system changes the designation of the element used in the subsequent circuit block based on the driving capability value obtained by the calculation.
A logic circuit delay optimizing method characterized by the above. For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used to configure the circuit block designated for each circuit block has the same function as the element. And a program for causing a computer to perform a process of optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a different driving capability value,
Processing for calculating the slack value of the circuit block;
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. Based on the difference in the slack value calculated for each subsequent stage circuit block while maintaining the total drive capacity value for each subsequent stage circuit block, the driving capacity value for each subsequent stage circuit block before the designation change And distributing to each of the subsequent circuit blocks;
A process of calculating a driving capability value required for the subsequent circuit block by regarding the driving capability value distributed to each of the subsequent circuit blocks as the driving capability value of the preceding circuit block of the subsequent circuit block;
A process of changing the designation of the element used in the subsequent circuit block based on the driving ability value obtained by the calculation;
A program for causing the computer to execute. For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used to configure the circuit block designated for each circuit block has the same function as the element. And a system for optimizing the delay of a signal propagating in the logic circuit by changing to another primitive element having a different driving capability value,
Slack value calculating means for calculating the slack value of the circuit block;
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. The driving ability value before the designation change for the sum of the driving ability values for each subsequent stage circuit block before the designation change and the slack value of the latter stage circuit block showing that the timing margin is the smallest. Driving capacity ratio calculating means for calculating the ratio of
Based on the ratio of the driving ability values calculated by the driving ability ratio calculating means, the driving ability required for the succeeding circuit block which is the latter circuit block and has the least timing margin according to the slack value. Driving ability value calculating means for calculating a value;
Subsequent circuit block change that performs the specified change for the subsequent circuit block that is the latter circuit block and has the least timing margin based on the slack value based on the drive capability value obtained by the calculation Means,
A logic circuit delay optimizing system comprising: For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used to configure the circuit block designated for each circuit block has the same function as the element. And a logic circuit delay optimization method performed by a logic circuit delay optimization system for optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a different driving capability value. There,
The slack value calculating means of the logic circuit delay optimization system calculates the slack value of the circuit block,
Drive capability ratio calculation means of the logic circuit delay optimization system when one output of the circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block However, there is a minimum timing margin depending on the sum of the driving capability values for each subsequent circuit block before the designation change determined by the element specified for the subsequent circuit block and the slack value of the subsequent circuit block. Calculate the ratio with the driving ability value before the designated change for those indicated by
The driving capability value calculation means included in the logic circuit delay optimization system is required for the subsequent circuit block that is indicated by the slack value to have the least timing margin based on the ratio. Calculate the driving ability value
It is indicated that the subsequent circuit block changing means of the logic circuit delay optimization system is the latter circuit block based on the driving capability value calculated based on the ratio and has the least timing margin depending on the slack value. Changing the designation for the subsequent circuit block being
A logic circuit delay optimizing method characterized by the above. For a logic circuit formed by connecting a plurality of circuit blocks, the designation of a primitive element used to configure the circuit block designated for each circuit block has the same function as the element. And a program for causing a computer to perform a process of optimizing a delay of a signal propagating in the logic circuit by changing to another primitive element having a different driving capability value,
Processing for calculating the slack value of the circuit block;
When one output of a circuit block in the logic circuit is connected to a subsequent circuit block that is a plurality of circuit blocks subsequent to the circuit block, the output is determined by the element specified for the subsequent circuit block. The driving ability value before the designation change for the sum of the driving ability values for each subsequent stage circuit block before the designation change and the slack value of the latter stage circuit block showing that the timing margin is the smallest. Processing to calculate the ratio of
Based on the ratio, a process for calculating a driving ability value required for the subsequent circuit block, which is indicated by the slack value and has the least timing margin based on the ratio,
A process of changing the designation of the subsequent circuit block which is the latter circuit block and has the least timing margin based on the slack value based on the drive capacity value calculated based on the ratio; ,
A program for causing the computer to execute.

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