JP2007011477A - Logical circuit operation model generation device and logical circuit operation model generation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logical circuit operation model generation device which realizes simulation precision which is sufficient for achieving a purpose of verification, completes simulation within a permissible range of time even in a large-scale system, and generates an adequate logical circuit operation model in a short period even if a designer of the circuit is different from the designer of a logical circuit operation model. <P>SOLUTION: The logical circuit operation model generation device is provided with; a generation part which integrates a logical circuit RTL model, which is obtained by describing the operation of a logical circuit with an RTL, with an external operation model which describes an input/output operation, and generates a first logical circuit operation model which integrally describes the operations of the logical circuit and external device connected to the logical circuit; and a conversion part which inputs a restricted model in which verification precision is described in accordance with a purpose of verification, and reduces and converts the scale of the first logical circuit operation model within a range, in which the verification precision is guaranteed, based on the restricted model, to generate a second logical circuit operation model. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a logic circuit operation model generation apparatus and a logic circuit operation model generation method, and in particular, a logic circuit operation model that generates a logic circuit operation model by converting a logic circuit RTL model expressed in a hardware description language or the like. The present invention relates to a generation device and a logic circuit operation model generation method.

  In recent years, in the design and manufacture of large-scale logic circuits such as LSI, hardware is described in a language called HDL (Hardware Description Language), and the described HDL is converted into data representing the connection relationship of circuit elements called a netlist. In many cases, hardware such as an actual LSI is manufactured from this netlist.

  Conversion from the HDL to the netlist is called “logic synthesis”, and the HDL can be converted into the netlist using a predetermined logic synthesis tool. The netlist is data representing the mutual connection relationship with circuit elements such as an AND circuit, an OR circuit, a register, and a counter, for example, and a conventional so-called circuit diagram can be printed out using this netlist. is there.

  There are various hardware description languages (HDLs), and for example, HDLs such as Verilog-HDL, VHDL, and SystemC are often used today. In addition, there are several description levels in HDL, typically, a behavior level and a register transfer level (RTL).

  The behavior level represents an operation (including not only a hardware operation but also a software operation) without a “clock concept”. It is used to describe circuit blocks whose detailed design specifications are not fixed, and to describe models for simulation purposes, for example, modeled CPU operations.

  On the other hand, a register transfer level (RTL) is a level that expresses a register, a counter, etc., which are circuit components, and a data transfer state (connection state) between them. There is a “clock concept” for operating these.

  In order to “logic-synthesize” HDL and generate a netlist, it is necessary to describe HDL at a register transfer level (hereinafter simply referred to as RTL). A logic circuit described in HDL at the RTL level is called a “logic circuit RTL model”.

  On the other hand, in today's large-scale circuits, in addition to designing the circuit itself, verification and evaluation of the designed circuit has become very important. By carrying out sufficient verification and evaluation (before making an object) at the design stage, the development period can be shortened and the development cost can be reduced.

  Furthermore, many of today's systems are generally hardware / software integrated systems including a microprocessor and the like. For this reason, it is becoming necessary to verify and evaluate not only hardware but also software that operates on a microprocessor or the like.

  By the way, a logic circuit widely used today is a synchronous logic circuit, and in the “logic circuit RTL model”, writing to a defined register group is written using a synchronization signal such as a clock and a reset. It is described in. Therefore, the temporal accuracy that can be evaluated by the “logic circuit RTL model” is an accuracy that ensures that the value of the register can be verified each time a synchronization signal such as a periodic clock is input. (Hereinafter, this accuracy will be referred to as clock cycle accuracy). As described above, the verification using the “logic circuit RTL model” enables very precise verification every clock cycle.

  However, in a large-scale logic circuit including a microprocessor, etc., each logic circuit and software that communicates with each other and operates on the microprocessor are connected to the “logic circuit RTL model” and the microprocessor simulator. When verifying with clock cycle accuracy using a simulation environment, there is a big problem that the simulation time becomes enormous.

  On the other hand, when verifying software such as a microprocessor that communicates with the “logic circuit RTL model”, it is not always necessary to verify with fine accuracy such as clock cycle accuracy. Further, it is not necessary to verify all the states of the registers in the “logic circuit RTL model”.

  Therefore, the simulation time can be reduced by reducing the temporal accuracy of the simulation (time roughness for monitoring and verification) and the spatial accuracy (types and amounts of registers and signals to be monitored and verified) as long as the verification purpose is achieved. Various techniques have been developed to shorten the time.

  For example, Patent Documents 1 to 3 disclose a technique for creating a simulation model with a rough simulation accuracy (high abstraction level) and sequentially refining the simulation model. Among these, Patent Document 1 discloses a technique for creating a model of a programming language that can be sequentially processed, greatly reducing the time required for verification, and easily realizing system level verification. Further, Patent Document 2 discloses a model with coarse accuracy by performing bit precision conversion for displaying decimal points of input / output data and converting bit widths using an interface model that connects a model with coarse simulation accuracy and a fine model. A technique for replacing a part is disclosed. Patent Document 3 discloses a technique for preparing a behavior description with rough simulation accuracy for each predetermined motion unit, and selecting them to create a model.

  On the other hand, there is also a technology that creates a model with a low simulation accuracy (low abstraction level) and summarizes it. For example, Patent Document 4 discloses a technique for shortening a logic verification time by omitting an event generated in a circuit that performs a logic operation in synchronization with one clock domain. Patent Document 5 discloses a technique for reducing a part of a logic circuit model by fixing a part of input and register values according to a verification purpose. Patent Document 6 discloses a technique for creating a table for each time in a clock cycle by taking advantage of the characteristics of a synchronous circuit and performing an event schedule before performing a simulation.

  Further, in Patent Document 7, the states of the logic circuit block are set as the operation start state and the operation end state, and a sequence of input / output instructions for making a transition from the state to the state is given to the RTL model every clock and the operation is performed. A technique for extracting and creating a model having no concept of time is disclosed.

Also, in Patent Document 8, a circuit corresponding to a control unit that characterizes the operation of a logic circuit is specified, a circuit whose operation is determined by the control unit is extracted, and a model suitable for a programming language for software is created. Technology is disclosed.
JP 2001-14356 A JP 2001-101247 A JP 2003-141204 A JP 2004-185213 A Japanese Patent Laid-Open No. 2001-22808 US Pat. No. 5,862,361 Japanese Patent Laid-Open No. 2003-16134 JP 2004-21841 A

  As described above, a model for performing a simulation (hereinafter, this model is referred to as a “logic circuit operation model”) is a newly generated model having a high abstraction level apart from the “logic circuit RTL model”. It is converted into a “logic circuit operation model” by summarizing it using a method of generating a “logic circuit operation model” by refinement sequentially or an existing “logic circuit RTL model” (a model with low abstraction level). Often generated by methods.

  The quality of the “logic circuit operation model” must be judged from two viewpoints: the quality of the “logic circuit operation model” (first condition) and the time and effort for creating the “logic circuit operation model” (second condition). is there.

  The quality (first condition) of the “logic circuit operation model” ensures sufficient simulation accuracy (temporal accuracy and spatial accuracy) to achieve the verification purpose, and simulation is executed even for a large-scale system. The time is within a practically acceptable range.

  In addition, the time required for creating the “logic circuit operation model” (second condition) was that the “logic circuit operation model” was consistent with the “logic circuit RTL model” by the time when the verification of the logic circuit or software program was started. Is to be provided in a state.

  A method (Patent Documents 1 to 3) of newly creating a model with high simulation accuracy (high abstraction level) and sequentially refining the model is performed manually (or semi-automatically) according to the purpose of verification. This is a method of creating a “model”. For this reason, the quality (first condition) of the “logic circuit operation model” is achieved if sufficient manpower and time are required.

  However, this method is a double development of the “logic circuit operation model” and the “logic circuit RTL model”, and there is a problem that consistency between the two models cannot be guaranteed. In addition, when incorporating a logic circuit that has been designed in the past, there are many cases where a “logic circuit RTL model” exists, but there is no “logic circuit operation model”. Need to develop. This causes a problem that the development of the “logic circuit operation model” is not completed before the verification start time (that is, the second condition is not satisfied). In addition, as disclosed in Patent Document 3, although the creation period can be shortened by creating a “component” for creating a “logic circuit operation model” in advance, the created “component” group and the “logic” Since the consistency cannot be inspected with the “circuit RTL model”, the problem that the consistency between the “logic circuit operation model” and the “logic circuit RTL model” cannot be guaranteed becomes more serious.

  On the other hand, methods for summarizing models with low simulation accuracy (low abstraction) (Patent Documents 4 to 8) automatically summarize a designed “logic circuit RTL model” as a starting point, and “logic circuit operation model”. Therefore, the possibility that the second condition (development effort) is satisfied is relatively high.

  However, in the disclosed prior art, in a development period that satisfies the second condition, an appropriate temporal and spatial accuracy suitable for the verification purpose is ensured, and the system is a large-scale system. However, it is expected that it is difficult to obtain a “logic circuit operation model” that satisfies the first condition that the simulation execution time is within a practically acceptable range.

  For example, Patent Document 4 or Patent Document 5 maintains clock cycle accuracy as temporal accuracy, is excessive accuracy for system level verification, and simulation execution time becomes enormous and the first condition is satisfied. Do not meet.

  On the other hand, the method disclosed in Patent Document 7 includes a step of manually setting the internal state of the “logic circuit RTL model”, and the internal state set manually is used as a starting point for conversion to the “logic circuit operation model”. Is. Therefore, a desired “logic circuit operation model” cannot be obtained unless the behavior of the logic circuit to be modeled is sufficiently analyzed and the internal state is appropriately set so that there is no leakage or duplication. In addition, when all “logic circuit operation models” are generated manually, the process of analyzing the behavior of the logic circuit to be modeled through specifications etc. and defining the internal state appropriately so that there is no leakage or duplication is the process It is generally considered to account for about half of the total. For this reason, even if the process of actually describing the model and the process of ensuring the consistency of the model are reduced, a lot of time is spent on the process of appropriately defining the internal state, and as a result, the second condition ( There is a high possibility that the development effort will not be satisfied. Furthermore, since the method disclosed in Patent Document 7 is a method of converting from a “logic circuit RTL model” having a concept of time to a “logic circuit operation model” having no concept of time, a specific time is designated. Monitoring and verification cannot be performed, and the verification application is limited.

  The method of Patent Document 8 designates a control unit of a logic circuit and uses it as a starting point, thereby eliminating the internal state setting step used in the method of Patent Document 7. However, there is no detailed knowledge about the “logic circuit RTL model” because there are a plurality of control units dispersed in the circuit, or because the logic circuit designer and the “logic circuit operation model” designer are different. In some cases, it may be difficult to specify an appropriate control unit, and there is room for improvement.

  The present invention has been made in view of the above circumstances, achieves sufficient simulation accuracy to achieve the verification purpose, and can keep the simulation execution time within an allowable range even in a large-scale system. A logic circuit operation model generation apparatus and a logic circuit operation model generation method capable of generating an accurate “logic circuit operation model” in a short period of time even when the circuit designer and the “logic circuit operation model” designer are different The purpose is to provide.

  In order to solve the above-described problem, a logic circuit operation model generation apparatus according to the present invention includes a logic circuit RTL model in which an operation of a logic circuit is described at a register transfer level and the logic circuit RTL as described in claim 1. A generating unit that integrates an external operation model including a description of input / output operations for the model, and generates a first logic circuit operation model that integrally describes the operation of the logic circuit and the operation of an external device coupled thereto. A constraint model describing verification accuracy according to the verification purpose is input, and the scale of the first logic circuit operation model is reduced and converted within a range in which the verification accuracy is guaranteed based on the constraint model, And a conversion unit that generates a logic circuit operation model of the instruction, wherein the generation unit represents an instruction representing a procedure, a variable representing a value used or generated by the instruction, a time, and a branch state. It is possible to describe a graph with a node representing a storage location of a storage element including a number and a register as a node, and an arrow line connecting the nodes as a branch so as to indicate the usage relationship or substitution relationship of the instruction and each variable. A first logic circuit operation model, or a first logic circuit operation model described by an adjacency matrix or an edge list that can be mutually converted with the graph is generated.

  The logic circuit operation model generation method according to the present invention includes a logic circuit RTL model in which the operation of the logic circuit is described at a register transfer level, and an input / output operation for the logic circuit RTL model. And generating a first logic circuit operation model that integrally describes the operation of the logic circuit and the operation of the external device coupled thereto, and for verification purposes. A constraint model in which the corresponding verification accuracy is described is input, the scale of the first logic circuit operation model is reduced and converted within a range in which the verification accuracy is guaranteed based on the constraint model, and a second logic circuit operation model And a conversion step for generating an instruction representing a procedure, a variable representing a value used or generated by the instruction, a time, and a branch state. Variables and variables representing the storage location of storage elements including registers can be described as nodes, and graphs with branches as arrows connecting the nodes to indicate the usage relationship or substitution relationship of the instructions and the variables can be described. A first logic circuit operation model, or a first logic circuit operation model described by an adjacency matrix or an edge list that can be mutually converted with the graph is generated.

  According to the logic circuit operation model generation apparatus and the logic circuit operation model generation method of the present invention, simulation accuracy sufficient to achieve the verification purpose is achieved, and the simulation execution time is allowed even in a large-scale system. Even when the circuit designer and the “logic circuit operation model” designer are different, an accurate “logic circuit operation model” can be generated in a short period of time.

  Embodiments of a logic circuit operation model generation device and a logic circuit operation model generation method according to the present invention will be described with reference to the accompanying drawings.

(1) Positioning and Configuration of Logic Circuit Operation Model Generation Device FIG. 1 is a diagram conceptually illustrating the positioning of a logic circuit operation model generation device and a logic circuit operation model generation method according to the present invention.

  The left diagram of FIG. 1 is a diagram modeling a system configuration of a large-scale logic circuit as a target. In this model, the large-scale logic circuit 200, the logic circuit 210, and the microprocessor 220 are connected to each other via a bus.

  Among these, the large-scale logic circuit 200 is a circuit that has already been designed and has a track record, or a level at which detailed design has been completed. That is, the large-scale logic circuit 200 already has a model described in a hardware description language at a register transfer level (RTL) capable of logic synthesis. This model is called a logic circuit RTL model 100.

  On the other hand, the logic circuit 210 is in a schematic design stage, and there is no hardware description language at the register transfer level (RTL). However, the general functional performance and external interface (transaction via the bus) are determined.

  It is also assumed that the external interface is determined for the software executed by the microprocessor 220. In other words, the logic circuit 210 and the software of the microprocessor 220 are at a level at which transactions (reading and writing) via the bus can be described. This is called model 110.

  The position of the present invention is to generate a model for verifying a system having such a configuration by simulation or the like with “roughness” according to the verification purpose.

  The logic circuit RTL model 100 in which the large-scale logic circuit 200 is described in RTL is described in such a manner that signal transmission between registers can be expressed at the level of a clock unit.

  Therefore, in a model in which the logic circuit RTL model 100 and the external operation model 110 are simply combined (referred to as the first logic circuit operation model 50), the circuit operates at each clock and the internal state also changes at each clock. Therefore, the verification time becomes enormous.

  On the other hand, verification by simulation or the like is usually performed for some verification purpose, and the verification accuracy required depending on the verification purpose differs. Here, the verification accuracy refers to both temporal accuracy and the range (spatial accuracy) of the circuit to be verified.

  Normally, in the verification of software and the verification of the logic circuit in the schematic design stage, the temporal accuracy of the clock level and the spatial accuracy that covers all registers as the verification range are unnecessary.

  Therefore, a constraint model describing the verification accuracy required for the purpose of verification is defined, the first logic circuit operation model 50 is reduced and converted under the constraints of the constraint model, and the second logic circuit operation model 60 is obtained. The second logic circuit operation model 60 is generated and a simulation or the like is verified. As a result, the system can be evaluated in a short time and with verification accuracy according to the verification purpose.

  The logic circuit operation model generation apparatus and the logic circuit operation model generation method according to the present invention automatically generate the first logic circuit operation model 50 from the logic circuit RTL model 100 and the external operation model 110, and The conversion is automatically reduced to the logic circuit operation model 60.

  FIG. 2 is a diagram showing a configuration example of an embodiment of the logic circuit behavior model generation device 1 according to the present invention.

  The logic circuit operation model generation apparatus 1 includes a generation unit 2 that generates a first logic circuit operation model 50 from the logic circuit RTL model 100 and the external operation model 110, and a first circuit that is generated under the constraints of the constraint model 120. The logic circuit operation model 50 is reduced and converted to generate a second logic circuit operation model 60.

  The conversion unit 3 obtains an “evaluation symbol” under the constraints of the constraint model 120 for each node (a point representing an instruction or a variable) inside the first logic circuit operation model 50, and generates an evaluation symbol table. Based on the evaluation symbol table, the symbol evaluation unit 30 determines whether or not reduction conversion of a predetermined method is possible, generates a reduction conversion table, and a first logic based on the reduction conversion table. An updating unit 32 that performs reduction conversion from the circuit operation model 50 to the second logic circuit operation model 60 and outputs a predetermined analysis result is provided.

(2) Operation of Logic Circuit Operation Model Generation Device 1 FIG. 3 is a flowchart showing a basic operation flow of the logic circuit operation model generation device 1.

  In step ST1, a first logic circuit operation model 50 is generated from the logic circuit RTL model 100 and the external operation model 110.

  In step ST2, a symbol evaluation rule and a constraint model 120 that are determined in advance for each location (each node) on the description of the first logic circuit operation model 50 (or the second logic circuit operation model 60 during the reduction conversion). Based on the above, an “evaluation symbol” is obtained, and an evaluation symbol table is generated.

  Next, in step ST3, the first logic circuit operation model 50 (or the second logic circuit operation model 60 during the reduction conversion) and the evaluation symbol table are referred to, and reduction is performed based on a predetermined reduction conversion determination criterion. It is determined whether or not conversion is possible, and whether or not reduction conversion is possible for each location (each node) on the description of the first logic circuit operation model 50 (or the second logic circuit operation model 60 during reduction conversion) is described. A reduced conversion table is generated. In addition, an analysis result report may be generated in this step.

  In step ST4, it is determined whether or not there is a place where the reduction conversion is possible in the reduction conversion table. If there is a place where reduction conversion is possible, the process proceeds to step ST5.

  In step ST5, the first logic circuit operation model 50 (or the second logic circuit operation model 60 during the reduction conversion) is reduced and converted according to the contents of the reduction conversion table to generate the second logic circuit operation model 60. The part for which the reduction conversion is completed is deleted from the reduction conversion table.

  Part of the description structure of the second logic circuit operation model 60 is changed by the reduction conversion in step ST5. For this reason, it is set as the form which returns to step ST2 again and produces | generates the evaluation symbol table | surface of each location again based on the changed structure.

  Step ST2 to step ST5 are repeated until it is determined in step ST4 that there is no portion that can be reduced and converted.

  When there is no place where reduction conversion is possible, the final second logic circuit operation model 60 is generated.

  When time is required for the reduction conversion process, it may be configured to be interrupted when step ST3 is completed by an external operation.

  After the interruption, as a result of the analysis of the analysis result report or the like by the designer, it may be determined that further reduction is possible by making an appropriate correction to the constraint model 120. In such a case, it is good also as a form which restarts from step ST2 after correcting the constraint model 120. FIG.

  Each of the above steps will be described in detail below with specific examples.

(3) Outline of Each Model The first logic circuit operation model 50 is generated with the logic circuit RTL model 100 and the external operation model 110 as inputs. Therefore, first, the logic circuit RTL model 100 and the external operation model 110 will be described using specific circuits as examples. In addition, the constraint model 120 will also be described.

  In the following description, an 8-bit counter circuit with asynchronous reset is taken as an example of a logic circuit (a part corresponding to the large-scale logic circuit 200 in FIG. 1).

  FIG. 4 shows the configuration of an 8-bit counter circuit 101 with asynchronous reset (hereinafter simply referred to as counter circuit 101). The counter circuit 101 is connected to a bus, and has WRIO (write instruction), RDIO (read instruction), CS (chip select), AB (address bus), and IOBUSI (bus input data) as the bus input 102. is doing. The bus output 103 has IOBUSO (bus output data).

  The counter circuit 101 includes logic circuits A, B, and C, and includes an IOBUSO register, a CONTROL register, a COUNT register, and the like as registers.

  The basic operation of the counter circuit 101 is that when the RESET signal is H (“1”), the counter circuit 101 sequentially counts up at the rising edge of the CLK signal, and resets to zero when the RESET signal falls to L (“0”). It's simple.

  When RDIO (read instruction) is input to the counter circuit 101 via the bus, the value of the COUNT register in which the count value is stored or the data of the internal state is stored according to the value of AB (address bus) at that time. One of the stored CONTROL register values is output.

  The configuration and operation of FIG. 4 are described as the logic circuit RTL model 100.

  FIG. 5 is a diagram showing the timing relationship between the bus input 102, the bus output 103, and the CLK signal and the RESET signal input / output to / from the counter circuit 101.

  “Data” shown at the top of FIG. 5 is data exchanged with an external system (a portion corresponding to the logic circuit 210 or the microprocessor 220 in FIG. 1) via the bus.

  The timing relationship shown in FIG. 5 is described as the external operation model 110 as described later.

  FIG. 6 shows the constraints determined from the verification purpose and the like on the same timing diagram as FIG. As the first constraint (constraint 1), at time 0, the CLK signal is “0”, the RESET signal is “H”, the WRIO (write instruction) is “L”, and the other signals are “undefined”. ".

  In the first constraint (constraint 1), the category of “determined” or “undefined” depends on the system specifications, but the more the range that can be “determined”, the more the first logic circuit operation model 50 to the second It is possible to increase the scale of the reduction conversion to the logic circuit operation model 60, and as a result, the verification time (simulation time) is shortened.

  As a second constraint (constraint 2), the observation time and the target of the observation signal are defined. In this example, the observation time is only time 0 and time 3, and the observation signal targets are all signals (points indicated by asterisks in FIG. 6) except the CLK signal and the RESET signal. is doing.

  The time is defined immediately before the rising edge of the CLK signal, and the time advances at every rising edge of the CLK signal.

  By limiting (constraining) the range of observation time and the observation signal according to the verification purpose, the verification time (simulation time) is shortened. However, the shortening of the verification time (simulation time) is realized by partially extracting the CLK signal, and the accuracy of each observation time maintains the accuracy of the CLK signal. The constraints shown in FIG. 6 are described in the constraint model 120.

  In the example shown in FIG. 6, both the specification of the time required for verification and the specification of the components on the logic circuit are specified, but only one of them may be specified.

  FIG. 7 shows a logic circuit RTL model 100 in which the counter circuit 101 shown in FIG. 4 is described in a hardware description language. Verilog-HDL is used as the hardware description language. The description level is a level at which logic synthesis is possible, that is, a register transfer level (RTL).

  The logic circuit RTL model 100 of this example is mainly composed of five blocks. The block 0 is a part defining input / output ports (bus input 102, bus output 103) and internal registers of the counter circuit 101.

  Block 1 describes the operation of outputting the value of the internal register to the bus output 103 (IOBUSO). Block 2 describes operations related to setting / updating of internal registers.

  Block 3 and block 4 describe the operation of actually counting up the counter at the rising edge of the CLK signal.

  FIG. 8 shows only the description part of block 1 extracted from FIG.

  The first line is a comment sentence. The second line is called an always statement, which means that if any register value in the parentheses changes, always execute the processing below the always statement.

  The third and subsequent lines show an assignment instruction to the “IOBUSO” register and a condition (logical condition based on the value of the internal register).

  Specifically, when CS = 1, RDIO = 1, WRIO = 0, and AB = 8 (hexa), substitute the contents of the “CONTROL” L register into the “IOBUSO” register, and CS = 1, RDIO = 1. When WRIO = 0 and AB = A (hexa), assign the contents of the “COUNT” register to the “IOBUSO” register; otherwise, “Z (hexa)” (high impedance) This means the process of setting (meaning).

  FIG. 9 describes the timing diagram of each signal shown in FIG. 5 as the external operation model 110. The external operation model 110 is also described in Verilog-HDL.

  In FIG. 9, the symbol “#” means delay, for example, “# 10” means that the time is delayed by 10 units. Therefore, from the 7th line to the 20th line, the clock operation of rising (CLK = 1) and falling (CLK = 0) the CLK signal every 10 time units is described. In addition, the rise and fall timings of CS and RDIO are also described corresponding to FIG.

(4) Generation of first logic circuit operation model 50 (step 1)
As a first step of generating the first logic circuit operation model 50, a model described in Verilog-HDL is converted into a model described in “graph”.

  In general, according to graph theory or the like, a “graph” and an adjacency matrix or an edge list can be converted into each other. Therefore, the first logic circuit operation model 50 may be generated in the form of an adjacency matrix or an edge list.

  In the following description, a case where the first logic circuit operation model 50 is converted into a model described by “graph” will be described as an example.

  FIG. 11 is obtained by converting the block 1 portion (the portion corresponding to FIG. 8) of the counter circuit 101 described in Verilog-HDL into a “graph” description.

  The first logic circuit operation model 50 described in the “graph” (hereinafter simply referred to as the first logic circuit operation model 50) is composed of a plurality of types of nodes and arrows (branches) connecting the nodes. .

  A node is a box-like node (reference numeral 301 or the like) including instructions (“wait”, “load”, “store”, “equal”, “select”, etc.) indicating a procedure, and a value ( r03, etc.), octagonal nodes (symbol 303, etc.), time variables (c0001, etc.), branching state round nodes (symbol 302, etc.), and the like. Further, the box-like node includes variables (“CONTROL”, “COUNT”, “CS”, “AB”, “RDIO”, etc.) representing the storage location including the register.

  The graph description in FIG. 11 uniquely corresponds to the description in Verilog-HDL in FIG.

  For example, the procedure indicated by reference numeral 301 is to wait until the contents of the registers “CONTROL”, “COUNT”, “CS”, “AB”, “RDIO”, and “WRIO” change. This corresponds to the always statement on the second line. When the contents of each register change, the value stored in each register is read (processing in the range indicated by A in FIG. 11).

  Next, logical operation is performed from the contents of each register of “CS”, “AB”, “RDIO”, “WRIO”, and the condition of the if statement (3rd line, 5th line) in FIG. 8 is determined. (Processing in the range indicated by B in FIG. 11). Depending on the determined condition, one of “CONTROL”, “COUNT”, and “z (hexa)” is selected by the procedure of reference numeral 306. The selected value is written into the “IOBUSO” register by the procedure indicated by reference numeral 307.

  A series of processing from reference numeral 301 to reference numeral 308 is repeated for each clock. This repetition is performed in the form of tail recursion by a call statement of reference numeral 309.

  The processing of block 2 to block 3 is similarly converted to a “graph” description. Similarly, the external operation model 110 (FIG. 9) described in Verilog-HDL is also converted into a “graph” description.

  FIG. 12 is a diagram called a call graph, which expresses a procedure for calling and integrating the blocks 1 to 4 of the logic circuit RTL model 100 described in “graph” and the external operation model 110.

  In the call graph, integration between blocks is performed and development in the time axis direction is performed. All of the blocks from block 1 to block 4 are repeatedly executed at every clock with the always statement. Therefore, the integration of blocks by the call graph is developed by duplicating each block for each clock and sequentially coupling in the time axis direction.

  Expansion in the time axis direction is expanded up to the observation time range described by the constraint model 120. In this example, as shown in FIG. 6, time 0 and time 3 are defined as observation times. Therefore, it is sufficient to expand to the range of 3 clocks between time 0 and time 3.

  As described above, by expanding the processing of each block in the time axis direction, it is possible to accurately and uniquely represent the internal state (change in the value of a register or the like) that changes every clock.

  On the other hand, by defining the observation time with the constraint model 120, the development in the time axis direction can be limited to the minimum range required for verification.

  FIG. 13 is a diagram showing the first logic circuit operation model 50 in the final form integrated according to the call graph. In FIG. 13, the external operation model 110 and the processing of block 1 to block 4 expanded in the time axis direction within a range of 3 clocks are described as “graph”.

  The line marked “Waiting for writing” corresponds to waiting for the data to be written to the register at every clock and changing its contents before proceeding to the next processing (waiting for writing).

(5) Generation of evaluation symbol table (step 2)
Next, at each node of the integrated first logic circuit operation model 50 in the final form, an “evaluation symbol” is obtained based on a predetermined symbol evaluation rule and constraint model 120, and each node and “evaluation” are determined. An evaluation symbol table in which “symbols” are associated is generated.

  Here, the symbol evaluation rule is a general rule such as an arithmetic operation rule or a logical operation rule, or a rule such that “a value read when the time is unknown (undefined) is undefined”. The “evaluation symbol” refers to a constant or an indefinite value.

  This will be described with reference to the examples of FIGS.

  The procedure denoted by reference numeral 401 in FIG. 14 indicates a procedure for reading the CLK signal at time 0 (c0000). Reference numerals 402 and 403 denote procedures for reading the RESET signal at time 0 (c0000).

  In the constraint model 120 (see FIG. 6), at time 0, CLK = 0 and RESET = 1 are defined. Therefore, the value of the read CLK is fixed to 0 (constant) (CLK = 0). Therefore, a constant “0” is assigned to r01_14 as an evaluation symbol and written to the evaluation symbol table.

  Similarly, since RESET at time 0 is fixed to 1 (constant), r02_14 assigns a constant “1” as an evaluation symbol and writes it to the evaluation symbol table.

  On the other hand, since the read time of the CLK value read at 408 is unknown (depending on the time at which the asynchronous RESET signal is set to 0 by the wait instruction at 403), the time is unknown (indeterminate ), The evaluation symbol is “undefined”.

  In addition, the reference numeral 406 and the reference numeral 407 are both logical operations between constants, and the result is uniquely determined as a constant. As shown in FIG. 14, that is, 1 (constant) is assigned to r05_14 and 1 (constant) is assigned to r07_14 as evaluation symbols.

  In this way, evaluation symbols are obtained for the evaluation target variables at the respective nodes of the integrated first logic circuit operation model 50 in the final form, and an evaluation symbol table as illustrated in FIG. 15 is generated. it can.

  In the above description, constants and indefinite values are treated as evaluation symbols, and combinations of these are obtained as evaluation symbols based on symbol evaluation rules such as arithmetic operations and logical operations.

  In addition to constant and indefinite value evaluation symbols, at least one of a primary expression, a range expression, and a logical expression is treated as an evaluation symbol, and a combination of these is obtained as an evaluation symbol based on a symbol evaluation rule. Good.

(6) Reduction conversion determination for the first logic circuit operation model 50 (step ST3)
In step ST3, with reference to the symbol evaluation rule, for each predetermined reduction conversion method, a portion that is likely to be reduced conversion is detected in the first logic circuit operation model 50, and whether or not reduction conversion is actually possible is performed. It will be determined.

  In the present embodiment, four types of reduction conversion are performed: short-circuit between a read instruction and a write instruction, short-circuit between a write wait instruction and a write instruction, convolution of a constant value, and removal of a fixed conditional branch instruction.

  FIG. 16 is a diagram illustrating possibility determination regarding a short circuit between a read instruction and a write instruction. The object of this determination is a read command (load command). As a determination criterion, a write command for writing to the same register as the register read by the target read command exists unconditionally and in the latest past of the target read command. It is determined that a read command and a write command that satisfy this criterion can be short-circuited.

  If the target register is the same and there is an unconditional read command and a write command is present immediately, even if they are short-circuited, the observation space-time (observation time and observation target point) is not affected. Therefore, the first logic circuit operation model 50 can be reduced and converted (short-circuited) without deteriorating the verification accuracy.

  In the example of FIG. 16, the read instruction (load: 60) to be determined is an instruction for reading the contents of the “RUN” register. The read command (load: 60) and the write command (store: 514) are directed to the same register, that is, the “RUN” register, and the write command (store: 514) is the same as the read command (load: 60). It meets the conditions of the condition and the latest past. As a result, it is determined that the read command (load: 60) and the write command (store: 514) can be short-circuited.

  FIG. 17 is a diagram illustrating a possibility determination regarding a short circuit between a write wait instruction (wait instruction) and a write instruction (store instruction). The object of this determination is a write wait instruction (wait instruction). The write wait instruction (wait instruction) monitors the contents of one or more target registers and continues to wait as long as the contents of the target register do not change. It is an instruction.

  The criterion for determining whether or not the write wait instruction and the write instruction are short-circuited is the case where the target register is the same, and the write instruction is unconditionally in the immediate future with respect to the target write wait instruction. Also in this case, even if the write wait command and the write command are short-circuited, the observation time space is not affected. Therefore, the first logic circuit operation model 50 can be reduced and converted (short-circuited) without deteriorating the verification accuracy.

  In the example of FIG. 17, the write wait instruction (wait: 129) to be determined is writing to the “CS”, “RDIO”, “WRIO”, “AB”, “CONTROL”, and “COUNT” registers. Waiting for the presence or absence. Therefore, a write instruction (store instruction) for any of the registers “CS”, “RDIO”, “WRIO”, “AB”, “CONTROL”, and “COUNT” is searched. In the example of FIG. 17, store: 518 is an instruction for writing the value r05_13 into the “COUNT” register, and store: 516 is an instruction for writing the value r04_13 into the “CONTROL” register. Therefore, these write commands are short-circuit candidates. Next, it is determined by following the path indicated by the arrow (branch) whether or not these write commands that are short-circuit candidates are located in the unconditional and most recent future of the write wait command (wait: 129). If it is determined that it is unconditionally located in the immediate future, it is determined that the write command and the write wait command can be short-circuited.

  FIG. 18 is a diagram illustrating constant convolution.

  In step ST2, an evaluation symbol is obtained for each node of the logic circuit RTL model 100. If the evaluation symbols are all constants in the predetermined area, the result of the procedure between the constants is also a constant. Therefore, it is possible to represent all the procedures in the area collectively as one or a plurality of constants. This process is called constant convolution.

  In FIG. 18, the area surrounded by a solid line is configured with a plurality of logical operation instructions and their input and output variables as nodes, but the evaluation symbols for all variables are constants based on the conditions of the constraint model 120 and the like. It is said that there is.

  As a result, the area surrounded by the solid line can be finally folded into one constant. Even if the constants in the area surrounded by the solid line are convolved, the observation space-time is not affected. Therefore, the first logic circuit operation model 50 can be reduced and converted (short-circuited) without deteriorating the verification accuracy.

  FIG. 19 is a diagram for explaining the removal of a branch instruction (branch instruction) with a determined branch condition. When the evaluation symbol of the variable indicating the branch condition of the branch instruction is a constant, the branch destination of the branch instruction is uniquely determined. Therefore, in this case, even if the branch instruction is removed and the procedure immediately before the branch instruction and the procedure immediately after the branch instruction are directly short-circuited, the observation space-time is not affected and the verification accuracy is not degraded. One logic circuit operation model 50 can be reduced and converted (short-circuited).

  In the example of FIG. 19, the evaluation symbol of the variable r11_14 that determines the condition of the branch instruction branch: 87 is evaluated as a constant. As a result, the branch instruction branch 87 can be removed.

(7) Execution of reduction conversion (step ST5)
In step ST5, the reduction conversion is actually performed on the part determined to be reduction conversion in step ST3. Specifically, four types of reduction conversion are performed: a short-circuit between a read instruction and a write instruction, a short-circuit between a write wait instruction and a write instruction, convolution of a constant value, and removal of a fixed conditional branch instruction. It also removes descriptions that are no longer needed due to short circuits, convolutions, etc.

  FIG. 20 shows the first logic circuit operation model 50 (the model described in the graph shown in FIG. 13: before the reduction conversion) and the model after the reduction conversion, that is, the second logic circuit operation model 60. .

  The description before the reduction conversion is described with the accuracy of the clock cycle and includes 337 instructions. On the other hand, the description after the reduction conversion is described with the accuracy at the transaction level, that is, the accuracy at the timing of the external read instruction via the bus, and the total number of instructions is 134. Has been reduced to

  In the second logic circuit operation model 60 after the reduction conversion, 60.3% of instructions are removed from the first logic circuit operation model 50 before the reduction conversion.

  Verification by simulation or the like is performed based on the second logic circuit operation model 60 subjected to reduction conversion. In general, it is shown that the execution time of simulation or the like has a strong correlation with the number of instructions included in the model. Therefore, it is possible to shorten the simulation time by reducing the number of instructions.

(8) Analysis Result Report FIG. 21 is a diagram illustrating a report example of an analysis result for the second logic circuit operation model 60 subjected to the reduction conversion.

  It is reported that there is no short circuit candidate for three read instructions (load: 213, load: 96, load: 716). For each read instruction, there was no write instruction that writes values to the "COUNT" register, "CONTROL" register, and "RUN_next" register, or even if it existed, it did not exist unconditionally in the last past It means that.

  A large number of branches come out from the node indicated by the variable r03_13. This indicates that a large number of variables r03_13 are referenced and the influence range is wide. The variable r03_13 is a value obtained by reading the value of the “RUN_next” register.

  The reason why the three read instructions are “no short-circuit candidates” and the variable r03_13 remains with a wide influence range is that the external operation model 110 is used for the “COUNT” register, the “CONTROL” register, and the “RUN_next” register. The constraint model 120 does not specifically define each of these registers, and this is because the value of each register is treated as an indefinite value.

  The model creator who has received this analysis result report, for example, confirms that the value of the “RUN_next” register is guaranteed to be 0 (constant) by some method, and checks the constraint model 120 with “RUN_next” at time 0. By adding a description that the value of the register is 0 (constant), the range that can be reduced and converted can be increased. As a result, the scale of the second logic circuit operation model 60 can be further reduced and converted.

  According to the logic circuit behavior model generation device 1 and the logic circuit behavior model generation method according to the present embodiment, the temporal accuracy (observation time) and spatial accuracy (range of registers to be observed) defined by the constraint model 120. Is reduced and converted to keep it consistent. As a result, the accuracy of the generated second logic circuit operation model 60 is guaranteed not to deteriorate the accuracy of the first logic circuit operation model 50 describing the contents of the internal register for each clock.

  Further, according to the logic circuit operation model generation device 1 and the logic circuit operation model generation method according to the present embodiment, the second logic circuit operation is performed in a form in which the temporal accuracy and the spatial accuracy specified by the constraint model 120 are guaranteed. Reduction conversion to the model 60 is performed. In the specific example of the counter circuit 101, the number of instructions is reduced from 337 to 134. As a result, it is possible to greatly shorten the simulation time in the reduced model.

  Furthermore, the generation of the second logic circuit operation model 60 can be automatically generated only from the logic circuit RTL model 100, the external operation model 110, and the constraint model 120.

  As a result, when the logic circuit RTL model 100 already exists, knowledge of the detailed structure and internal state of the logic circuit RTL model 100 that is generally large in scale is obtained by the model creator (the second logic circuit operation model 60). Even if the creator does not know, if there is knowledge about the external operation and knowledge necessary for verification, the external operation model 110 and the constraint model 120 are generated to automatically generate the second logic circuit operation model 60. Is generated.

  For this reason, the man-hour concerning the production | generation of the 2nd logic circuit operation | movement model 60 can be reduced significantly.

  Furthermore, according to the logic circuit operation model generation device 1 and the logic circuit operation model generation method according to the present embodiment, by adding a description to the constraint model 120 or the like, a more efficient logic can be obtained from a previously created logic circuit operation model. A circuit behavior model can be generated. For this reason, past improvement results can be used in a stacked manner, and the time for improvement can be reduced.

  In the analysis result report, the area with a wide influence range is clearly indicated. Therefore, it is also possible to check with a logic circuit designer whether or not the condition that has been indefinite can be specifically specified, for example, in a priority order from the one having a wide influence range. In this way, the number of man-hours required for investigation for specifying conditions can be reduced.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, the constituent elements over different embodiments may be appropriately combined.

The figure explaining the positioning of the logic circuit operation model generation device and the logic circuit operation model generation method according to the present invention. The figure which shows the structural example of embodiment of the logic circuit operation | movement model production | generation apparatus which concerns on this invention. The flowchart which shows the flow of a basic process of the logic circuit operation | movement model generation method which concerns on this invention. The block diagram as a specific example for demonstrating a logic circuit RTL model. The timing chart as a specific example for demonstrating an external operation model. The figure which shows the specific example explaining a constraint model. The 1st figure which shows the specific example of the logic circuit RTL model described by Verilog-HDL. The 2nd figure which shows the specific example of the logic circuit RTL model described by Verilog-HDL. The figure which shows the specific example of the external operation model described by Verilog-HDL. The figure which shows the specific example which described the constraint model. The figure which shows the specific example of the logic circuit RTL model described with the graph. The figure which shows the specific example of a call graph. The figure which shows the specific example of the integrated 1st logic circuit operation | movement model. The figure which shows an example of the production | generation method of an evaluation symbol. The figure which shows an example of the evaluation symbol table produced | generated. The figure which shows an example of the short circuit determination of a read command and a write command. The figure which shows an example of the short circuit determination of a write wait command and a write command. The figure which shows an example of the convolution determination of a constant. The figure which shows an example of the branch instruction deletion determination of the defined conditions. The figure which shows an example of the logic circuit operation | movement model before reduction conversion, and the logic circuit operation | movement model after reduction conversion. The figure which shows an example of an analysis result report.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Logic circuit operation model production | generation apparatus 2 Production | generation part 3 Conversion part 30 Symbol evaluation part 31 Reduction | contraction conversion determination part 32 Update part 50 1st logic circuit operation model 60 2nd logic circuit operation model 70 Analysis result 100 Logic circuit RTL model 110 External motion model 120 Constraint model

Claims (30)

The logic circuit RTL model describing the operation of the logic circuit at the register transfer level and the external operation model including the description of the input / output operation for the logic circuit RTL model are integrated, and the operation of the logic circuit and the external connected to the logic circuit RTL model are integrated. A generating unit that generates a first logic circuit operation model that integrally describes the operation of the device;
A constraint model in which verification accuracy according to the verification purpose is described is input, and the scale of the first logic circuit operation model is reduced and converted within a range in which the verification accuracy is guaranteed based on the constraint model, and the second logic A conversion unit for generating a circuit operation model,
The generator is
An instruction representing a procedure, a variable representing a value used or generated by the instruction, a variable representing a time and a branch state, and a variable representing a storage location of a storage element including a register, and the use of the instruction and each of the variables It is described by a first logic circuit operation model that can describe a graph having branches as arrows connecting the nodes so as to indicate a relation or substitution relation, or an adjacency matrix or an edge list that can be mutually converted with the graph. Generating a first logic circuit operation model;
A logic circuit operation model generation device characterized by the above. The converter is
A symbol evaluation unit for obtaining an evaluation symbol in the node according to the constraint model and a predetermined symbol evaluation rule, and generating an evaluation symbol table in which the node and the evaluation symbol are associated;
With reference to the evaluation symbol table at the node, it is determined whether or not reduction conversion is possible based on a reduction conversion determination standard defined for each predetermined reduction conversion method, and when it is determined that reduction conversion is possible, A reduction conversion determination unit that generates a reduction conversion table in which the nodes determined to be reduction conversion capable of being associated with the reduction conversion method;
An updating unit for performing reduction conversion from the first logic circuit operation model to the second logic circuit operation model based on the reduction conversion table;
The logic circuit operation model generation device according to claim 1, further comprising: The constraint model is a model including a description for specifying a time required for verification,
The conversion unit generates the second logic circuit operation model so that the time accuracy required for the verification is equivalent to the time accuracy obtained by the first logic circuit operation model. The logic circuit operation model generation device according to claim 1, wherein The constraint model is a model including a description for specifying a component on a logic circuit necessary for verification,
2. The logic according to claim 1, wherein the conversion unit generates the second logic circuit operation model by performing reduction conversion so as to retain a range of components on the logic circuit necessary for the verification. Circuit behavior model generation device. The constraint model is a model including a description for specifying a time required for verification and a description for specifying a component on a logic circuit required for verification,
The conversion unit is a component on the logic circuit required for the verification so that the accuracy of the time required for the verification is equivalent to the time accuracy obtained by the first logic circuit operation model. 2. The logic circuit operation model generation device according to claim 1, wherein the second logic circuit operation model is generated by performing reduction conversion so as to maintain the range of the second logic circuit operation model. 3. The logic circuit operation model according to claim 2, wherein the symbol evaluation unit treats the evaluation symbol including a constant and an indefinite value as the evaluation symbol, and obtains the evaluation symbol based on a symbol evaluation rule for a combination thereof. Generator. The symbol evaluation unit treats at least one of a primary expression, a range expression, and a logical expression as the evaluation symbol, and further determines the evaluation symbol based on a symbol evaluation rule for a combination thereof. The logic circuit operation model generation device described in 1. The reduction conversion determination unit
When there is a read command and a write command,
Decrease conversion determination that the memory location where the read command is read and the memory location where the write command is written are the same, and that the write command is executed unconditionally in the last past when the read command is executed As a reference,
Shortening the read command and the write command when the reduced conversion determination criterion is satisfied is a reduced conversion method,
The logic circuit operation model generation device according to claim 2, wherein The reduction conversion determination unit
When there are a write wait command and a write command,
The storage location referred to by the write wait instruction is the same as the storage location written by the write command, and when the write wait command is executed, the write command is executed unconditionally in the immediate future. Use the reduced conversion criteria,
When the reduction conversion determination criterion is satisfied, the reduction conversion method is to short-circuit the write wait instruction and the write instruction.
The logic circuit operation model generation device according to claim 2, wherein The reduction conversion determination unit
If there is an instruction that generates a value,
The criterion that the value generated by the instruction is a constant value is the reduction conversion criterion,
When the reduction conversion determination criterion is satisfied, a reduction conversion method is to delete an instruction that generates the value.
The logic circuit operation model generation device according to claim 2, wherein The reduction conversion determination unit
If there is a conditional branch instruction,
The reduction conversion criterion is that the value that determines the branch destination is a constant value,
When the reduced conversion determination criterion is satisfied, the reduced conversion method is to short-circuit the instruction immediately before the conditional branch instruction and the instruction immediately after the branch destination.
The logic circuit operation model generation device according to claim 2, wherein When the conversion unit is instructed to interrupt the reduction conversion, the conversion unit generates an already reduced-conversion range that satisfies the constraint model as the second logic circuit operation model even if the instructed time point is in the middle of the reduction conversion. The logic circuit operation model generation device according to claim 1, wherein: The converter is
2. The logic circuit operation model generation device according to claim 1, wherein when there is a part that cannot be determined whether or not reduction conversion is possible and is unclear, the part and the reason are output as an analysis result. The converter is
14. The logic circuit operation model according to claim 13, wherein if further reduction conversion is performed on the second logic circuit operation model, information indicating a range that may be affected is further output. Generator. The converter is
2. The logic circuit operation model generation apparatus according to claim 1, wherein a modified constraint model is input to further reduce and convert the second logic circuit operation model, and the reduction conversion process is resumed. 3. The logic circuit RTL model describing the operation of the logic circuit at the register transfer level and the external operation model including the description of the input / output operation for the logic circuit RTL model are integrated, and the operation of the logic circuit and the external connected to the logic circuit RTL model are integrated. A generation step for generating a first logic circuit operation model that integrally describes the operation of the device;
A constraint model in which verification accuracy according to the verification purpose is described is input, and the scale of the first logic circuit operation model is reduced and converted within a range in which the verification accuracy is guaranteed based on the constraint model, and the second logic A conversion step for generating a circuit behavior model,
The generating step includes
An instruction representing a procedure, a variable representing a value used or generated by the instruction, a variable representing a time and a branch state, and a variable representing a storage location of a storage element including a register, and the use of the instruction and each of the variables It is described by a first logic circuit operation model that can describe a graph having branches as arrows connecting the nodes so as to indicate a relation or substitution relation, or an adjacency matrix or an edge list that can be mutually converted with the graph. Generating a first logic circuit operation model;
A logic circuit operation model generation method characterized by the above. The converting step includes
A symbol evaluation step for obtaining an evaluation symbol in the node according to the constraint model and a predetermined symbol evaluation rule, and generating an evaluation symbol table in which the node and the evaluation symbol are associated;
With reference to the evaluation symbol table at the node, it is determined whether or not reduction conversion is possible based on a reduction conversion determination standard defined for each predetermined reduction conversion method, and when it is determined that reduction conversion is possible, A reduction conversion determination step for generating a reduction conversion table in which the nodes determined to be reduction conversion capable of being associated with the reduction conversion method;
An update step for reducing and converting from the first logic circuit operation model to the second logic circuit operation model based on the reduction conversion table;
The logic circuit operation model generation method according to claim 16, further comprising: The constraint model is a model including a description for specifying a time required for verification,
The converting step generates the second logic circuit operation model so that the time accuracy required for the verification is equivalent to the time accuracy obtained by the first logic circuit operation model. The logic circuit operation model generation method according to claim 16, wherein: The constraint model is a model including a description for specifying a component on a logic circuit necessary for verification,
17. The logic according to claim 16, wherein the converting step generates the second logic circuit operation model by performing a reduction conversion so as to retain a range of components on the logic circuit necessary for the verification. Circuit operation model generation method. The constraint model is a model including a description for specifying a time required for verification and a description for specifying a component on a logic circuit required for verification,
The conversion step includes a component on the logic circuit necessary for the verification so that the accuracy of the time required for the verification is equivalent to the time accuracy obtained by the first logic circuit operation model. 17. The logic circuit operation model generation method according to claim 16, wherein the second logic circuit operation model is generated by performing reduction conversion so as to maintain the range of 18. The logic circuit operation model according to claim 17, wherein the symbol evaluation step treats the evaluation symbol including a constant and an indefinite value as the evaluation symbol, and obtains the evaluation symbol based on a symbol evaluation rule for a combination thereof. Generation method. The symbol evaluation step treats at least one of a primary expression, a range expression, and a logical expression as the evaluation symbol, and further determines the evaluation symbol based on a symbol evaluation rule for a combination thereof. 2. A logic circuit operation model generation method described in 1. The reduction conversion determination step includes:
When there is a read command and a write command,
Decrease conversion determination that the memory location where the read command is read and the memory location where the write command is written are the same, and that the write command is executed unconditionally in the last past when the read command is executed As a reference,
Shortening the read command and the write command when the reduced conversion determination criterion is satisfied is a reduced conversion method,
The logic circuit operation model generation method according to claim 17. The reduction conversion determination step includes:
When there are a write wait command and a write command,
The storage location referred to by the write wait instruction is the same as the storage location written by the write command, and when the write wait command is executed, the write command is executed unconditionally in the immediate future. Use the reduced conversion criteria,
When the reduction conversion determination criterion is satisfied, the reduction conversion method is to short-circuit the write wait instruction and the write instruction.
The logic circuit operation model generation method according to claim 17. The reduction conversion determination step includes:
If there is an instruction that generates a value,
The criterion that the value generated by the instruction is a constant value is the reduction conversion criterion,
When the reduction conversion determination criterion is satisfied, a reduction conversion method is to delete an instruction that generates the value.
The logic circuit operation model generation method according to claim 17. The reduction conversion determination step includes:
If there is a conditional branch instruction,
The reduction conversion criterion is that the value that determines the branch destination is a constant value,
When the reduced conversion determination criterion is satisfied, the reduced conversion method is to short-circuit the instruction immediately before the conditional branch instruction and the instruction immediately after the branch destination.
The logic circuit operation model generation method according to claim 17. The converting step includes
When instructed to interrupt the reduction conversion, the already reduced-converted range that satisfies the constraint model is generated as the second logic circuit operation model even if the instructed time is in the middle of the reduction conversion. The logic circuit operation model generation method according to claim 16. The converting step includes
17. The logic circuit operation model generation method according to claim 16, wherein when there is a part that cannot be determined whether or not reduction conversion is possible and is unclear, the part and the reason are output as an analysis result. The converting step includes
29. The logic circuit operation model according to claim 28, further outputting information indicating a range that may be affected if further reduction conversion is performed on the second logic circuit operation model. Generation method. The converting step includes
17. The logic circuit operation model generation method according to claim 16, wherein a modified constraint model is input to further reduce and convert the second logic circuit operation model, and the reduction conversion process is resumed.

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