JP2007193416A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To precisely perform pulse output even when a request for immediate pulse output is made. <P>SOLUTION: A microcomputer (1) is provided with a timer (2) and a CPU (3) for controlling the timer. The timer is provided with a counter (10), a comparison register (11), a forced comparison match control circuit (12), a comparator circuit (13) and an output control circuit (14). The counter counts a clock signal. The comparison register is made accessible by the CPU, and configured to store a prescribed value. The comparison circuit compares the counter value of the counter with the set value of the register. When a forced comparison match request flag FG is set by the CPU, the forced comparison match control circuit loads the counter value of the counter to a comparison register, and makes the comparator circuit output a matching signal (17) for operating the edge change of a timer output signal. The output control circuit operates the edge change of a timer output signal (20) according to the matching signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit provided with a timer, and relates to a technique that is effective when applied to an engine control microcomputer such as an automobile.

  For example, a microcomputer for engine control outputs a pulse signal generated by a timer to an injector that injects fuel into an intake pipe or a combustion chamber of the engine to perform engine control. A conventional timer includes a counter, a compare register, a comparison circuit, and an output control circuit. The comparison circuit compares the counter value of the counter with the set value of the compare register, and if these values match (hereinafter referred to as a compare match), it generates a match signal and outputs it to the output control circuit. The output control circuit can be set by the central processing unit (CPU) of the microcomputer. For example, the output signal is changed from the low level to the high level at the first compare match, and is changed from the high level to the low level at the next compare match. By setting so as to cause the edge to change, the edge can be changed according to the coincidence signal.

  The compare register can be set by the CPU, and a value corresponding to the time until the first compare match occurs is set. After the first compare match occurs, the time until the next compare match occurs, that is, A value obtained by adding a value corresponding to the pulse width is set. In this way, a microcomputer equipped with a conventional timer can output a pulse signal having a predetermined pulse width at a predetermined timing. Patent Document 1 describes a PWM (Pulse Width Modulation) pulse generator that includes a compare match register that compares the contents of a counter and a timing register and outputs a signal when they match. This PWM pulse generator generates a predetermined pulse pattern according to the output signal of the compare match register.

JP-A-8-19264

  The present inventor has considered a means for efficiently performing pulse output when, for example, the driver depresses the accelerator and a quick pulse output is requested to the injector after the time until the compare match occurs is set. did. In a microcomputer equipped with a conventional timer, the CPU reads the counter value when an immediate pulse output is requested from the timer, adds “2” to the read counter value, and writes the addition result to the compare register. Process. The reason for adding “2” to the read counter value is, for example, if only “1” is added, the counter is counted up before the above processing of the CPU ends, and the counter value exceeds the set value of the compare register. This is because there is a possibility that it will end up. In this case, a compare match cannot be generated until the counter overflows and counts up again from zero.

  As described above, in the microcomputer, the CPU needs to perform the above processing in response to a request for an urgent pulse output that cannot be predicted when it occurs. Therefore, the CPU must wait until a compare match occurs. And efficiency is reduced.

  A timer with a forced compare match control circuit that forcibly generates a compare match and outputs a match signal from the comparison circuit when there is an immediate pulse output request for such a conventional timer. Are known. In a microcomputer equipped with this timer, the CPU does not need to perform the above processing when changing the edge of the output signal from a low level to a high level in response to an immediate request for pulse output. There is no decline.

  Then, after a compare match is generated by the forced compare match control circuit and a match signal is output from the comparison circuit, the CPU reads the counter value from the counter, adds a value corresponding to the pulse width to the read counter value, Processing to write the addition result to the compare register is performed. However, since the CPU and the counter operate in parallel, there is a high possibility that the counter value read by the CPU does not match the counter value at the time of the compare match by the forced compare match control circuit. That is, in the counter, since the count has already passed from the time of the compare match to when it is actually accessed by the CPU, the counter value fluctuates accordingly. As a result, in the microcomputer, it is difficult to add a value corresponding to the pulse width in consideration of fluctuations in the counter value when the edge of the pulse signal is changed from the high level to the low level. In other words, in the microcomputer, in response to an immediate request for pulse output, when the output signal is changed from the high level to the low level, the accuracy of the timing to be set to the low level is lowered.

  An object of the present invention is to provide a semiconductor device capable of performing pulse output with high accuracy even when an immediate pulse output is required.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A semiconductor integrated circuit according to the present invention includes a timer (2) and a central processing unit (3) for controlling the timer. The timer includes a counter (10), a register (11), a comparison circuit (13), an output control circuit (14), and a compare match control circuit (12). The counter counts clock signals. The register is accessible by the central processing unit. The comparison circuit compares the counter value of the counter with the set value of the register. The output control circuit changes the edge of the output signal (20) according to the coincidence result of the comparison circuit. The compare match control circuit, in response to an instruction for changing the state of the output signal, loads the counter value of the counter into the register, and also matches the output signal from the comparison circuit (17) is output. The central processing unit performs control for reading a value loaded from the counter and writing an addition result obtained by adding a required value to the value to the register.

  From the above, for example, if there is an instruction to change the state of the output signal from low level to high level, the compare match control circuit forcibly generates a compare match and outputs a match signal from the comparison circuit. Edge changes can be made without imposing a burden on the processing apparatus. The counter value at the time of compare match is loaded into the register by the compare match control circuit. Therefore, the central processing unit accesses the register, not the counter, and reads the loaded counter value, thereby obtaining a required value, for example, a value corresponding to the pulse width, based on the accurate counter value. Addition can be performed and the addition result can be written to the register. This makes it possible to accurately set the timing at which the state of the output signal should be changed from the high level to the low level. Therefore, even when there is an instruction to change the state of the output signal, pulse output can be performed with high accuracy.

  [2] A semiconductor integrated circuit according to the present invention includes a timer (2A) and a central processing unit that controls the timer. The timer includes a counter, a first register (11) and a second register (26), a comparison circuit, an output control circuit, a compare match control circuit (12A), and an adder circuit (27). The counter counts clock signals. The central processing unit can access the first register and the second register. The comparison circuit compares the counter value of the counter with the set value of the first register. The output control circuit changes the edge of the output signal according to the matching result of the comparison circuit. In response to an instruction to change the state of the output signal, the compare match control circuit loads the counter value of the counter into the first register and changes the edge of the output signal from the comparison circuit. A match signal is output. In response to an instruction for changing the state of the output signal, the adder circuit inputs and adds the value loaded from the counter to the first register and the required value of the second register, The addition result is output to the first register.

  From the above, if there is an instruction for changing the state of the output signal from low level to high level, for example, the edge of the output signal can be changed without imposing a burden on the central processing unit. Furthermore, if a value corresponding to, for example, the pulse width is stored in advance as a required value in the second register, the adder circuit inputs the values of the first register and the second register, and outputs the addition result to the first register. Therefore, the processing of the central processing unit becomes unnecessary when the output signal changes from the high level to the low level. In this way, the burden on the central processing unit accompanying the edge change of the output signal can be reduced, and pulse output can be performed with high accuracy.

  As a specific form of the present invention, the instruction to change is performed by the compare match control by means of a dedicated line (21) different from the internal bus (6) to which the central processing unit and the timer are commonly connected. Input to the circuit. From the above, since the instruction for changing the state of the output signal is surely input regardless of the usage status of the internal bus, for example, when the central processing unit outputs an instruction to the compare match control circuit There is no.

  As a specific form of the present invention, the adder circuit is connected to the first register via a dedicated bus (28). As described above, the adder circuit can input / output values to / from the first register without using the central processing unit.

  [3] A semiconductor integrated circuit according to the present invention includes a central processing unit and a timer controlled by the central processing unit. The timer includes a counter, a register, an output circuit, and a control circuit. The register is accessible by the central processing unit. The output circuit determines whether the count value of the counter matches the set value of the register, and changes the edge of the output based on the match determination. In response to an instruction from the outside, the control circuit changes the edge of the output of the output circuit and loads the count value of the counter at that time into the register.

  As described above, in response to an instruction from the outside, the count value of the counter when the compare match occurs can be acquired. By using the acquired count value, the time until the next compare match, that is, a value corresponding to the pulse width can be set accurately. As a result, even when there is an instruction to change the edge of the output quickly as an instruction from the outside, for example, pulse output can be accurately performed.

  As a specific form of the present invention, the central processing unit reads a count value loaded from the counter into the register, adds a predetermined value to the read count value, and writes the read value into the register. return. From the above, the central processing unit performs processing with a predetermined value corresponding to the time until the next compare match, for example, a value corresponding to the pulse width, based on the counter value at the time of the compare match. The timing at the edge change from to low level can be set with high accuracy.

  As a specific form of the present invention, another register accessed by the central processing unit, a count value loaded from the counter to the register in response to an instruction from the outside, and the other register And an arithmetic circuit that inputs and adds the required values and outputs the addition result to the register. From the above, the edge from the high level to the low level of the output signal is reduced by reducing the burden on the central processing unit by using another register and arithmetic circuit when the output signal changes from the high level to the low level. The timing of change can be set accurately.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, even when there is a request for urgent pulse output, pulse output can be performed with high accuracy.

  FIG. 1 illustrates a schematic configuration of a microcomputer as an example of a semiconductor integrated circuit according to Embodiment 1 of the present invention. The microcomputer 1 is used, for example, in an engine control system such as an automobile, and performs engine control by outputting a pulse signal to an injector that injects fuel into an intake pipe or a combustion chamber of the engine. The microcomputer 1 includes a timer 2 and a central processing unit (CPU) 3. The CPU 3 controls all of the microcomputer 1 based on a program stored in a read only memory (ROM) 4. The ROM 4 stores programs to be executed by the CPU 3 and fixed data. A random access memory (RAM) 5 stores a calculation result by the CPU 3 and also serves as a work area for the CPU 3. The timer 2, CPU 3, ROM 4, and RAM 5 are connected to each other via an internal bus 6.

  The timer 2 is a module that generates a pulse signal and the like for controlling fuel injection by the injector, and includes a counter 10, a compare register 11, a forced compare match control circuit 12, a comparison circuit 13, and an output control circuit. 14 etc. The counter 10 has a function of counting clock signals and storing the count value (hereinafter referred to as a counter value). The counter 10 counts up the counter value, for example, in synchronization with the clock signal. The compare register 11 is accessible by the CPU 3 and is set with a predetermined set value. The comparison circuit 13 compares the counter value of the counter 10 input via the signal line 15 with the set value of the compare register 11 input via the signal line 16. The comparison circuit 13 generates coincidence signals 17 and 18 if these values coincide. That is, the coincidence signals 17 and 18 are generated when a compare match occurs. The coincidence signal 17 is output to the output control circuit 14 by the comparison circuit 13. The coincidence signal 18 is output from the comparison circuit 13 to the peripheral circuit (not shown) in the microcomputer 1 instead of the output control circuit 14 and used for various controls.

  The output control circuit 14 can be set by the CPU 3 via the internal bus 6 and the signal line 19. For example, when the coincidence signal 17 is first input by the CPU 3, the output control circuit 14 changes the state of the output signal (hereinafter referred to as a timer output signal) 20 from low level to high level, and then coincides with the coincidence signal. When 17 is input, the state of the timer output signal 20 is set in advance so as to change the edge from the high level to the low level. As a result, the output control circuit 14 changes the edge of the timer output signal 20 every time the coincidence signal 17 is input, and can generate a pulse signal.

  When the forced compare match control circuit 12 is instructed from the CPU 3 via the dedicated line 21 to quickly output a pulse, the forced compare match request flag FG is set. Thus, the forced compare match control circuit 12 performs control for forcibly generating a compare match. Here, the quick pulse output means not only that the state of the timer output signal 20 is rapidly changed from the low level to the high level but also the high level at an appropriate timing so as to have a predetermined pulse width. It also means changing the edge to low level.

  First, the case where the state of the timer output signal 20 is changed from the low level to the high level will be described. When the forced compare match request flag FG is set, the forced compare match control circuit 12 outputs control signals S1 and S2 to the counter 10 and the compare register 11 via the control lines 22 and 23, respectively. The counter value of 10 is loaded into the compare register 11 as indicated by the arrow 24 in the figure. Further, at this time, the forced compare match control circuit 12 outputs the control signal S3 to the comparison circuit 13 via the control line 25, and forcibly outputs the match signal 17 from the comparison circuit 13. Thereby, the microcomputer 1 generates a compare match immediately when the forced compare match request flag FG is set without imposing a burden on the CPU 3, and changes the state of the timer output signal 20 from low level to high level. Can be made. Hereinafter, the compare match by the forced compare match control circuit 12 is referred to as a forced compare match. The operation of changing the state of the timer output signal 20 from the high level to the low level will be described in detail later with reference to FIG.

  Here, for convenience of explanation, engine control will be schematically described. For example, a single-cylinder engine has one cylinder that accommodates a piston inside. The combustion chamber described above is a space surrounded by the upper surface of the piston and the inner wall of the cylinder, and an intake port and an exhaust port are formed on the inner wall of the cylinder. In a series of cycles including an intake process, a compression process, a combustion / expansion process, and an exhaust process of a single cylinder engine, the piston receives the gas pressure of the combustion chamber on its upper surface. The piston is linked to the crankshaft via a connecting rod. Thereby, the reciprocating motion of the piston is converted into the rotational motion of the crankshaft. In the intake process, the exhaust port is closed by the exhaust valve, the intake port is opened by the intake valve, and an air-fuel mixture composed of air or fuel injected from the injector is passed through the intake pipe connected to the intake port. Introduced into the combustion chamber. At this time, the piston moves in the direction of decreasing the pressure by increasing the volume of the combustion chamber, that is, in the downward direction. The position at which the piston has moved downward is defined as the bottom dead center. In the compression process, the intake port and the exhaust port are closed by the intake valve and the exhaust valve, respectively, the inside of the combustion chamber is airtight, and the piston moves upward, so that the volume of the combustion chamber is increased. It becomes smaller and the gas pressure becomes higher. The position at which the piston has moved upward is defined as the top dead center. Next, in the combustion / expansion step, when the position of the piston is near top dead center, the air-fuel mixture in the combustion chamber is combusted by the spark plug, and the air-fuel mixture expands. In the exhaust process, when the position of the piston approaches the bottom dead center due to the expansion of the air-fuel mixture, the exhaust port is opened by the exhaust valve. Then, again, as the position of the piston approaches top dead center, the volume of the combustion chamber decreases, so the air-fuel mixture after combustion is exhausted through the exhaust pipe connected to the exhaust port. Then, when the position of the piston reaches the top dead center again, the above intake process is started again.

  In short, the injection of fuel from the injector is required once in the intake process in one cycle consisting of the above-described processes. For this reason, in order to set the timing for performing the pulse output, for example, the top dead center or the bottom dead center of the piston in the intake process may be used as a reference. The timing at which the piston is located at the top dead center or the bottom dead center can be calculated by, for example, an appropriate sensor that detects the rotation angle of the crankshaft.

  Next, a situation where the forced compare match request flag FG is set in the engine control system will be described. In the engine control system, for example, a throttle for adjusting the flow rate of air introduced into the intake pipe is provided. The throttle changes the opening of the intake pipe according to the degree of depression of the accelerator by the driver or the like. That is, the air flow rate can be detected by the throttle opening. The engine speed can be detected by, for example, the speed of the crankshaft. In the engine control system, the optimum engine speed for the flow rate is stored in advance in a table or the like. For example, the engine speed is lower than the optimum state even though the throttle opening is increased and the flow rate is increased. If it is, it will be determined that the fuel injected from the injector is insufficient. In other words, the engine control system sets the time for injecting fuel from the injector in advance because the driver requested the acceleration by depressing the accelerator and the current engine speed cannot respond to the acceleration request. It is determined that it is necessary to advance the time until the compare match occurs. In such a situation, in the engine control system, the CPU 3 makes the above determination, outputs an instruction for promptly outputting a pulse, and sets the forced compare match request flag FG of the forced compare match control circuit 12. The period during which the injector can inject fuel is a period in which the state of the timer output signal 20 is at a high level. For this reason, in the engine control system, the CPU 3 can also calculate a value corresponding to the pulse width of the timer output signal 20 with reference to an appropriate table.

  FIG. 2 shows an example of the operation timing of the microcomputer 1. In this timing chart, the horizontal axis indicates time, and the vertical axis indicates the set value of the compare register 11, the counter value of the counter 10, the state of the coincidence signal 17, and the state of the timer output signal 20 due to forced compare match. Further, the state of the timer output signal 20 by a normal compare match is indicated by a two-dot chain line in the figure. The normal compare match means that the set value preset in the compare register 11 matches the counter value of the counter 10 without using the forced compare match control circuit 12.

  Time t0 is, for example, a timing at which the piston is located at the top dead center in the intake process. At time t0, the set value of the compare register 11 is YR, and the counter value of the counter 10 is YC, which are set as reference values. At time t0, the state of the coincidence signal 17 and the timer output signal 20 are both set to the low level. The counter value is counted up every cycle of the clock signal with YC as a reference value. The counter 10 is reset, for example, at the timing when the piston is located at the bottom dead center in the intake process. This reference value YC is, for example, zero.

  First, in a normal compare match, the set value of the compare register 11 is not forcibly changed. In the figure, the set value of the compare register 11 after time t2 is indicated by a dotted line as the same value as YR. ing. As indicated by point D, the counter value becomes the same value as YR at time t4. At this time, the state of the timer output signal 20 changes from a low level to a high level as indicated by a two-dot chain line. For this reason, the time until a normal compare match occurs is time t4.

  Next, forced compare match will be described. At time t1, the CPU 3 determines that the fuel injected from the injector is insufficient, and sets the forced compare match request flag FG of the forced compare match control circuit 12 via the dedicated line 21 different from the internal bus 6. set. Therefore, the forced compare match request flag FG is surely set regardless of the usage status of the internal bus 6. That is, the CPU 3 does not stand by when the forced compare match request flag FG of the forced compare match control circuit 12 is set. At time t2, the forced compare match control circuit 12 loads the counter value of the counter 10 into the compare register 11, thereby changing the set value of the compare register 11 from YR to the loaded counter value. That is, the forced compare match occurs at the point A. At this time, the forced compare match request flag FG is cleared. At time t2, the forced compare match control circuit 12 outputs the match signal 17 from the comparison circuit 13 to the output control circuit 14, so that the state of the match signal 17 is set to the high level. Thereby, at the time t2, the state of the timer output signal 20 changes from the low level to the high level.

  Next, an operation for changing the state of the timer output signal 20 from the high level to the low level will be described. After time t2, the CPU 3 accesses the compare register 11 via the internal bus 6 instead of the counter 10, and reads the counter value loaded from the counter 10 when a forced compare match occurs. For example, if the CPU 3 determines that the fuel injected from the injector is insufficient, the CPU 3 calculates a period during which the injector can inject fuel, that is, a value corresponding to the pulse width, and sets a value corresponding to the pulse width. The counter value loaded from the counter 10 is added, and the addition result is written to the compare register 11. The data processing of the CPU 3 is executed at the point B, and some time has already passed from the time t2. However, since the data processing of the CPU 3 uses the accurate counter value when the forced compare match occurs as a reference, if the data processing is completed by the time t3 when the next compare match is made, the timer output signal The 20 states can be changed from a high level to a low level.

  Here, an example of a value corresponding to the pulse width is shown. The value corresponding to the pulse width is equal to the counter value of the counter 10 counted up for each cycle of the clock signal after the time t2 and the set value of the compare register 11 again to generate the next compare match. It corresponds to the time until For example, when one cycle of the clock signal of the counter 10 is 100 ns and the pulse width of the timer output signal 20 is to be 1 μs, the value corresponding to the pulse width is “10”. This is because 1 μs corresponds to a time corresponding to 10 cycles of the clock signal. That is, since the counter value of the counter 10 is counted up by “10” in 1 μs, it matches the set value of the compare register 11 after 1 μs has elapsed.

  At time t3, the counter value of the counter 10 matches the set value of the compare register 11 as indicated by a point C. The counter value of the counter 10 and the set value of the compare register 11 at time t3 are input to the comparison circuit 13 via the signal lines 15 and 16, respectively. Since the comparison circuit 13 outputs the coincidence signal 17 to the output control circuit 14 at time t3, the state of the coincidence signal 17 is set to the high level. As a result, the output control circuit 14 changes the state of the timer output signal 20 from the high level to the low level at time t3 when the next compare register is generated, as previously set by the CPU 3. That is, according to the microcomputer 1, it is possible to accurately set the timing at which the state of the timer output signal 20 should be changed from the high level to the low level. Therefore, according to the microcomputer 1, even when an immediate pulse output is requested, the pulse can be output with high accuracy.

  On the other hand, as a comparative example, for example, a microcomputer that provides a pulse width setting counter in a timer and activates the pulse width setting counter and outputs a pulse when a compare match occurs can be considered. However, this microcomputer has a complicated and large-scale circuit configuration.

  FIG. 3 illustrates a schematic configuration of a microcomputer as an example of a semiconductor integrated circuit according to the second embodiment of the present invention. In the second embodiment, parts having the same functions and the like as those of the microcomputer 1 of the first embodiment described above are denoted by the same reference numerals, and portions having duplicate explanations are omitted as appropriate. The microcomputer 1A includes a timer 2A. The timer 2A includes a counter 10, a compare register 11 and a duty register 26, a comparison circuit 13, an output control circuit 14, a forced compare match control circuit 12A, and an adder circuit 27. In a normal compare match, the timer 2A performs the same operation as the timer 2.

  In the forced compare match, the timer 2A performs the same operation as the timer 2 for changing the edge of the timer output signal 20 from the low level to the high level, but the operation for changing the edge from the high level to the low level is different. For example, in the timer 2, the state of the timer output signal 20 is changed from the high level to the low level by the CPU 3 performing data processing. On the other hand, in the timer 2A, the edge of the timer output signal 20 can be changed from the high level to the low level by the duty register 26, the adder circuit 27, the forced compare match control circuit 12A, and the like.

  Specifically, when the forced compare match request flag FG is set, the forced compare match control circuit 12A sends control signals to the compare register 11, the adder circuit 27, and the duty register 26 via the control lines 23, 29, and 30, respectively. S4, S5 and S6 are output. In the duty register 26, a value corresponding to the pulse width calculated by the CPU 3 or the like is stored in advance, and a value corresponding to this pulse width can be output to the adding circuit 27 by the control signal S6. The compare register 11 can output the counter value loaded in the compare register 11 to the adder circuit 27 when the forced compare match occurs by the control signal S4. The adder circuit 27 can receive a counter value output from the compare register 11 and a value corresponding to the pulse width output from the duty register 26 by the control signal S5.

  Since the adder circuit 27 is connected to the compare register 11 and the duty register 26 via the dedicated buses 28 and 31, respectively, the counter value and the pulse width are transferred from the compare register 11 and the duty register 26 without interposing the CPU 3. A value corresponding to is input. The adding circuit 27 adds these input values and holds the addition result. The forced compare match control circuit 12A outputs the control signals S7 and S8 again via the control lines 23 and 29, and the addition circuit 27 can output the addition result to the compare register 11. Then, the adding circuit 27 outputs the addition result to the compare register 11. Therefore, according to the timer 2A, when the state of the timer output signal 20 is changed from the high level to the low level, the processing of the CPU 3 becomes unnecessary, so the burden on the CPU 3 due to the edge change of the timer output signal 20 is reduced. it can.

  Furthermore, the time required for the adder circuit 27 to input and add the respective values from the compare register 11 and the duty register 26 and to output the addition result to the compare register 11 is longer than the data processing time of the CPU 3 in the timer 2. It's short. Thereby, even if the value corresponding to the pulse width is smaller than the data processing time of the CPU 3, for example, the timer 2A can cope with it, and the accuracy of pulse output can be further improved.

  As mentioned above, although the invention made by this inventor was concretely demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to it and can be variously changed in the range which does not deviate from the summary.

  For example, although the forced compare match request flag FG of the forced compare match control circuits 12 and 12A is set by the CPU 3 via the dedicated line 21, it is not limited to this and is set by an interrupt control circuit not shown. You may do it. In this way, when the forced compare match request flag FG of the forced compare match control circuits 12 and 12A is set, for example, it is performed by interrupt control by the interrupt control circuit instead of the branch process of the CPU 3, and the load on the CPU 3 is increased. Can be further reduced. Further, since the microcomputers 1 and 1A described above have a function of outputting a pulse signal having a desired pulse width at a predetermined timing, the microcomputers 1 and 1A are not limited to the engine control system, and may be appropriately controlled such as a monitor function control system. Can be applied to the system.

1 is an explanatory diagram illustrating a schematic configuration of a microcomputer that is an example of a semiconductor integrated circuit according to a first embodiment of the invention; It is a timing chart which shows the operation timing of a microcomputer. It is explanatory drawing which illustrates schematic structure of the microcomputer which is an example of the semiconductor integrated circuit which concerns on Embodiment 2 of this invention.

Explanation of symbols

1, 1A microcomputer 2, 2A timer 3 central processing unit (CPU)
4 Read-only memory (ROM)
5 Random access memory (RAM)
6 Internal bus 10 Counter 11 Compare register 12 Forced compare match control circuit 13 Comparison circuit 17 Match signal 20 Timer output signal 21 Dedicated line 26 Duty register 27 Adder circuit 28 Dedicated bus FG Forced compare match request flag S1 to S8 Control signal

Claims (7)

A semiconductor integrated circuit comprising a timer and a central processing unit for controlling the timer,
The timer includes a counter for counting clock signals;
A register accessible to the central processing unit;
A comparison circuit for comparing the counter value of the counter with the set value of the register;
An output control circuit for changing an edge of the output signal in accordance with the result of matching of the comparison circuit;
In response to an instruction to change the state of the output signal, the counter value of the counter is loaded into the register, and a compare match control for outputting a match signal for changing the edge of the output signal from the comparison circuit A circuit,
The central processing unit is a semiconductor integrated circuit that performs control for reading a value loaded from the counter and writing an addition result obtained by adding a required value to the value to the register. A semiconductor integrated circuit comprising a timer and a central processing unit for controlling the timer,
The timer includes a counter for counting clock signals;
A first register and a second register accessible by the central processing unit;
A comparison circuit for comparing a counter value of the counter with a set value of the first register;
An output control circuit for changing an edge of the output signal in accordance with the result of matching of the comparison circuit;
In response to an instruction to change the state of the output signal, the compare value is loaded into the first register and the match signal for changing the edge of the output signal is output from the comparison circuit. A match control circuit;
In response to an instruction to change the state of the output signal, the value loaded from the counter to the first register and the required value of the second register are input and added, and the addition result is A semiconductor integrated circuit comprising: an adder circuit that outputs the first register;   3. The semiconductor integrated circuit according to claim 1, wherein the instruction for changing is input to the compare match control circuit through a dedicated line different from an internal bus to which the central processing unit and the timer are commonly connected. .   The semiconductor integrated circuit according to claim 2, wherein the adder circuit is connected to the first register via a dedicated bus. A central processing unit and a timer controlled by the central processing unit;
The timer includes a counter,
A register accessible by the central processing unit;
An output circuit that determines whether the count value of the counter matches the set value of the register, and changes the edge of the output based on the match determination;
A semiconductor integrated circuit comprising: a control circuit that changes an output of the output circuit in response to an instruction from the outside and loads a count value of the counter at that time into the register.   6. The semiconductor integrated circuit according to claim 5, wherein the central processing unit reads a count value loaded from the counter into the register, adds a predetermined value to the read count value, and writes back to the register. Another register accessed by the central processing unit;
In response to an instruction from the outside, a count value loaded from the counter to the register and a required value of the other register are input and added, and an arithmetic circuit that outputs the addition result to the register; 6. The semiconductor integrated circuit according to claim 5, further comprising:

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