JPH08162933A - Period signal generator - Google Patents

Abstract

PURPOSE: To generate the pulse width signals (period signals) of a cycle exceeding the circulation period of a counter while minimizing the processing loads of a CPU. CONSTITUTION: When a value set to a comparator 23 by the CPU 18 and the counted value of a free-running timer 24 match, the comparator 23 outputs matching signals to a pulse generation circuit 25 as trigger signals and outputs them to the CPU 18 as interruption signals. When the interruption signals are inputted, the CPU 18 sets the level of pulse signals to be outputted at the time of the input of the trigger signals at the next time to the pulse generation circuit 25 and sets the value corresponding to a time interval for outputting the matching signals next to the comparator 23. In the case of generating the pulse width signals of the cycle exceeding the circulation cycle of the free- running timer 24, the CPU 18 divides the cycle of the pulse width signals and sets the value to the comparator 23 so as to minimize the number of times of the matching signals outputted by the comparator 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention compares a counter for cyclically counting the number of pulses of a clock signal within a certain counting range with a set value and the count value of the counter, and when they match, a coincidence signal is generated. The present invention relates to a period signal generating device for generating a period signal having a predetermined cycle exceeding the circulation cycle of a counter by controlling an output comparator and a control means.

[0002]

2. Description of the Related Art A conventional signal generator for such a period is
For example, as disclosed in Japanese Patent Laid-Open No. 4-262614, the period T of the period signal to be generated is set to the unit time TZR.
T divided by the number n divided by and the remainder Trest
= N × TZR + Trest, 1 is added to the set value of the comparator every time the CPU as the control means is interrupted every unit time TZR, and when the internal counter of the CPU becomes n, it corresponds to the surplus Trest. The count value is set in the comparator, and then the coincidence signal is output from the comparator to obtain the period signal of the cycle T.

[0003]

However, in such a conventional device, it is necessary to interrupt the CPU as the control means every unit time TZR, and due to the frequently occurring interrupt processing, the CPU is interrupted. There is a problem that the function is almost exclusively occupied by the signal generation during this period.

The present invention solves the above problems, and an object thereof is to provide a period signal generator capable of generating a period signal of a predetermined period exceeding the circulation period of a counter with a minimum of interrupt processing. is there.

[0005]

In order to achieve the above object, a period signal generator according to a first aspect of the present invention includes a counter for cyclically counting the number of pulses of an input clock signal within a certain counting range, and a predetermined counter. Can be set to the value of, and the set value is compared with the count value of the counter, and a comparator that outputs a match signal when they match, and a period signal is generated based on the match signal given as an interrupt signal. When the cycle of the period signal to be generated exceeds the circulation cycle of the counter, the period signal is output so that the output interval of the coincidence signal is equal to or less than the circulation cycle and the number of times of output is minimized. And a control means for determining a value to be set in the comparator by dividing the period. In this case, the period signal generator may be used in connection with the control of the internal combustion engine (claim 2).

[0006]

According to the period signal generator of the present invention, when the period of the period signal to be generated exceeds the circulation cycle of the counter, the control means sets the output interval of the coincidence signal to be equal to or less than the circulation cycle. Since the period signal is generated by dividing the cycle of the period signal so that the number of outputs is the minimum and determining the value to be set in the comparator, the coincidence signal output by the comparator is interrupted. It is possible to generate a period signal with a minimum of interrupt processing.

In this case, if the period signal generator is used in connection with the control of the internal combustion engine, it can be effectively applied to the control of various valves (claim 2).

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an electronic fuel injection device in a gasoline engine (hereinafter referred to as an engine) which is an internal combustion engine of an automobile will be described with reference to the drawings. In FIG. 2 showing a simplified mechanical structure of an engine, an engine main body 1 is mainly composed of a plurality of cylinders 2 and a piston 3 which vertically moves in contact with an inner wall of the cylinders 2. Only one is shown as a representative. At an upper portion of the combustion chamber 4 formed in a space between the cylinder 2 and the upper surface of the piston 3, an intake passage 6 whose communication to the combustion chamber 4 is controlled by an intake valve 5 on the upper right side of the cylinder 2, Similarly, an exhaust passage 8 whose communication with the combustion chamber 4 is controlled by an exhaust valve 7 on the upper left side of the cylinder 2 is formed. A spark plug 16 is provided in the upper part of the combustion chamber 4 between the intake valve 5 and the exhaust valve 7.

In the intake passage 6, there are an air amount sensor 9 for measuring the intake air amount, a throttle valve 10 interlocking with an accelerator pedal (not shown), and a surge tank 11 for distributing the intake air to other cylinders (not shown). . Then, the intake passage 6 between the surge tank 11 and the intake valve 5
A fuel injection valve 12 for injecting fuel into the intake passage 6 is installed above the.

An evaporative gas exhaust port 13 for introducing the fuel (evaporative gas) vaporized from a fuel tank (not shown) and stored in the canister into the intake passage 6 is provided in the lower portion of the surge tank 11, and the evaporative gas intake passage is provided. The discharge to 6 is controlled by the purge valve 14.
The fuel injection valve 12 provided for each cylinder
The opening and closing of the purge valve 14 are controlled by a control signal which is an electric pulse signal output from the controller 15.

From the crank angle sensors 17a and 17b provided in the distributor 17, a pulse signal is output each time the rotation angle of a crankshaft (not shown) becomes 180 degrees and 720 degrees, and each output signal is an air signal. The output signal of the quantity sensor 9 is provided to the control device 15.

In FIG. 3 showing the electrical construction of the control device 15, the CPU 18 as a control means is provided with a ROM 19, R
It is connected to the AM 20, the A / D converter 21, and the I / O interfaces 22a and 22b via address and data bus lines and control signal lines. The output signals of the air amount sensor 9 and other sensors (not shown) are A /
The signal is given to the input terminal of the D converter 21 and is A / D converted according to the instruction signal given by the CPU 18.

The output signal from the crank angle sensor 17a is applied to the input terminal of the I / O interface 22a and becomes an interrupt request signal to the CPU 18. In addition, the output signal from the timing counter of the CPU 18 is provided. It becomes a clock signal. The output signal from the crank angle sensor 17b is also given to the input terminal of the I / O interface 22a, which serves as a reset signal for the timing counter. The CPU 18
An injection pulse width signal is output based on the timing signal obtained from the timing counter and given to the I / O interface 22b.

The I / O interface 22b has a drive circuit for converting it into a drive signal corresponding to the timing and pulse width of the input pulse width signal for injection. The drive signal is given to the fuel injection valve 12, and the fuel injection valve 12 injects an amount of fuel according to the injection pulse width signal (see FIG. 5).

Now, FIG. 1 shows an electrical configuration of the period signal generator 27 centering on the CPU 18. In FIG. 1, a CPU 18, a comparator 23, and a free run timer (FR), which is a counter that cyclically counts the number of pulses of an input clock signal.
T) 24 and the pulse generation circuit 25 are connected by a data bus line and a control signal line, and an address decoder (not shown) is connected by an address bus line and a control signal line. Also, a chip select signal is applied from the address decoder to the comparator 23, the FRT 24 and the pulse generating circuit 25.

A clock signal is supplied from the clock circuit 26 to the clock input terminal of the FRT 24, and the FRT 24 counts at the rising edge of the clock signal. The FRT 24 has a bit width of 16 bits, for example, and when counting from 0000H to FFFFH,
It returns to 0000H again and continues counting cyclically. Further, the CPU 18 can read the counter bit of the FRT 24 via the data bus line.

At one data input terminal of the comparator 23,
The counter bit of the FRT 24 is input, and the data written from the CPU 18 is latched and input to the other data input terminal by a latch circuit (not shown). When the data at both data input terminals match, the comparator 23 applies a match signal to the trigger input terminal of the pulse generation circuit 25 and at the same time to the interrupt input terminal of the CPU 18.

In the pulse generator 25, the high or low level of the opening / closing pulse width signal output when a trigger is input is written and set by the CPU 18, and the output opening / closing is performed. The pulse width signal for use is applied to the input terminal of the I / O interface 22b. And I / O interface 2
2b outputs a drive signal corresponding to the opening / closing pulse width signal from the drive circuit and supplies it to the purge valve 14, and the purge valve 14 is controlled to open / close by this.

Next, the operation of this embodiment will be described with reference to FIGS. 4 to 12. The control device 15 outputs the injection pulse width signal based on the output signals from the crank angle sensors 17a and 17b given as the clock signal of the timing counter and the reset signal thereof to perform the fuel injection control process.

That is, the opening and closing of the fuel injection valve 12 provided for each cylinder 2 is controlled by the drive signal (injection pulse width signal) output from the I / O interface 22b of the control device 15, and is shown in the drawing. The pressurized fuel sent from the fuel supply system is intermittently injected into the intake passage 6.

The fuel injected into the intake passage 6 is supplied into the combustion chamber 4 together with the air taken in through the throttle valve 10 when the intake valve 5 is opened, ignited by the ignition plug 16 and burned. The explosive force pushes down the piston 3 to rotate a crank (not shown). Then, the exhaust gas after being burned in the combustion chamber 4 is sent to the exhaust passage 8 through the open exhaust valve 7 and is discharged into the atmosphere through a catalytic converter (not shown). By repeating this combustion cycle, the engine rotates to drive the load.

In FIG. 4 showing a flow chart of the control subroutine of the purge valve 14, this is performed by the base processing of the CPU 18 at intervals of 65 ms, and the purge valve 14 is executed in the processing step P1 of "calculate duty Dw".
The duty ratio Dw, which is the ratio of opening control during one cycle (driving cycle T), is the input / output information of the engine, that is, the intake air amount obtained from the air amount sensor 9 and the pulse signal from the crank angle sensor 17a or 17b. It is calculated based on the number of revolutions obtained by counting, for example, it is set to 0% during idling, and becomes larger as the number of revolutions increases and the intake amount increases (that is, as the load increases). Is set to. When the calculation of the duty ratio Dw is completed in this way, the process is exited and the process returns to the main routine.

When the duty ratio Dw calculated here is calculated at the time for the opening / closing pulse width signal as the period signal, as will be described later, the pulse signal which becomes low level by the pulse generation circuit 25 for that time. Is output to the I / O interface 22b as the purge valve 1
4 is controlled to open and close (see FIG. 5).

If the cycle of the clock signal given to the FRT 24 is 1 μs, the count value is 0 to 6
Since it is 5535, the circulation cycle Tm is 65.536 ms.
Becomes Then, the driving cycle T is 100 ms, and the low-level output pulse width is Twms. The bit width of the setting data of the comparator 23 is 16 bits, which is the same as that of the FRT 24. Creation of the opening / closing pulse width signal which is the control signal of the purge valve 14 is performed based on the interrupt processing to the CPU 18 generated by the coincidence signal from the comparator 23.

First, the interrupt generated before the first pulse is generated is generated by the CPU 18 writing an appropriate value in the comparator 23. Further, the level "low" is set in the pulse generation circuit 25 in the initialization process, and at the time when the match signal is first output,
The pulse generation circuit 25 outputs low. In the following, the value expressed by converting the time in ms unit into the count value of the FRT 24 will be expressed by adding a subscript to C. For example, a count value of 50 ms is expressed as C50. The maximum count value corresponding to the maximum cycle Tm of the FRT 24 is Cm (= FFFFH).

In FIG. 6 showing a flow chart of the control contents of the interrupt processing, the CPU 18 causes "CINT = 0".
? In a determination step S1 of "," it is determined whether or not the value of CINT, which is a counter of the number of interrupts, is 0. CIN
Since T has been cleared to 0 in the initialization processing, first, it is determined to be "YES" and the next "Dw to Tw
Calculation step S2.

In processing step S2, a low-level pulse width (hereinafter simply referred to as pulse width) is calculated from the duty ratio Dw of the opening / closing pulse width signal obtained in processing step P1.
When the time Tw of is calculated, the value of the next Comp is read and “RAM (100 ms reference START time) ← Co
mp ”processing step S3, and the current register C
A reference START provided in the RAM 20 for reading the value of omp and setting the value in the comparator 23 as an initial value.
When it is written and stored in the time value storage area, the next “0 <Tw
≦ 50 ms? The determination step S4 is performed.

In the processing step S4, the pulse width T
w is 50 which is 1/2 of the driving cycle T of 100 ms.
It is determined whether or not ms or less. Judgment step S4
If “YES” is determined in step 1, the next “pulse generation circuit is set to“ H ”Comp ← Comp + Cw” processing proceeds to step S5, and if “NO” is determined, the next “pulse generation circuit is set to“ L ”. Setting Comp ← Comp
+ Cw / 2 "processing step S6.

After that, first, the pulse width Tw is 0 <Tw ≦ 5.
The case of 0 ms will be described. In processing step S5, the CPU 18 writes to the pulse generation circuit 25, and sets the level of the pulse signal output from the pulse generation circuit 25 to "high" at the next input of the trigger signal.
Set to (H). Then, the value Cw obtained by converting the pulse width Tw into a count value is added to the value of the register Comp written in step S3, and the value is added again to the register Com.
Write to p and set it in comparator 23. afterwards,
The process moves to the processing step S7 of "CINT ← CINT + 1". In the processing step S7, the interrupt processing is finished by incrementing the interrupt number counter CINT, and the process returns to the main routine.

After that, the count of the FRT 24 progresses,
When it becomes equal to the value set in the comparator 23 in step S5, the comparator 23 outputs a coincidence signal to the pulse generation circuit 25 and causes the CPU 18 to generate an interrupt.
Since the pulse generation circuit 25 outputs the level "high" set in step S5 at this time, the time from the time when the first interrupt is input to this point is the output time of the low level period corresponding to the pulse width Tw. (See Figure 7).

When the interrupt processing routine is entered again, the interrupt counter CINT has become 1, so this time it is judged "NO" at judgment step S1 and "CINT =
1? The determination step S8. Judgment step S
In No. 8, since it is determined as “YES”, the next “0 <Tw ≦ 5
0 ms? The determination step S9 is performed.

If "YES" is determined in S9 in the determination step, "pulse generator circuit is set to" H "Comp ← Co
mp + (C100-Cw) / 2 "processing step S10 is performed, and if" NO "is determined, the next" pulse generator circuit "H" setting Comp ← Comp + Cw / 2 "processing step S11 is performed.

In the processing step S10, the pulse width Tw is in the range of 0 <Tw ≦ 50 ms. Therefore, a value C100 obtained by converting the driving period T of 100 ms into a count value
If the value obtained by subtracting the pulse width count value Cw from the above is directly added to the current value of the register Comp, the maximum count value Cm may be exceeded, that is, C100-Cw> Cm. This will be described with reference to FIG. 7. Step S
In order to specify the circulation cycle Tm in which the RAM value (reference time) is read in 3 and Tm (1), depending on the RAM value (reference time), the next circulation cycle Tm (2) is exceeded, and the next circulation cycle is further exceeded. This indicates that the count value for Tm (3) may be reached.

At this time, the bit width of the comparator 23 is FRT.
Since it is 16 bits which is equal to the bit width of 24, the 17th bit that overflows beyond the circulation period Tm (2) is ignored, and the time to come to point a in Tm (3) on the horizontal axis in FIG. 7 is ignored. Will come to point b in Tm (2), and accurate time setting will not be possible.

In order to avoid this, in the processing step S10, the value of the register Comp is set to the count value C of the driving cycle.
The value obtained by subtracting the pulse width count value Cw from 100 and dividing by 2 is added, the value is again written in the register Comp, and the value is set in the comparator 23. And "CINT
When the counter CINT is incremented by going to the processing step S12 of "← CINT + 1", the interrupt processing is terminated and the process returns to the main routine.

Then, after a lapse of time, the FRT 24
When the count value of 1 coincides with the value set in the comparator 23 in step S10, the comparator 23 outputs a coincidence signal to the pulse generation circuit 25 and causes the CPU 18 to generate an interrupt. The pulse generation circuit 25 outputs the level "high" set in step S10 at this point.

In the third interrupt processing routine, the counter CINT is 2, and it is judged "NO" in steps S1 and S8, and "the pulse generation circuit is" L ".
Setting Comp ← RAM (100 ms reference START time) + C100 ”processing proceeds to step S13. In the processing step S13, when the level "low" is set in the pulse generation circuit 25, the driving cycle (T) of 100 ms is set.
In order to output, the counter initial value Cx of the FRT 24 stored in the RAM 20 in the processing step S3 is read, and a value obtained by adding the count value C100 of the driving cycle of 100 ms to the register Comp is written and stored in the comparator 23. Set. Then, when the counter CINT is cleared to 0 in the next processing step S14 of "CINT ← 0", the interrupt processing is terminated and the process returns to the main routine.

When a further time elapses and the count value of the FRT 24 becomes equal to the value set in the comparator 23 in step S13, the comparator 23 outputs a coincidence signal to the pulse generation circuit 25.
And the CPU 18 is caused to generate an interrupt, and the process of creating the opening / closing pulse width signal in the next cycle is started. The pulse generation circuit 25 then returns to step S1 at this point.
The level "low" set in 3 is output. As described above, the opening / closing pulse width signal for one cycle is created.

On the other hand, the pulse width Tw is 50 ms <Tw ≦ 1.
The case of being in the range of 00 ms will be described. In this case, it is determined to be "NO" in the determination step S4 and the process proceeds to the processing step S6. Here, the converted value Cw
If is added to the current value of the register Comp as it is, the count value may exceed the circulation cycle Tm (2) and reach the next circulation cycle Tm (3) as in the case of step S10 (see FIG. 8). In order to avoid this, in processing step S6, Cw / 2 obtained by dividing the converted value Cw by 2 is added to the value of the register Comp, the value is written again in the register Comp, and it is set in the comparator 23. To do. Then, the process proceeds to the processing step S7 of "CINT ← CINT + 1".

In the next interrupt processing at CINT = 1, it is judged "NO" in the judgment step S9 and "the pulse generating circuit is set to" H "Comp ← Comp +.
Cw / 2 ”processing step S11, and register C
The value of omp is read, Cw / 2 obtained by dividing the converted value Cw by 2 is added again, the value is written again in the register Comp, and it is set in the comparator 23. Then, the processing step S12 of "CINT ← CINT + 1"
Move to

Thereafter, the coincidence signal is output from the comparator 23, and in the interrupt processing at CINT = 2, the pulse generation circuit 25 outputs the level "high" set in step S11, so that the first interrupt is input. From this point to the point up to this point is the output time of the low level period corresponding to the pulse width Tw.

Next, the case of T = 150 ms will be described with reference to FIGS. 9 to 12. The same parts as those in FIG. 5 are designated by the same reference numerals, and only different parts will be described below. In FIG. 9 showing the flowchart of the control contents of the interrupt process when T = 150 ms, first, when the pulse width Tw is 0 <Tw ≦ 50 ms (see FIG. 10),
The first interrupt process passes through steps S1 to S5 and S7, exits the interrupt process, and returns as in the case of T = 100 ms. Also, the second interrupt processing is T
As in the case of 100 ms, the process goes through steps S8 to S10 and S12, exits the interrupt process, and returns.

In the third interrupt processing, "CIN
T = 1? If "NO" is determined in the determination step S8 of "," the process proceeds to determination step S19 of "CINT = 2?", And it is determined whether or not the interrupt counter CINT is 2. In this case, the determination step S19 returns "Y
When it is judged as "ES", the process proceeds to the next judgment step S20 of "0 <Tw≤50 ms?". Then, the judgment step S
Since it is determined to be “YES” also in 20, the next “H” is set in the pulse generation circuit Comp ← Comp + (C10
0-Cw) / 2 "processing step S21.

In the processing step S21, the level "high" is set in the pulse generating circuit 25, and the step S10 is performed.
The same value (C100
Add −Cw) / 2 to the current value of register Comp and set it in comparator 23. Then, "CINT ← CI
If the counter CINT is incremented by proceeding to the processing step S25 of "NT + 1", the interrupt processing is terminated and the processing returns.

In the fourth interrupt processing, the counter CINT is 3, so "NO" is determined in the determination steps S1, S8 and S19, and "L" is set in the pulse generation circuit Comp ← RAM (150 ms standard). ST
(ART time) + C150 "processing proceeds to step S26. In the processing step S26, the pulse generation circuit 2
Set level "high" to 5. Further, the difference value between the value of the register Comp and the count value for outputting the cycle of 150 ms at this time is (RAM (150 ms standard ST
(ART time) + C150)-(RAM (150 ms standard S
TART time) + C100) = C50, and the value does not exceed the maximum count value Cm.

Therefore, Comp + C50 is set to the register Com.
It is only necessary to set it to p, but to set the flow divided into cases according to the value of the pulse width Tw, which will be described later, collectively, read the 150 ms reference START time stored in the RAM 20 and add C150 to it. This is set in the register Comp. As described above, this process is represented by a count value RAM (150 ms reference START time) + C100 + C50 = RAM (150 m
s reference START time) + C150, so Comp +
This is equivalent to the expression C50, and even when viewed along the horizontal axis (time) in FIG. 10, Tx + 100 + 50 = Tx + 150, and both indicate the same time. Then, when the counter CINT is cleared to 0 in the next processing step S27 of "CINT ← 0", the interrupt processing is terminated and the process returns to the main routine.

Next, the pulse width Tw is 50 ms <Tw ≦
Processing in the case of being in the range of 100 ms will be described with reference to FIG. In this case, if "NO" is determined in the determination step S4 in the first interruption process, "50 m
s <Tw ≦ 100 ms? The determination step S <b> 15 is performed. Then, in determination step S15, "YES"
Since it is determined that "L" is set in the pulse generation circuit C
The process proceeds to the processing step S6 of "omp ← Comp + Cw / 2" and is processed in the same manner as when the pulse period is 100 ms.

In the second interruption process, the judgment step S
When it is judged as “NO” in 9, “50 ms <Tw ≦
100ms? The determination step S17 is performed. Then, since "YES" is determined in the determination step S17, "H" is set in the pulse generation circuit Comp ← Co
mp + Cw / 2 ”, the process proceeds to step S11, and the same process is performed as when the pulse period is 100 ms.

In the third interrupt processing, if "NO" is determined in the determination step S20, "50 ms" is returned.
<Tw ≦ 100 ms? The determination step S22 is performed. Then, since "YES" is determined in the determination step S22, "pulse generation circuit is set to" H "Com
p ← Comp + (C150-Cw) / 2 "processing step S23. Register Comp at this point
The difference between the value of and the cycle of 150 ms is (RAM (150
ms reference START time) + C150)-(RAM (15
0 ms reference START time) + Cw) = C150-Cw, and depending on the value of the count value Cw, the maximum count value C
There is a possibility of exceeding m. Therefore, this value is
If it is added to the current value of omp as it is, the time at which point a in FIG. 11 should arrive is point b, and accurate time setting may not be performed.

Therefore, in the processing step S23,
After the level "high" is set in the pulse generation circuit 25, the value obtained by dividing the difference value by 2 is added to the current value of the register Comp and set in the register Comp again, and the value is set in the comparator 23. Then, when the process proceeds to step S25 and the counter CINT is incremented, the interrupt process is exited and the process returns to the main routine.

In the fourth interrupt processing, the remaining value to be set in the comparator 23 to output the driving cycle of 150 ms at that time is within the maximum count value Cm, so that the pulse width Tw is 50 ms or less in the processing step S26. The same processing as in the case of is performed.

Next, a case where the pulse width Tw exceeds 100 ms will be described with reference to FIG. In the first interrupt process, since “NO” is determined in the determination step S15 of “50 ms <Tw ≦ 100 ms?”, “Pulse generator circuit is set to“ L ”Comp ← Com
p + C50 "processing step S16. In the processing step S16, the pulse generation circuit 25 receives the level "
"Low" is set, and a value within the cycle period Tm, for example, C50 is added to the current value of the FRT 24 to register Comp.
Set to. Then, when the counter CINT is incremented in step S7, the interrupt process is terminated and the process returns to the main routine.

In the second interrupt processing, since "NO" is determined in the determination step S17, "pulse generator circuit is set to" L "Comp ← Comp + (Cw
-C50) / 2 "processing step S18. In the processing step S18, the pulse width count value Cw
The value obtained by subtracting the count value C50 from is the maximum count value Cm.
May exceed.

Therefore, in step S18, the level "low" is set in the pulse generation circuit 25, and the value obtained by dividing the difference value between the count value Cw and the count value C50 by 2 is added to the current value of the register Comp and the register is added. The Comp is reset, and the value of the register Comp is set in the comparator 23. Then, in step S12, the counter C
When the INT value is incremented, the interrupt processing is terminated and the process returns to the main routine.

In the third interruption process, "50 m
s <Tw ≦ 100 ms? Since it is judged as "NO" in the judgment step S22 of "
H "setting Comp ← Comp + (Cw-C50) / 2"
The processing shifts to the processing step S24. Processing step S24
, The level "high" is set in the pulse generation circuit 25, and the same value (Cw-C50) / 2 added to the register Comp in step S18 is set in the register Co.
It is added to the current value of mp and set again in register Comp. Then, in step S25, the counter CIN
When T is incremented, the interrupt process is terminated and the process returns to the main routine.

In the fourth interrupt processing, the remaining value to be set in the comparator 23 to output the driving cycle of 150 ms at that time is within the maximum count value Cm, so that the pulse width Tw is 50 ms or less in the processing step S26. In the case, and the pulse width Tw is 50 ms <Tw ≦ 100 ms, the same processing is performed.

As described above, according to this embodiment, the comparator 2
When the value set to 3 and the count value of the FRT 24 match, the FRT based on the match signal output from the comparator 23.
When generating a pulse signal having a cycle exceeding 24 circulation cycles Tm, the CPU 18 sets the output interval of the coincidence signal input as an interrupt signal to be less than or equal to the circulation cycle Tm and minimizes the number of outputs. The pulse signal period is divided to determine the value to be set in the comparator 23. Therefore, unlike the prior art, it is not necessary to perform a complicated process such that an interrupt is input to the CPU every unit time and a value is reset to the comparator each time the interrupt is input. It is possible to minimize the CPU processing time required for the generation.

The present invention is not limited to the embodiments described above and shown in the drawings, but the following modifications are possible. Set the bit width of the FRT 24 and the comparator 23 to 1
Although it is set to 6 bits, more or less bits may be used. Set the cycle of the clock signal input to the FRT 24 to 1μ
However, it may be larger or smaller than this.

Although the upper limit of the range of cases depending on the value of the pulse width Tw is set to 50 ms in the determination steps S4 and S9, it may be any value that is less than the circulation period Tm and exceeds Tm-Tw. Similarly, determination steps S15, S17 and S
In Fig. 22, the lower limit of the range of cases is set to 50 ms and the upper limit is set to 100 ms.
Any value that exceeds −Tw is acceptable, and the upper limit is 2 Tm or less and 2
Any value may be used as long as it exceeds Tm-Tw. Along with that, the count value represented by C50 in the process step of setting the value in the register Comp may be a value equal to or less than the maximum count value Cm and larger than Cm-Cw, and represented by C100. The counted value is 2Cm or less and 2
Any value may be used as long as it exceeds Cm-Cw.

When the driving cycle T is 100 ms and 150 m
Although the case of s is shown, the present invention is not limited to this, and even if the driving cycle T is three times or more of the circulation cycle Tm, it can be appropriately implemented by adding a flow accordingly. Although the purge valve 14 is controlled based on the opening / closing pulse width signal, the idle up valve and the EGR (exhaust
A gas recirculation valve or the like may be controlled. Further, the invention is not limited to the valve control of the engine but can be applied as appropriate as long as it requires a signal for a period of a certain cycle.

[0061]

Since the present invention is as described above,
The following effects are obtained. According to the period signal generating device of claim 1, the control means, when the period of the period signal to be generated exceeds the circulation period of the counter, the output interval of the coincidence signal is equal to or less than the circulation period, and Since the period signal is divided so that the number of outputs is minimized and the value to be set in the comparator is determined, it is possible to generate the period signal while minimizing the processing load of the control means.

In this case, if the period signal generator is used in connection with the control of the internal combustion engine, it can be effectively applied to the control of various valves (claim 2).

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a period signal generator of the present invention.

FIG. 2 is a simplified structural diagram of an internal combustion engine.

FIG. 3 is a block diagram showing an electrical configuration of a control device.

FIG. 4 is a flowchart of control contents of purge valve control processing.

FIG. 5 is a timing chart of an opening / closing pulse width signal.

FIG. 6 is a diagram corresponding to FIG. 4 of the coincidence signal interrupt processing when the driving cycle is 100 ms.

FIG. 7 shows a pulse width Tw of 0 <Tw in a driving cycle of 100 ms.
The figure which shows the relationship between the count value of FRT and a period in case of <= 50ms

FIG. 8 shows a pulse width Tw of 50 <T in a driving cycle of 100 ms.
FIG. 7 equivalent diagram when w ≦ 100 ms

FIG. 9 is a diagram corresponding to FIG. 6 when the driving cycle is 150 ms.

FIG. 10 shows a pulse width Tw of 0 <T in a driving cycle of 150 ms.
FIG. 7 equivalent diagram when w ≦ 50 ms

FIG. 11 shows a pulse width Tw of 50 <with a driving cycle of 150 ms.
FIG. 7 equivalent diagram when Tw ≦ 100 ms

FIG. 12 shows a pulse width Tw of 100 at a driving cycle of 150 ms.
Fig. 7 equivalent diagram when ms <Tw

[Explanation of symbols]

1 is an engine body, 14 is a purge valve, 18 is a CPU
(Control means), 23 is a comparator, 24 is a free-run timer (counter), 25 is a pulse generator, and 27 is a period signal generator.

Claims (2)

[Claims] 1. A counter that cyclically counts the number of pulses of an input clock signal within a certain counting range, and a counter that can be set to an arbitrary value and that set value is compared with the count value of the counter. And a comparator which outputs a coincidence signal when they coincide with each other, and a period signal which is provided so as to generate a period signal based on the coincidence signal given as an interrupt signal. If it exceeds, the control means for dividing the cycle of the period signal so as to determine the value to be set in the comparator so that the output interval of the coincidence signal is equal to or less than the circulation cycle and the number of times of output is minimized. A period signal generator comprising: 2. The period signal generator according to claim 1, which is used in connection with the control of an internal combustion engine.