JP2007186725A5 - - Google Patents

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JP2007186725A5
JP2007186725A5 JP2006003444A JP2006003444A JP2007186725A5 JP 2007186725 A5 JP2007186725 A5 JP 2007186725A5 JP 2006003444 A JP2006003444 A JP 2006003444A JP 2006003444 A JP2006003444 A JP 2006003444A JP 2007186725 A5 JP2007186725 A5 JP 2007186725A5
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circuit
waveform
output
arc
targets
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JP2006003444A
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Japanese (ja)
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JP4963023B2 (en
JP2007186725A (en
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Priority claimed from JP2006003444A external-priority patent/JP4963023B2/en
Priority to JP2006003444A priority Critical patent/JP4963023B2/en
Priority to PCT/JP2007/050200 priority patent/WO2007080905A1/en
Priority to CN2007800022189A priority patent/CN101370959B/en
Priority to TW096101141A priority patent/TWI392755B/en
Priority to KR1020087016805A priority patent/KR101028050B1/en
Publication of JP2007186725A publication Critical patent/JP2007186725A/en
Publication of JP2007186725A5 publication Critical patent/JP2007186725A5/ja
Publication of JP4963023B2 publication Critical patent/JP4963023B2/en
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スパッタリング法では、プラズマ雰囲気中のイオンを、処理基板表面に成膜しようとする薄膜の組成に応じて所定形状に作製されたターゲットに向けて加速させて衝撃させ、ターゲット原子を飛散させ、処理基板表面に薄膜を形成する。この場合、カソード電極であるターゲットに、直流電源または交流電源を介して電圧を印加することでカソード電極と、アノード電極またはアース電極との間にグロー放電を生じさせてプラズマ雰囲気を形成している。 In the sputtering method, ions in the plasma atmosphere, treatment in accordance with the composition of Utosu Ru film to film formation on the substrate surface is accelerated toward the target made into a predetermined shape by an impact, to scatter the target atom, A thin film is formed on the surface of the processing substrate. In this case, a plasma atmosphere is formed by applying a voltage to the target, which is a cathode electrode, via a DC power supply or an AC power supply, thereby generating a glow discharge between the cathode electrode and the anode electrode or the earth electrode. .

この場合、ターゲット41a、41bは、その未使用時のスパッタ面411が、処理基板Sに平行な同一平面上に位置するように並設され、各ターゲット41a、41bの向かい合う側面412相互の間には、アノードやシールドなどの構成部品を何ら設けていない。各ターゲット41a、41bの外形寸法は、各ターゲット41a、41bを並設した際に処理基板Sの外形寸法より大きくなるように設定している。 In this case, the targets 41a and 41b are juxtaposed so that the sputtering surfaces 411 when not in use are positioned on the same plane parallel to the processing substrate S, and between the side surfaces 412 facing each target 41a and 41b. Does not have any components such as an anode or a shield. The external dimensions of the targets 41a and 41b are set to be larger than the external dimensions of the processing substrate S when the targets 41a and 41b are arranged side by side.

そして、第2のドライバー回路73a及び第2のPMW制御回路73bによって、例えば第1及び第のスイッチングトランジスタ72a、72と、第及び第のスイッチングトランジスタ72、72とのオン、オフのタイミングが反転するように各スイッチングトランジスタ72a、72b、72c、72dの作動を制御すると、発振用スイッチ回路72からの交流電力ライン74a、74bを介して正弦波の交流電力が出力できる。この場合、発振電圧、発振電流を検出する検出回路75a及びAD変換回路75bが設けられ、検出回路75a及びAD変換回路75bを介して第2のCPU回路71に入力されるようになっている。 Then, the second driver circuit 73a and the second PMW control circuit 73b, for example, the first and fourth switching transistors 72a, 72 d, the second and third on the switching transistor 72 b, 72 c, When the operation of each switching transistor 72a, 72b, 72c, 72d is controlled so that the OFF timing is reversed, sinusoidal AC power can be output via the AC power lines 74a, 74b from the oscillation switch circuit 72. In this case, a detection circuit 75a and an AD conversion circuit 75b that detect an oscillation voltage and an oscillation current are provided, and are input to the second CPU circuit 71 via the detection circuit 75a and the AD conversion circuit 75b.

本実施の形態では、発振部7に、一対のターゲット41a、41bへの出力電圧波形の電圧降下時間が正常なグロー放電時よりも短時間である電圧降下を検出するアーク検出手段8を設けることとした。そして、アーク検出手段8でアーク放電発生を検出すると、電圧降下アーク出力信号を、通信自在に接続した第2のCPU回路71に出力し、第2のCPU回路71と通信自在な第1のCPU回路61からの制御信号で第1のドライバー回路66aによってスイッチングトランジスタ65の作動を制御し、一対のターゲット41a、41bへの出力を直ちに遮断することとした。 In the present embodiment, the oscillating unit 7 is provided with arc detecting means 8 for detecting a voltage drop in which the voltage drop time of the output voltage waveform to the pair of targets 41a and 41b is shorter than that during normal glow discharge. It was. When the arc detection means 8 detects the occurrence of arc discharge, the voltage drop arc output signal is output to the second CPU circuit 71 connected to be communicable, and the first CPU communicable with the second CPU circuit 71 is provided. The operation of the switching transistor 65 is controlled by the first driver circuit 66a by the control signal from the circuit 61 , and the output to the pair of targets 41a and 41b is immediately cut off.

図6(a)及び図6(b)を参照して説明すれば、90は、さらに他の実施の形態に係るアーク検出手段である。このアーク検出手段90は、出力電圧波形及び出力電流波形の差分波形からアーク放電の発生を検出するものであり、検出回路77aからの出力電圧及び出力電流を増幅する電流センサアンプ910及び電流トランスアンプ920と、出力電圧波形及び出力電流波形のノイズの除去を可能とする公知のノイズフィルター930a、930bと、ノイズフィルター930a、930bを経た出力電圧波形及び出力電流波形の振幅が略一致するように調節する第1及び第2の各ゲイン調整回路940a、940bとを有する。 If it demonstrates with reference to Fig.6 (a) and FIG.6 (b), 90 is the arc detection means which concerns on other embodiment. The arc detection means 90 detects the occurrence of arc discharge from the difference waveform between the output voltage waveform and the output current waveform, and a current sensor amplifier 910 and current transformer amplifier that amplify the output voltage and output current from the detection circuit 77a. 920, known noise filters 930a and 930b that can remove noise in the output voltage waveform and output current waveform, and adjustment so that the amplitudes of the output voltage waveform and output current waveform that have passed through the noise filters 930a and 930b substantially match First and second gain adjustment circuits 940a and 940b.

また、アーク検出手段90は、第1及び第2の各ゲイン調整回路940a、940bを経た出力電圧波形と出力電流波形とがそれぞれ入力され、それらの差に応じて差動する公知の構造の差動アンプ950と、差動アンプ950からの差分波形の絶対値を検出する絶対検出回路960と、この絶対値と、差分波形検出レベルとがそれぞれ入力される比較器970aを設けた差分波形検出回路970とを有する。
Further, the arc detection means 90 receives the output voltage waveform and the output current waveform that have passed through the first and second gain adjustment circuits 940a and 940b, respectively, and the difference between the known structures that performs differential operation according to the difference between them. Differential waveform detection provided with a dynamic amplifier 950, an absolute value detection circuit 960 that detects the absolute value of the differential waveform from the differential amplifier 950, and a comparator 970a to which the absolute value and the differential waveform detection level are input. Circuit 970.

JP2006003444A 2006-01-11 2006-01-11 Sputtering method and sputtering apparatus Active JP4963023B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2006003444A JP4963023B2 (en) 2006-01-11 2006-01-11 Sputtering method and sputtering apparatus
KR1020087016805A KR101028050B1 (en) 2006-01-11 2007-01-11 Sputtering method and sputtering system
CN2007800022189A CN101370959B (en) 2006-01-11 2007-01-11 Sputtering method and sputtering system
TW096101141A TWI392755B (en) 2006-01-11 2007-01-11 Sputtering method and sputtering device
PCT/JP2007/050200 WO2007080905A1 (en) 2006-01-11 2007-01-11 Sputtering method and sputtering system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006003444A JP4963023B2 (en) 2006-01-11 2006-01-11 Sputtering method and sputtering apparatus

Publications (3)

Publication Number Publication Date
JP2007186725A JP2007186725A (en) 2007-07-26
JP2007186725A5 true JP2007186725A5 (en) 2009-02-26
JP4963023B2 JP4963023B2 (en) 2012-06-27

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JP (1) JP4963023B2 (en)
KR (1) KR101028050B1 (en)
CN (1) CN101370959B (en)
TW (1) TWI392755B (en)
WO (1) WO2007080905A1 (en)

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JP5016819B2 (en) * 2006-01-11 2012-09-05 株式会社アルバック Sputtering method and sputtering apparatus
WO2009025306A1 (en) * 2007-08-20 2009-02-26 Ulvac, Inc. Sputtering method
JP5429771B2 (en) * 2008-05-26 2014-02-26 株式会社アルバック Sputtering method
US9613784B2 (en) * 2008-07-17 2017-04-04 Mks Instruments, Inc. Sputtering system and method including an arc detection
JP5363166B2 (en) * 2009-03-31 2013-12-11 株式会社アルバック Sputtering method
DE102010031568B4 (en) 2010-07-20 2014-12-11 TRUMPF Hüttinger GmbH + Co. KG Arclöschanordnung and method for erasing arcs
KR20130121935A (en) * 2011-02-08 2013-11-06 샤프 가부시키가이샤 Magnetron sputtering device, method for controlling magnetron sputtering device, and film forming method
DE102013110883B3 (en) 2013-10-01 2015-01-15 TRUMPF Hüttinger GmbH + Co. KG Apparatus and method for monitoring a discharge in a plasma process
EP2905801B1 (en) 2014-02-07 2019-05-22 TRUMPF Huettinger Sp. Z o. o. Method of monitoring the discharge in a plasma process and monitoring device for monitoring the discharge in a plasma
TWI617687B (en) * 2014-12-04 2018-03-11 財團法人金屬工業研究發展中心 Monitoring method and system for a sputter device
KR101757818B1 (en) 2015-10-12 2017-07-26 세메스 주식회사 Apparatus for monitoring pulsed radio frequency power, and apparatus for treating substrate comprising the same
JP2019189913A (en) * 2018-04-26 2019-10-31 京浜ラムテック株式会社 Sputtering cathode, sputtering cathode assembly and sputtering apparatus
JP7195504B2 (en) * 2020-07-31 2022-12-26 国立研究開発法人日本原子力研究開発機構 Vacuum component, vacuum exhaust method using the same

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DE4441206C2 (en) * 1994-11-19 1996-09-26 Leybold Ag Device for the suppression of rollovers in cathode sputtering devices
JPH09170079A (en) * 1995-12-18 1997-06-30 Asahi Glass Co Ltd Sputtering method and device
WO1998048444A1 (en) * 1997-04-21 1998-10-29 Tokyo Electron Arizona, Inc. Method and apparatus for ionized sputtering of materials
JPH11200036A (en) * 1998-01-16 1999-07-27 Toshiba Corp Production of thin film and sputtering device therefor
JP2001003166A (en) * 1999-04-23 2001-01-09 Nippon Sheet Glass Co Ltd Method for coating surface of substrate with coating film and substrate by using the method
JP2002012969A (en) * 2000-07-03 2002-01-15 Sanyo Shinku Kogyo Kk Method for controlling sputtering apparatus
JP4780972B2 (en) * 2004-03-11 2011-09-28 株式会社アルバック Sputtering equipment

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