JP2007184427A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 132
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 33
- 230000003647 oxidation Effects 0.000 claims description 28
- 238000007254 oxidation reaction Methods 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 18
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 107
- 239000000758 substrate Substances 0.000 description 25
- 230000015572 biosynthetic process Effects 0.000 description 14
- 230000000694 effects Effects 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000000470 constituent Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】第1半導体層10上に設けられ、前記第1半導体層10よりも酸化速度の遅いn型の第2半導体層11と、前記第2半導体層11内に互いに離隔して設けられ、前記第2半導体層11表面から前記第1半導体層10内部に達する深さを有するp型の第3半導体層12と、隣接する前記第3半導体層12間の前記第2半導体層11上にゲート絶縁膜13を介在して設けられたゲート電極14とを具備し、前記第2半導体層11の格子定数は前記第3半導体層12の格子定数よりも小さい。
【選択図】図1
Description
(1)pチャネルMOSトランジスタのチャネルに効果的に圧縮応力を印加し、MOSトランジスタの性能を向上出来る。
本実施形態に係る構成及び方法であると、ソース及びドレイン形成予定領域を、酸化とウェット処理を用いてリセスしている。そのため、ハードマスク15の消失を防止しつつソース及びドレインを深く形成出来、チャネルに効果的に圧縮応力を印加出来る。本効果について以下詳細に説明する。
MOSトランジスタにおいて、ソース及びドレインとウェル領域との間の接合に生じるリーク電流の原因の一つとして、両者の間の格子定数差に起因して発生するミスフィット転位がある。例えば図9に示す構成において、ソース及びドレインとなるSiGe層のGe濃度が20%であるとすれば、格子のミスマッチは約0.8%である。従って、ミスフィット転位密度が高く、接合リークが大きな問題となる場合がある。
(3)nチャネルMOSトランジスタのチャネルに効果的に引っ張り応力を印加し、MOSトランジスタの性能を向上出来る。
更に第1の実施形態と同様に、図14に示すようにSi層31直下におけるソース及びドレイン32からもSi層31に対して引っ張り応力を印加出来る。
(4)MOSトランジスタの特性バラツキを抑制し、半導体装置の性能を向上出来る。
一般的に、半導体等をエッチングする際、エッチングの結果得られる形状はエッチングすべきパターン形状に依存する。例えばエッチングパターンに疎密がある場合、密な領域ではエッチング深さが浅く、疎な領域では深くなる。従って、図21に示す構成を有する半導体装置において、ソース及びドレイン形成予定領域のリセスをRIEで行うと、密な領域ほどソース及びドレインが浅く、疎な領域ほど深くなり、MOSトランジスタ間で特性がばらつく。
また上記SiCだけでなく、GaAsを材料に用いることも可能であるし、GaAsにInやAl等が含まれる三元、四元化合物半導体を用いても良い。また、基板となるSiGe層10、30は、例えばシリコン基板上に形成された絶縁膜上に形成されても良い(SGOI構造)でも良いし、バルクSiGe基板であっても良い。
Claims (5)
- 第1半導体層上に設けられ、前記第1半導体層よりも酸化速度の遅いn型の第2半導体層と、
前記第2半導体層内に互いに離隔して設けられ、前記第2半導体層表面から前記第1半導体層内部に達する深さを有するp型の第3半導体層と、
隣接する前記第3半導体層間の前記第2半導体層上にゲート絶縁膜を介在して設けられたゲート電極と
を具備し、前記第2半導体層の格子定数は前記第3半導体層の格子定数よりも小さい
ことを特徴とする半導体装置。 - 第1半導体層上に設けられ、前記第1半導体層よりも酸化速度の遅いp型の第2半導体層と、
前記第2半導体層内に互いに離隔して設けられ、前記第2半導体層表面から前記第1半導体層内部に達する深さを有するn型の第3半導体層と、
隣接する前記第3半導体層間の前記第2半導体層上にゲート絶縁膜を介在して設けられたゲート電極と
を具備し、前記第2半導体層の格子定数は前記第3半導体層の格子定数よりも大きい
ことを特徴とする半導体装置。 - n型領域とp型領域とを有する第1半導体層と、
前記第1半導体層の前記n型領域上に設けられ、前記第1半導体層よりも酸化速度の遅いn型の第2半導体層と、
前記第2半導体層内に互いに離隔して設けられ、前記第2半導体層表面から前記第1半導体層内部に達する深さを有するp型の第3半導体層と、
隣接する前記第3半導体層間の前記第2半導体層上に第1ゲート絶縁膜を介在して設けられた第1ゲート電極と、
前記第1半導体層の前記p型領域上に設けられ、前記第1半導体層よりも酸化速度の遅いp型の第4半導体層と、
前記第4半導体層内に互いに離隔して設けられ、前記第4半導体層表面から前記第1半導体層内部に達する深さを有するn型の第5半導体層と、
隣接する前記第5半導体層間の前記第4半導体層上に第2ゲート絶縁膜を介在して設けられた第2ゲート電極と
を具備し、前記第1、第3、第5半導体層は、前記第2、第4半導体層と異なる同一の材料を用いて形成され、
前記第4半導体層の膜厚は、前記第1半導体層との格子整合によって生じる歪みが緩和しない臨界膜厚未満であり、
前記第2半導体層の格子定数は前記第3半導体層の格子定数よりも小さく、
前記第1半導体層の格子定数は前記第5半導体層の格子定数よりも大きい
ことを特徴とする半導体装置。 - 第1半導体層上に設けられた第1導電型の第2半導体層上に、ゲート絶縁膜を介在してゲート電極を形成する工程と、
前記ゲート電極上にマスク材を形成する工程と、
前記マスク材をマスクに用いて前記第2半導体層をエッチングし、前記第1半導体層を露出させる工程と、
酸化速度が前記第2半導体層よりも速い条件下で前記第1半導体層の表面を酸化させる工程と、
ウェット処理により前記第1、第2半導体層表面の酸化膜を除去する工程と、
前記第1、第2半導体層表面に第3半導体層をエピタキシャル成長させる工程と
を具備することを特徴とする半導体装置の製造方法。 - 前記第1導電型はn型であり、
前記第2半導体層は、前記第1半導体層との格子整合によって生じる歪みが緩和しない臨界膜厚未満であり、
前記第3半導体層の格子定数は、前記第1半導体の格子定数よりも大きい
ことを特徴とする請求項4記載の半導体装置の製造方法。
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JP2006001812A JP4410195B2 (ja) | 2006-01-06 | 2006-01-06 | 半導体装置及びその製造方法 |
US11/619,799 US7816739B2 (en) | 2006-01-06 | 2007-01-04 | Semiconductor device using SiGe for substrate |
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JP2006001812A Expired - Fee Related JP4410195B2 (ja) | 2006-01-06 | 2006-01-06 | 半導体装置及びその製造方法 |
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Cited By (2)
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JP2010533963A (ja) * | 2007-07-17 | 2010-10-28 | シャープ株式会社 | コア−シェル−シェル・ナノワイヤトランジスタ、およびその製造方法 |
JP2010171337A (ja) * | 2009-01-26 | 2010-08-05 | Toshiba Corp | 電界効果トランジスタ |
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US20070164364A1 (en) | 2007-07-19 |
US7816739B2 (en) | 2010-10-19 |
JP4410195B2 (ja) | 2010-02-03 |
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