JP2007180831A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To invalidate the command of external reset signals after executing the cancellation of a standby mode in which only an interface circuit part is turned "ON". <P>SOLUTION: In the semiconductor device, an LCD driver 20 is provided with an input/output circuit part 1, a logic memory circuit part 2 and a reset terminal PadReset. The input/output circuit 1 is provided with a Schmitt circuit 3 composed of a 2-input NOR circuit NOR 1 and an inverter INV1, a deep standby cancellation circuit 4, a first level shift circuit 5 and a second level shift circuit 8, and the logic memory circuit part 2 is provided with a regulator circuit 6 and a register. After a deep standby mode is canceled and a plurality of internal power sources are turned "ON", the signals of a "High" level which are "enable" signals are inputted from the register 7 to the 2-input NOR circuit NOR1, and the command of the external reset signals is invalidated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device provided with a standby mode.

  Semiconductor devices are strongly required to reduce power consumption as the system scale increases. In the field of mobile equipment using a battery or the like as a power source, it is particularly necessary to reduce current consumption from the viewpoint of battery life. Further, due to the progress of miniaturization of elements constituting the semiconductor device, an increase in leakage current and an element breakdown voltage are reduced, and in order to cope with this, the operating voltage of the element is lower than the external power supply voltage. For this reason, many power supply circuits for stepping down the external power supply are employed in the semiconductor device. Semiconductor memory, SoC (system on a chip), microcomputer or liquid crystal display device as a semiconductor device incorporating various power supply circuits does not access data, etc. in order to achieve low power consumption. A standby mode (also referred to as a power-down mode or a sleep mode) in which only the circuit section is “ON” is provided (see, for example, Patent Document 1).

In an image display device equipped with a display display driver or a display display driver, a standby mode (also referred to as a deep standby mode) in which only the input / output circuit section is “ON” after the external power supplied from the battery is turned on When the standby mode is canceled and the internal power is supplied, the logic / memory circuit portion and the driver portion are turned “ON”. At this time, when an enable signal of an external reset signal is input from the reset terminal, there is a problem that the mode is shifted to the standby mode. When transitioning to the standby mode again, there arises a problem that test efficiency such as noise test and product test test of an image display device equipped with a display display driver or a display display driver is lowered.
JP 2003-133935 A (page 30, FIG. 22)

  The present invention provides a semiconductor device including a circuit that can invalidate a command of an external reset signal after execution of cancellation of a standby mode in which only an interface circuit portion is “ON”.

  In order to achieve the above object, the semiconductor device of one embodiment of the present invention is input with an external reset signal that enables a deep standby mode when the enable signal level is set and allows the deep standby mode to be released when the disable signal level is set. A reset terminal, an external reset signal invalidating means for outputting a first signal for invalidating the external reset signal at the enable signal level, an interface circuit unit, and the external reset signal and the first signal. Input signal selecting means for inputting the signal, and the interface circuit unit, the signal output from the input signal selecting means is input, and after the first power is supplied to the interface circuit, the enable signal level The first signal of the external reset signal and the disable signal level is the input signal. When the signal is input to the selection means, the internal second power supply is turned “OFF” to output a signal to enter the deep standby mode, and after the deep standby mode is released, the first signal at the enable signal level is A deep standby release circuit that outputs a signal that disables the external reset signal and maintains the "ON" state of the second power supply when input to the input signal selection means.

  Furthermore, in order to achieve the above object, the semiconductor device according to another aspect of the present invention has an external reset signal that enables the deep standby mode when the enable signal level is set and allows the deep standby mode to be released when the disable signal level is set. An input reset terminal, a register provided in the logic memory circuit unit, which outputs a first signal for invalidating the external reset signal when the enable signal level is provided, and an interface circuit unit provided with the external reset A Schmitt circuit for inputting a signal and the first signal; an enable signal provided in the interface circuit unit; the signal output from the Schmitt circuit is input; and the first power is supplied to the interface circuit. Level external reset signal and disable signal level When the signal is input to the Schmitt circuit, the second power supplied to the logic memory circuit unit is shut off, and a signal for setting the deep standby mode is output. After the deep standby mode is released A deep standby release circuit that disables the external reset signal and outputs a signal that holds the “ON” state of the second power supply when the first signal of the enable signal level is input to the Schmitt circuit; It is characterized by comprising.

  According to the present invention, it is possible to provide a semiconductor device including a circuit capable of invalidating a command of an external reset signal after execution of canceling a standby mode in which only the interface circuit portion is “ON”.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an LCD (Liquid Crystal Display) driver used in a liquid crystal display device, and FIG. 2 is a diagram showing a relationship between a signal level input to a Schmitt circuit and an output signal level. In this embodiment, the command of the external reset signal is invalidated after executing the reset of the standby mode release circuit in which only the interface circuit portion of the LCD driver is “ON”.

  As shown in FIG. 1, the LCD driver 20 is provided with an input / output circuit unit 1, a logic / memory circuit unit 2, and a reset terminal PadReset. Here, the oscillation circuit, the gate driver, and the source driver are not shown.

  The input / output circuit 1 is provided with a Schmitt circuit 3, a deep standby release circuit 4, a first level shift circuit 5, and a second level shift circuit 8, and is supplied with, for example, 5V power when the power is turned on. . Here, a system interface circuit for connecting to a microprocessor (MPU) is not shown.

  The logic memory circuit section 2 is provided with a regulator circuit 6 and a register, and is supplied with 1.5V power, for example, by stepping down 5V power. Here, a display register circuit, a display RAM, a timing generation circuit, a gate control circuit, a latch circuit, and the like are not shown.

  The Schmitt circuit 3 is provided between the reset terminal PadReset and the deep standby release circuit 4 and includes a two-input NAND circuit NOR1 and an inverter INV1.

  The 2-input NAND circuit NOR1 is provided between the reset terminal PadReset and the inverter INV1, and receives the signal of the node N1 that is an external reset signal and the signal of the node N8 output from the second level shift circuit via the reset terminal PadReset. The input and logically operated signal is output to the output side node N2.

  The inverter INV1 is provided between the 2-input NAND circuit NOR1 and the deep standby release circuit 4, and receives the signal of the node N2 and outputs the inverted signal to the output-side node N3. Here, the Schmitt circuit 3 functions as input signal selection means.

  The deep standby release circuit 4 is provided between the inverter INV1 and the first level shift circuit 5, and inputs the signal of the node N3 and the command signal 1. Signal processing is performed based on the signal of the node N3 or the command signal 1, and the signal of the node N4 is output to the output side.

  The first level shift circuit 5 is provided between the deep standby release circuit 4 and the regulator circuit 6 and inputs the signal of the node N4 which is a 5V signal level and adapts to the operation of the logic / memory circuit section 2. , A signal level-shifted to a 1.5V signal level is output as a signal at node N5.

  The regulator circuit 6 is provided between the first level shift circuit 5 and the register 7 and receives the signal of the node N5, and supplies power to the logic memory circuit 2 or performs power-off operation according to the signal level of the node N5. And outputs the signal of the node N6 to the output side when power is supplied.

  The register 7 is provided between the regulator circuit 6 and the second level shift circuit 8, has at least 1 bit of data for invalidating the external reset signal, and inputs the node N 6 and the command signal 2. Signal processing is performed based on the signal of the node N6 or the command signal 2, and the signal of the node N8 is output to the output side. Here, the register 7 functions as an external reset signal invalidating means.

  The second level shift circuit 5 is provided between the register 7 and the two-input NOR circuit NOR1, and receives the signal of the node N7 having a signal level of 1.5V system and adapts to the operation of the input / output circuit unit 1. A signal level-shifted to a 5V signal level is output as a signal at node N8.

  As shown in FIG. 2, when the signal of the node N1 input to the two-input NOR circuit NOR1 is “High” level and the signal level of the node N8 is “High” level, the signal of the node N2 is “Low” level. The signal level of the node N3 becomes “High”. Therefore, the deep standby release circuit 4 becomes “inactive”, the power is supplied to the logic / memory circuit section 2, and the logic / memory circuit section 2 performs various operations. Note that “inactive” means that a deep standby mode is set by release key control.

  Next, when the signal of the node N1 input to the two-input NOR circuit NOR1 is “High” level and the signal level of the node N8 is “Low” level, the signal of the node N2 is “Low” level and the signal level of the node N3 Becomes “High”. Therefore, the deep standby release circuit 4 becomes “inactive”, the power is supplied to the logic / memory circuit section 2, and the logic / memory circuit section 2 performs various operations.

  Subsequently, when the signal of the node N1 input to the two-input NOR circuit NOR1 is “Low” level and the signal level of the node N8 is “High” level, the signal of the node N2 is “Low” level and the signal level of the node N3 Becomes “High”. Therefore, the deep standby release circuit 4 becomes “inactive”, the power is supplied to the logic / memory circuit section 2, and the logic / memory circuit section 2 performs various operations.

  When the signal of the node N1 input to the 2-input NOR circuit NOR1 is “Low” level and the signal level of the node N8 is “Low” level, the signal of the node N2 is “High” level and the signal level of the node N3 is “Low”. For this reason, the deep standby release circuit 4 becomes “active” and no power is supplied to the logic memory circuit portion 2. Note that “active” means to release the deep standby mode.

  Here, when the signal of the node N1 that is the external reset signal is at the “Low” level, the signal is the enable signal level (hereinafter, the enable signal level is referred to as the “enable” signal level), and the signal of the node N1 that is the external reset signal “High” level, the “enable” signal level for resetting the deep standby mode release circuit is set, but the present invention is not limited to this. For example, an inverter is provided between the reset terminal PadReset and the two-input NOR circuit NOR1. When the signal of the node N1, which is an external reset signal, is at “High” level, the “enable” signal level is set. When the signal of the node N1, which is an external reset signal, is at “High” level, a deep standby mode release circuit is provided. “Enab” to reset It may be the “le” signal level.

  Next, power setting of the LCD driver will be described with reference to FIG. 3. FIG. 3 is a schematic diagram showing power setting of the liquid LCD driver.

  As shown in FIG. 3, when an external power supply ExVdd having a voltage in the range of 2.3 to 2.9 V is supplied from the outside to the LCD driver 20, a plurality of internal power supplies provided in the LCD driver 20 are “ON”. For example, the first internal power supply is “ON”, and the external power supply ExVdd is supplied to the interface circuit unit 1 or the second internal power supply. The second internal power supply is stepped down to a stable voltage of 1.5 V by the step-down circuit and supplied to the logic memory circuit section 2 (second internal power supply). The second internal power supply is boosted to a relatively high voltage such as a high potential side power supply VGH voltage or a low potential side power supply VGL voltage for operating a TFT (Thin Film Transistor) by a booster circuit, and the gate driver section is supplied with power. (Third internal power supply) is supplied.

  Next, the deep standby mode of the LCD driver will be described with reference to FIGS. FIG. 4 is a flowchart showing the setting of the deep standby mode of the LCD driver, and FIG. 5 is a flowchart showing the release of the deep standby mode of the LCD driver.

  As shown in FIG. 4, in the setting of the deep standby mode, first, an external power supply ExVdd having a voltage in the range of 2.3 to 2.9 V is supplied from the outside to the LCD driver 20 (step S1). Next, the first to third internal power supplies (power supply circuits) are turned “ON”, the 5 V power source that is boosted from the internal second power source is supplied to the source driver unit, and the 1.5 V power source that is stepped down is The voltage supplied to the memory circuit unit 2 and boosted is supplied to the gate driver unit (step S2).

  Subsequently, since the interface circuit unit 1 starts operating and the register 7 is not operating, the output signal of the node N7 is at the “Low” level. Through the reset terminal PadReset, an “low” level external reset signal that is an “enable” signal level and a “low” level signal at the node N8 are input to the Schmitt circuit 3, the deep standby release circuit 4 is reset, and the logic A signal for setting the memory circuit unit 2 to a deep standby is output (step S3).

  Next, the regulator circuit 6 inputs this signal and cuts off the power supply to the logic memory circuit unit 2. Note that the power supply to the source driver unit and the gate driver unit is also cut off based on this signal. In this manner, the deep standby release circuit 4 is reset by the external reset signal at the “enable” signal level, and a signal for setting the deep standby is output, thereby surely entering the “deep standby mode” (step S4).

  In the “deep standby mode”, power is supplied only to the interface circuit unit 1, so that power consumption can be reduced. Note that when the signal at the node N8 is at the “Low” level and the signal at the node N1 is at the “High” level of the disable signal level (hereinafter, the disable signal level is referred to as the “disable” signal level). The “standby mode” is released by release key control, and power is supplied to the logic / memory circuit unit 2, the source driver unit, and the gate driver unit.

  As shown in FIG. 5, in the release of the deep standby mode, first, when the external reset signal is “High” level of the “disable” signal level, the command signal 1 is input to the deep standby release circuit 4 to set the command, The deep standby release circuit 4 outputs an “ON” command signal to the regulator circuit 6 (step S11). Next, based on this signal, the regulator circuit 6 is turned “ON” and power supply to the logic memory circuit section 2 is started. Note that power is also supplied to the source driver unit and the gate driver unit (step S12).

  Subsequently, after power is supplied to the register 7, the register 7 inputs the signal of the node N6 output from the regulator circuit 6, and based on this signal, the register 7 has a “High” level for invalidating the command of the external reset signal. The signal is output to the node N7 on the output side (step S13).

  Then, the 2-input NOR circuit NOR1 receives the “High” level signal of the node N8, and the signal output from the Schmitt circuit 3 becomes the “High” level. As shown in FIG. 2, this level does not depend on the signal level (“High” level or “Low” level) of the node N1 (step S14).

  Next, this signal is input to the deep standby release circuit 4, and the deep standby release circuit 4 becomes "inactive". For this reason, the previous setting state set by the command signal 1 is held (step S15).

  To release from the reset prohibited state after a plurality of internal power supplies have started, the command signal 2 is input to the register 7 to set the command, and the signal level of the node N7 is set to the “Low” level (“disable” signal level). This is possible. Other than that, it is impossible to cancel the reset prohibition state, so that it is possible to eliminate the influence of an unexpected external reset signal and provide a stable operation mode.

  Here, the source driver and the gate driver are provided in the LCD driver 20, but for example, the present invention can be applied to an LCD driver in which a gate driver is provided on the liquid crystal display side using a low-temperature poly-Si TFT and only the source driver is incorporated. Further, it can be applied to an LCD driver having only a gate driver. In addition, a semiconductor memory device having a power down mode (also referred to as a sleep mode) in which only an interface circuit portion (also referred to as an input / output circuit portion) is “ON” after power-on to reduce power consumption, SoC (System on a chip) and microcomputers can also be applied.

  As described above, in the semiconductor device of this embodiment, the input / output circuit unit 1, the logic / memory circuit unit 2, and the reset terminal PadReset are provided. The input / output circuit 1 is provided with a Schmitt circuit 3, a deep standby release circuit 4, a first level shift circuit 5, and a second level shift circuit 8 comprising a two-input NOR circuit NOR1 and an inverter INV1, and a logic memory The circuit unit 2 is provided with a regulator circuit 6 and a register 7. After the deep standby mode is canceled, a plurality of internal power supplies are turned “ON”, and power is supplied to the logic / memory circuit unit 2, the source driver unit, and the gate driver. Then, the register 7 operates and a reset prohibition signal is output from the register 7. A two-input NOR circuit NOR1 is input. Based on this signal, the deep standby release circuit 4 becomes "inactive".

  For this reason, after power is supplied to the logic / memory circuit unit 2, the source driver unit, and the gate driver, even if an external reset signal is input, the command of the external reset signal is invalidated and the stable operation mode is maintained. Can do. Also, in the past, in the noise test and product test of liquid crystal display devices equipped with LCD drivers and LCD drivers, an unexpected external reset signal may cause a deep standby mode, and the image display may deteriorate from a predetermined one. In the present embodiment, since the deep standby mode is not set, it is not necessary to cancel the reset each time, and the decrease in test efficiency can be suppressed.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, the embodiment can be applied to a display device driver compatible with FED (Field Emission Display) or ELD (Electroluminescent Display) that performs display by performing SCAN for each line as in the LCD.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) Provided in the logic memory circuit section, a reset terminal to which an external reset signal is input to enable deep standby mode when enable signal level and deep standby mode can be canceled when disable signal level, A register that outputs a first signal that invalidates the external reset signal when the enable signal level is set; a two-input NOR circuit that is provided in the interface circuit unit and inputs the external reset signal and the first signal; A Schmitt circuit configured by an inverter that inverts a signal output from the two-input NOR circuit, and a signal that is provided in the interface circuit unit and that is output from the Schmitt circuit is input to the interface circuit. After the supply of the enable signal level When a reset signal and a first signal having a disable signal level are input to the Schmitt circuit, the second power supplied to the logic / memory circuit unit is shut off and a signal to enter a deep standby mode is output. When the external reset signal is at a disable signal level and a command signal is input, a signal for starting the second power supply is output to cancel the deep standby mode, and the first signal at the enable signal level And a deep standby release circuit that outputs a signal that disables the external reset signal and holds the “ON” state of the first and second power supplies when the signal is input to the Schmitt circuit.

1 is a block diagram showing an LCD driver used in a liquid crystal display device according to Embodiment 1 of the present invention. The figure which shows the relationship between the signal level input into the Schmitt circuit which concerns on Example 1 of this invention, and the signal level output. FIG. 3 is a schematic diagram illustrating voltage setting of the LCD driver according to the first embodiment of the present invention. 6 is a flowchart showing setting of a deep standby mode of the LCD driver according to the first embodiment of the present invention. 6 is a flowchart showing the release of the deep standby mode of the LCD driver according to the first embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Interface circuit part 2 Logic memory circuit part 3 Schmitt circuit 4 Deep standby release circuit 5 1st level shift circuit 6 Regulator circuit 7 Register 8 2nd level shift circuit 20 LCD driver INV1 Inverter N1-N8
NOR1 2-input NOR circuit PadReset Reset terminal

Claims (5)

A reset terminal to which an external reset signal is input to enable deep standby mode when the enable signal level is set and to cancel deep standby mode when the disable signal level is set;
An external reset signal invalidating means for outputting a first signal for invalidating the external reset signal at an enable signal level;
An input signal selecting means provided in an interface circuit section for inputting the external reset signal and the first signal;
The interface circuit unit is provided with a signal output from the input signal selection means, and after the first power is supplied to the interface circuit, the external reset signal at the enable signal level and the disable signal level. When the first signal is input to the input signal selecting means, the internal second power supply is turned “OFF” to output the signal to enter the deep standby mode, and after the deep standby mode is released, the enable signal A deep standby release circuit that outputs a signal that disables the external reset signal and holds the "ON" state of the second power supply when the first signal of the level is input to the input signal selection unit;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the external reset signal invalidating unit is provided with a second power supply and provided in a logic memory circuit unit.   The input signal selection means is a Schmitt circuit comprising a two-input NOR circuit that inputs the external reset signal and the first signal, and an inverter that inverts a signal output from the two-input NOR circuit. The semiconductor device according to claim 1, wherein the semiconductor device is characterized.   The semiconductor device according to claim 1, wherein the external reset signal invalidating unit is a register. A reset terminal to which an external reset signal is input to enable deep standby mode when the enable signal level is set and to cancel deep standby mode when the disable signal level is set;
A register that is provided in the logic memory circuit unit and outputs a first signal that invalidates the external reset signal at the enable signal level;
A Schmitt circuit that is provided in an interface circuit section and inputs the external reset signal and the first signal;
After the signal output from the Schmitt circuit is input to the interface circuit unit and the first power is supplied to the interface circuit, the external reset signal at the enable signal level and the first signal at the disable signal level When the signal is input to the Schmitt circuit, the second power supplied to the logic memory circuit unit is shut off, and a signal for setting the deep standby mode is output. After the deep standby mode is released A deep standby release circuit that disables the external reset signal and outputs a signal that holds the “ON” state of the second power supply when the first signal of the enable signal level is input to the Schmitt circuit; ,
A semiconductor device comprising:

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