JP2011180770A - Memory control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately hold storage contents of a memory even when a power supply voltage drops, in a memory control device controlling the memory having a self-refresh function. <P>SOLUTION: When the power supply voltage of +24 V drops, a detection signal sdbkupn becomes HIGH (1), and a reboot signal req_reboot becomes HIGH according thereto (2). Then, a signal self_refresh becomes HIGH (3), and a self-refresh operation is instructed to an SDRAM (Synchronous Dynamic Random Access Memory) 9 through an SDRAM controller 33. A signal reboot_output_n becomes LOW according to the reboot signal req_reboot (4). Then, a signal b_watch_in_n, a signal rst_rstctl_n, and a signal rst_cpu_n sequentially become LOW, and a monitoring block 35, a reset controller 37, and a CPU 31 are sequentially reset. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a memory control device that controls a memory, and more particularly to a memory control device that controls a memory having a self-refresh function.

  Conventionally, a memory such as an SDRAM (Synchronous Dynamic Random Access Memory) requires a refresh operation due to the configuration of a memory cell. Further, when the memory is not read or written such as in the power saving mode, the stored contents are held in a refresh mode called self-refresh. In addition, as a memory control device for controlling this type of memory, when the power saving mode is set by the power down signal, the SDRAM is instructed to perform a self-refresh operation, and then the power supply to the CPU or the like is stopped. Some have been proposed (see, for example, Patent Document 1).

  In this case, when setting the power saving mode in which the power supply to the CPU or the like is stopped and the access to the SDRAM by the CPU or the like is stopped, the self refresh operation is instructed to the SDRAM. The stored contents can be retained.

JP 2006-4108 A

  However, in Patent Document 1, a self-refresh operation is instructed to the SDRAM through the processing of the CPU when the power saving mode is set. In this case, when a drop in power supply voltage is transmitted to the CPU due to an abnormality or the like, the CPU accesses the SDRAM or the like and performs interrupt processing, whereby the CPU instructs the SDRAM to perform a self-refresh operation.

  If the time required for interrupt processing by the CPU is longer than the time required for the power supply voltage to drop to a voltage necessary for driving the CPU, the CPU cannot instruct the SDRAM to perform a self-refresh operation. The stored contents cannot be retained.

  Therefore, the present invention has been made for the purpose of accurately holding the stored contents of the memory even in the case where the voltage of the power supply is lowered, in the memory control device that controls the memory having the self-refresh function.

  The present invention made to achieve the above object is a memory control device for controlling a memory having a self-refresh function, wherein a drive voltage generation unit that generates a drive voltage of a constant value from a power source, and the drive voltage generation unit A CPU that is driven by the generated drive voltage and can access the memory, and the drive voltage generation unit has a value that is greater than or equal to a value necessary for the drive voltage generation unit to generate the constant drive voltage from the power supply. A power supply voltage detection unit configured to output a detection signal when a threshold value that is less than the lowest voltage in the error range of the voltage value is set and detects a voltage of the power supply that is less than the set threshold value, and the power supply voltage detection unit Outputs a refresh signal that instructs the memory to perform a self-refresh operation and a stop signal that instructs the CPU to stop. It is characterized with the control unit, further comprising a that.

  In the memory control device of the present invention configured as described above, the drive voltage generation unit generates a constant drive voltage from the power source, and the CPU that can access the memory is driven by the drive voltage. The power supply voltage detection unit outputs a detection signal when the voltage of the power supply becomes less than a predetermined threshold value. The threshold is not less than the value necessary for the drive voltage generator to generate the constant drive voltage from the power supply, and less than the minimum voltage in the error fluctuation range of the power supply voltage value. A threshold value is set. When the power supply voltage detection unit outputs the detection signal, the control unit outputs a refresh signal that instructs the memory to perform a self-refresh operation and a stop signal that instructs the CPU to stop.

  Thus, according to the present invention, when the voltage of the power supply becomes less than the threshold value, the memory can be instructed through the control unit and the CPU can be stopped. The control unit is independent of the CPU that can access the memory. For this reason, in the memory control device of the present invention, even when the power supply voltage drops below the threshold value, the stored contents of the memory can be accurately held by instructing the SDRAM to perform a self-refresh operation. In addition, by outputting a stop signal for stopping the CPU, it is possible to prevent malfunction caused by the CPU accessing the memory.

  The control unit includes a monitoring unit that outputs a reboot signal when the power supply voltage detection unit outputs the detection signal for a certain period, and a refresh signal and the stop when the monitoring unit outputs the reboot signal. And a reset controller unit that outputs a signal. In this case, when the power supply voltage detection unit outputs the detection signal for a certain period, the monitoring unit outputs a reboot signal, and the reset controller unit outputs the refresh signal and the stop signal accordingly. For this reason, when the detection signal is temporarily output due to some error or noise, the refresh signal and the stop signal are not output, and the stability of control by the memory control device can be ensured.

  In this case, when the monitoring unit outputs the reboot signal, the reset controller unit outputs the refresh signal and a monitoring unit reset signal for resetting the monitoring unit, and the monitoring unit is configured to output the reset controller. When the unit outputs the monitoring unit reset signal, it outputs a controller reset signal that resets the reset controller unit, and initializes and stops itself, and the monitoring unit resets the controller reset signal. The above stop signal may be output and may be initialized and stopped.

  In this case, when the detection signal is output for a certain period and the monitoring unit outputs the reboot signal, the reset controller unit outputs the refresh signal and a monitoring unit reset signal for resetting the monitoring unit. Then, the monitoring unit outputs a controller reset signal for resetting the reset controller unit in response to the monitoring unit reset signal, and initializes and stops itself. For this reason, when the reboot signal is output, the above-described refresh signal is output, and the monitoring unit is stopped in an initialized state. When the monitoring unit outputs the controller reset signal, the reset controller unit outputs the stop signal and initializes itself to stop. For this reason, when the reboot signal is output, the above-described stop signal is output, and the reset controller unit is stopped in an initialized state.

  Therefore, when the memory control device is restarted after the reboot signal is output and the self-refresh operation and the CPU are stopped, the monitoring unit and the reset controller unit are initialized. Will be restarted. Therefore, the process at the time of restart can be executed more smoothly. The drive voltage generation unit may be configured with a DC / DC converter.

1 is a block diagram schematically illustrating a configuration of a memory control device to which the present invention is applied. 4A and 4B are diagrams illustrating an operation when the power supply voltage of the memory control device is lowered, where FIG. 5A is an explanatory diagram illustrating a change in power supply voltage, and FIG. 5B is a time chart illustrating a change in each signal.

[Configuration of memory controller]
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram schematically showing the configuration of a memory control device 1 to which the present invention is applied. The memory control device 1 to which the present invention is applied is used to control a memory used in an image forming apparatus that forms an image on a sheet or the like by, for example, electrophotography.

  As shown in FIG. 1, the memory control device 1 of the present embodiment is mainly configured by an ASIC 3, and the ASIC 3 includes a DC / DC converter 5 (drive voltage generation) from a + 24V DC power supply (an example of a power supply). DC voltage of +3.3 V as an example of the drive voltage generated by the example of the unit is supplied. The + 24V DC power supply may be generated by rectifying from a commercial AC power supply, and the + 24V voltage is supplied as a drive voltage for the printer engine or the like (not shown) of the image forming apparatus described above. May be.

  In addition, a power supply voltage detection circuit 7 (an example of a power supply voltage detection unit) is connected to the + 24V power supply, and the following detection signal sdbkupn is input to the ASIC 3. That is, as shown in FIGS. 2A and 2B, the detection signal sdbkupn is HIGH when the voltage of the power source is higher than a predetermined threshold value VTH, and the voltage of the power source is higher than the threshold value VTH. Is low, the signal is LOW. Here, the threshold value VTH is equal to or greater than a value necessary for the DC / DC converter 5 to generate a + 3.3V DC voltage from the power source, and is within a normal fluctuation range of the voltage value of the power source. The minimum voltage is set to a value less than VM.

  In the case of the image forming apparatus, the voltage required for the printer engine to form an image is 24V, and the memory control apparatus 1 operates based on the voltage. The memory control device 1 operates in accordance with the clock signal, and many logic circuits operate at the moment when the clock signal changes. Therefore, the power supply needs to supply a large amount of current to the memory control device 1 instantaneously. This is the cause of the voltage fluctuation of the power supply, and the range of the fluctuation is the error range of the voltage of the power supply.

  The ASIC 3 is connected to an SDRAM 9 as an example of a memory having a self-refresh function and to which a + 3.3V DC voltage is applied from a secondary power source independent of the power source. The CPU 31 incorporated in the ASIC 3 is configured to be able to access the SDRAM 9 via an SDRAM controller (SDRAMCTL) 33 also incorporated in the ASIC 3. The SDRAM 9 stores the contents read and written by the CPU 31, but requires a refresh operation due to the structure of the SDRAM memory cell. In the power saving mode, when the SDRAM 9 receives the self-refresh control signal from the SDRAM controller 33, the SDRAM 9 replenishes charges with the voltage supplied from the secondary power supply and holds the stored contents. When the SDRAM 9 is in the self-refresh state, the CPU 31 cannot access the SDRAM 9 and cannot read / write the stored contents.

  Further, the ASIC 3 includes a reset / SDBKUPN monitoring block (an example of a monitoring unit: hereinafter simply referred to as a monitoring block) 35 and a reset controller 37 (an example of a reset controller unit). Note that the monitoring block 35 and the reset controller 37 are both configured by a logic circuit, and both correspond to an example of a control unit.

  The + 3.3V DC voltage generated by the DC / DC converter 5 is also input to the reset IC 41. The reset IC 41 outputs a signal output_rstic, which becomes HIGH after a predetermined delay time when the input voltage to the reset IC 41 exceeds 3.3 V after power-on. The signal output_rstic is input to an AND 43 that is a logical OR of negative logic together with a signal reboot_output_n described later output from the reset controller 37.

  The output of the AND 43 is input as a signal b_watch_in_n to the monitoring block 35 together with the detection signal sdbkupn output from the power supply voltage detection circuit 7 described above. The signal b_watch_in_n is also a LOW active reset signal for the monitoring block 35. Then, the monitoring block 35 outputs a reboot signal req_reboot to the reset controller 37 based on the detection signal sdbkupn and a signal rst_rstctl_n (an example of a controller reset signal) based on the signal b_watch_in_n. That is, the reboot signal req_reboot is a signal that is HIGH for a certain period when the detection signal sdbkupn continues to be LOW for a certain period. The signal rst_rstctl_n is a LOW active signal for resetting the reset controller 37, and becomes LOW when the detection signal sdbkupn and the signal b_watch_in_n are both LOW, and HIGH otherwise.

  Based on the reboot signal req_reboot and the signal rst_rstctl_n, the reset controller 37 outputs the following signal reboot_output_n (an example of a monitoring unit reset signal) and a signal self_refresh (an example of a refresh signal). That is, the signal reboot_output_n is a LOW active restart reset signal input to the AND 43 described above. When the reboot signal req_reboot becomes HIGH, the signal reboot_output_n becomes LOW. The signal self_refresh is a self-refresh control signal input to the SDRAM controller 33. When the reboot signal req_reboot becomes HIGH, the signal self_refresh becomes HIGH for a certain period. Further, the reset controller 37 inputs a signal rst_cpu_n (an example of a stop signal) that becomes LOW when the reset controller 37 is reset to the CPU 31. The signal rst_cpu_n is a LOW active reset signal that initializes the CPU 31 that becomes valid when the CPU 31 is LOW.

[Operation of memory controller]
Next, the operation of the memory control device 1 will be described by taking as an example a case where the voltage of the power supply is lowered due to the interruption of the power supply or some abnormality. FIG. 2A is an explanatory diagram illustrating a change in the voltage of the power supply in that case, and FIG. 2B is a time chart illustrating a change in each signal in that case.

  As shown in FIGS. 2A and 2B, when the power supply voltage (supply voltage) is maintained at +24 V, the detection signal sdbkupn, the signal reboot_output_n, the signal b_watch_in_n, the signal rst_rstctl_n, the signal rst_cpu_n, and the signal output_rstic The reboot signal req_reboot and the signal self_refresh are set to LOW. At this time, the CPU 31 is operating, and the CPU 31 can access the SDRAM 9.

  When the voltage of the power source decreases and falls below the threshold value VTH, the detection signal sdbkupn becomes LOW (1). When the detection signal sdbkupn continues to be LOW for a certain period, the reboot signal req_reboot becomes HIGH for a certain period (2). Note that the fixed period from (1) to (2) is about several milliseconds (see FIG. 2B).

  Then, when the reboot signal req_reboot becomes HIGH, the signal self_refresh becomes HIGH for a certain period (3). Thus, when the signal self_refresh input to the SDRAM controller 33 as the self-refresh control signal becomes HIGH, the SDRAM 9 is instructed to perform a self-refresh operation, and the SDRAM 9 enters a self-refresh state and the CPU 31 becomes inaccessible.

  Further, as described above, when the reboot signal req_reboot is HIGH, the signal reboot_output_n is also LOW (4). Then, the signal b_watch_in_n becomes LOW (5), the monitoring block 35 is reset, and the signal rst_rstctl_n (LOW active) for resetting the reset controller 37 also becomes LOW (6). As a result, the reset controller 37 is also reset, and the signal rst_cpu_n (LOW active) for resetting the CPU 31 also becomes LOW (7). For this reason, CPU31 transfers to the reset state from the operation state until then.

  Further, by resetting the reset controller 37 in this way, the signal reboot_output_n becomes HIGH in the initial state (7), and accordingly, the signal b_watch_in_n also becomes HIGH in the initial state (8). If the voltage of the power supply further decreases and falls below VDC, the DC / DC converter 5 cannot generate the voltage of + 3.3V that drives the ASIC 3, so that the signal output_static as well as the signal reboot_output_n and the signal b_watch_in_n become LOW. .

[Effect of this embodiment and its modification]
As described above, in the present embodiment, when the voltage of the power supply becomes less than the threshold value VTH, the SDRAM 9 performs self refresh, and the CPU 31 can be reset (initialized) and stopped. The monitoring block 35 and the reset controller 37 that perform such processing are independent of the CPU 31 that can access the SDRAM 9. Therefore, in the memory control device 1 of the present embodiment, when the power supply voltage drops below the threshold value VTH, the SDRAM 9 enters the self-refresh state, and the stored contents of the SDRAM 9 can be accurately retained.

  The CPU 31 itself does not instruct the SDRAM 9 to enter the self-refresh state, but the SDRAM 9 enters the self-refresh state based on the detection signal sdbkupn output from the power supply voltage detection circuit 7. In the present embodiment, the SDRAM 9 performs a self-refresh operation, and the CPU 31 is reset (initialized) and stopped in order to prevent malfunction due to the CPU 31 accessing the SDRAM 9 during self-refresh.

  In addition, the self-refresh operation and the resetting of the CPU 31 are executed when the detection signal sdbkupn that becomes LOW when the voltage of the power supply becomes less than the threshold value VTH continuously becomes LOW for a certain period. For this reason, when the detection signal sdbkupn temporarily becomes LOW due to some error or noise, the self-refresh operation and the CPU 31 are not stopped, and the control stability by the memory control device 1 can be ensured. it can.

  When the detection signal sdbkupn is continuously LOW for a certain period and the reboot signal req_reboot is output, the self-refresh operation and the reset of the CPU 31 are performed, as well as the monitoring block 35, the reset controller. 37 also stops in a reset (initialized) state. Therefore, when the memory control device 1 is restarted after the reboot signal req_reboot is output and the self-refresh operation and the CPU 31 are reset, the monitoring block 35 and the reset controller 37 are initialized. It will be restarted. Therefore, the process at the time of restart can be executed more smoothly.

  In addition, this invention is not limited to the said embodiment at all, It can implement with a various form in the range which does not deviate from the summary of this invention. For example, the drive voltage generation unit is not necessarily configured by a DC / DC converter, and may be configured by using a regulator or the like. The monitoring block 35 and the reset controller 37 may be configured as an integrated element. However, when the monitoring block 35 and the reset controller 37 are configured as separate elements as in the above embodiment and signals for resetting them are mutually output, the respective units are initialized as described above. The effect of facilitating the processing by restarting from the state can be obtained more reliably.

DESCRIPTION OF SYMBOLS 1 ... Memory control device 3 ... ASIC
DESCRIPTION OF SYMBOLS 5 ... DC / DC converter 7 ... Power supply voltage detection circuit 9 ... SDRAM 33 ... SDRAM controller 35 ... Reset, SDBKUPN monitoring block 37 ... Reset controller 41 ... Reset IC 43 ... AND
31 ... CPU

Claims (4)

A memory control device for controlling a memory having a self-refresh function,
A drive voltage generator for generating a constant drive voltage from the power supply;
A CPU that is driven by the drive voltage generated by the drive voltage generator and can access the memory;
A threshold that is equal to or greater than a value necessary for the drive voltage generator to generate the constant drive voltage from the power supply and less than the minimum voltage in the error range of the power supply voltage value is set. A power supply voltage detection unit that outputs a detection signal when detecting the voltage of the power supply below the set threshold;
A control unit that outputs a refresh signal that instructs the memory to perform a self-refresh operation and a stop signal that instructs the CPU to stop when the power supply voltage detection unit outputs the detection signal;
A memory control device comprising: The control unit is configured to output a reboot signal when the power supply voltage detection unit outputs the detection signal for a certain period;
A reset controller unit that outputs the refresh signal and the stop signal when the monitoring unit outputs the reboot signal;
The memory control device according to claim 1, further comprising: The reset controller unit outputs the refresh signal and a monitoring unit reset signal for resetting the monitoring unit when the monitoring unit outputs the reboot signal,
The monitoring unit outputs a controller reset signal for resetting the reset controller unit when the reset controller unit outputs the monitoring unit reset signal, and initializes and stops itself,
3. The memory control device according to claim 2, wherein when the monitoring unit outputs the controller reset signal, the reset controller unit outputs the stop signal and initializes itself to stop.   4. The memory control device according to claim 1, wherein the drive voltage generation unit includes a DC / DC converter. 5.