JP2007178451A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device in which a level shifter can be initialized without making a frame period longer and there is no need for an initialization circuit in the outside. <P>SOLUTION: An initialization circuit 15 initializes the level shifter 14 in an effective period of a vertical synchronizing signal Vsync and therefore, there is no need for separately (for example, within a display period) providing an initialization period and consequently the level shifter 14 can be initialized without prolonging the frame period and even more since the vertical synchronizing signal can be used, there is no more need for the initialization circuit on the outside. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device that can initialize a level shifter without lengthening a frame period and does not require an external initialization circuit.

  In an active matrix type liquid crystal display device, a thin film transistor (TFT: Thin Film Transistor) is formed on an array substrate made of glass or the like, and the array substrate and a counter substrate facing this through a liquid crystal layer Display was performed by switching the transistor with a separate driving IC.

  However, in recent years, a drive circuit equivalent to a drive IC is often formed in a substrate with transistors.

  Even in this case, it is desirable to operate the drive circuit in the substrate as it is with the input signal that has been input to the drive IC. However, in some cases, the amplitude of the input signal is amplified due to the limitations in the substrate. There is a need to. Therefore, a level shifter that amplifies the amplitude of the signal is used.

Among the level shifters, particularly, a shift register that operates at high speed gradually varies in threshold value and characteristics of transistors in the shift register due to the effect of high-speed operation. Thereby, for example, a delay that affects the operation occurs. Therefore, such a shift register is initialized in an initialization period provided separately.
JP 2002-174823 A

  However, since the level shifter cannot perform amplitude amplification in the initialization period, there is a problem that the frame period must be lengthened according to the length of the initialization period.

  In addition, initialization of the level shifter requires an external initialization signal to be input, and an initialization circuit for generating the initialization signal is required externally.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal display device that can initialize a level shifter without extending the frame period and does not require an initialization circuit outside. There is.

  In order to solve the above problems, a liquid crystal display device according to the present invention includes a pixel transistor in which a plurality of scanning lines and a plurality of signal lines intersect, and the scanning lines are driven to conduct at each intersection, and the conduction The pixel electrode to which the video signal is written from the signal line is arranged via the pixel transistor, the counter electrode is opposed to the pixel electrode via the liquid crystal layer, and the vertical synchronization signal and the vertical synchronization signal are not effective during the display period. The array substrate is provided with a level shifter that amplifies the amplitude of the input signal and a drive circuit that drives the scanning line and the signal line by the amplified signal. An initializing circuit for initializing the level shifter is formed during an effective period of the vertical synchronizing signal.

  According to the liquid crystal display device of the present invention, since the initialization circuit initializes the level shifter during the effective period of the vertical synchronization signal, there is no need to provide a separate initialization period (for example, within the display period). The level shifter can be initialized without increasing the length. In addition, since a vertical synchronizing signal can be used, an initialization circuit is not required outside. Further, since the vertical synchronization signal is slower than the input signal, the initialization circuit can be configured with a level shifter that does not require initialization.

  According to the present invention, the level shifter can be initialized without increasing the frame period. In addition, since a vertical synchronizing signal can be used, an initialization circuit is not required outside. Further, since the vertical synchronization signal is slower than the input signal, the initialization circuit can be configured with a level shifter that does not require initialization.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a configuration diagram of a liquid crystal display device 1 according to an embodiment of the present invention.

  The liquid crystal display device 1 includes an array substrate 11 made of glass or the like formed so that a plurality of signal lines X and a plurality of scanning lines Y intersect, and a liquid crystal layer (not shown) with respect to the array substrate 11. And a counter substrate 12 made of glass or the like and opposed to each other.

  In the array substrate 11, at each intersection where the signal line X and the scanning line Y intersect, a pixel transistor Q that is turned on by driving the scanning line Y, and a video signal from each signal line X through the turned-on pixel transistor Q. A pixel electrode P to be written is arranged.

  The pixel transistor Q is, for example, a p-Si (polysilicon) type transistor, and its gate, source, and drain are connected to the scanning line Y, the signal line X, and the pixel electrode P, respectively.

  The counter substrate 12 includes one counter electrode (not shown) that faces all of the pixel electrodes P. A liquid crystal capacitor CL is constituted by the pixel electrode P, the liquid crystal layer of the portion, and the counter electrode.

  Further, the liquid crystal display device 1 sequentially drives each scanning line Y, and supplies a video signal to each signal line X, and a scanning line driving circuit 131 that makes the pixel transistor Q connected to the scanning line Y conductive. And a signal line driver circuit 132. The scanning line driving circuit 131 and the signal line driving circuit 132 constitute the driving circuit 13.

  Further, the liquid crystal display device 1 amplifies the amplitude of the dot clock signal CK, the digital data signal D, and the horizontal synchronization signal Hsync input from the outside (each signal is referred to as the input signal IN when these signals are not distinguished). A level shifter 14 for outputting a later output signal OUT to the drive circuit 13 is provided.

  Further, the liquid crystal display device 1 amplifies the amplitude (same as the amplitude of the input signal IN) of the vertical synchronization signal Vsync input to the drive circuit 13 from the outside, the initialization signal VS1 which is the amplified signal, and its inverted signal Is provided with an initialization circuit 15 for outputting the signal VS2 to the level shifter 14. The level shifter 14 and the initialization circuit 15 share a ground point. That is, it has a common reference circuit node.

  Although not shown in FIG. 1, the liquid crystal display device 1 includes power supplies VCC, VDD, and REF with the negative pole grounded. The power supply VCC is a power supply that outputs a positive DC voltage having a magnitude equal to the amplitude of the input signal IN, the power supply VDD is a power supply that outputs a positive DC voltage larger than the amplitude of the input signal IN, and the power supply REF is This is a power supply that outputs a positive DC voltage that is half the amplitude of the input signal IN.

  FIG. 2 is a circuit diagram of the initialization circuit 15. The initialization circuit 15 is a level shifter that amplifies the amplitude of the signal and amplifies the amplitude of the vertical synchronization signal Vsync that is slower than the input signal IN, so that initialization is not necessary. Specifically, the following circuit configuration is provided.

  In the initialization circuit 15, the gates and drains of the P-type transistor Q1 and the N-type transistor Q2 are connected to each other, and the gates and drains of the P-type transistor Q3 and the N-type transistor Q4 are connected to each other. The gate and drains of the type transistor Q6 are also connected.

  The drains of the transistors Q1 and Q2 are connected to the gates of the transistors Q3 and Q4.

  The source of the transistor Q1 is connected to the positive pole (VCC in the figure) of the power supply VCC, and the sources of the transistors Q2, Q4, and Q6 are grounded.

  The vertical synchronization signal Vsync is input to the gates of the transistors Q1, Q2, Q5, and Q6.

  The drain of the P-type transistor Q7 and the source of the transistor Q3 are connected, and the drain of the P-type transistor Q8 and the source of the transistor Q5 are connected.

  The sources of the transistors Q7 and Q8 are connected to the positive pole (VDD in the figure) of the power supply VDD.

  The drains of the transistors Q3 and Q4 are connected to the gate of the transistor Q8, and a voltage signal VS1 (initialization signal) at this voltage is output to the level shifter 14 in FIG.

  The drains of the transistors Q5 and Q6 are connected to the gate of the transistor Q7, and a voltage signal VS2 (inverted signal of the initialization signal) at this voltage is output to the level shifter 14 in FIG.

  FIG. 3 is a circuit diagram of a part of the level shifter 14. This circuit is provided for each input signal IN.

  The switches SW1, SW2, SW3, and SW4 are two-terminal switches that are opened and closed by an initialization signal VS1 and an inverted signal VS2.

  An input signal IN is given to one end of the switch SW1, and the other end is connected to the circuit node A.

  One end of the switch SW2 is connected to the positive pole (REF in the figure) of the power supply REF, and the other end is connected to the circuit node A.

  One pole of the capacitor C1 is connected to the circuit node A.

  One end of the switch SW3 and the gates of the P-type transistor Q11 and the N-type transistor Q12 are connected to the circuit node B to which the other pole of the capacitor C1 is connected. The source of the transistor Q11 is connected to the positive pole of the power supply VDD, and the source of the transistor Q12 is grounded.

  The other end of the switch SW3 is connected to a circuit node C, to which the drains of the transistors Q11 and Q12 and one end of the switch SW4 are connected.

  The circuit node D to which the other end of the switch SW4 is connected is connected to the drain of the transistor Q13 and the input end of the inverter INV1. The source of the transistor Q13 is connected to the positive pole of the power supply VDD, and the signal VS1 is input to the gate.

  The output signal OUT of the inverter INV1 is output to the drive circuit 13 in FIG.

(Operation of this embodiment)
FIG. 4 is a timing chart used in the liquid crystal display device 1.

  In the effective period of the vertical synchronization signal Vsync, that is, the period when the level is the ground (GND) level, the transistors Q1 and Q5 in FIG. 2 are turned on and the transistors Q2 and Q6 are turned off.

  When the transistor Q1 is turned on, the transistor Q4 is turned on.

  When the transistor Q4 is turned on, the level of the initialization signal VS1 becomes the GND level.

  Thereby, the transistor Q8 is turned on. Since the transistor Q5 is turned on and the transistor Q6 is turned off, the level of the inverted signal VS2 becomes the level of the positive pole (VDD level) of the power supply VDD. As a result, the transistors Q7 and Q3 are turned off.

  That is, as shown in FIG. 4, in the effective period of the vertical synchronization signal Vsync, the level of the initialization signal VS1 becomes the GND level, and the level of the inverted signal VS2 becomes the VDD level.

  Accordingly, the switches SW1 and SW4 shown in FIG. 3 are opened (opened), the switches SW2 and SW3 are closed (closed), and the transistor Q13 is turned on.

  When the switch SW2 is closed, the circuit node A becomes the level of the power supply REF (REF level).

  As a result, the circuit node B that was at the GND level or the VCC level becomes the REF level.

  Further, the charge between the gate and drain of the transistors Q11 and Q12 is discharged through the closed switch SW3.

  Further, when the level of the signal VS1 becomes the GND level, the circuit node D becomes the VDD level, and the output signal OUT becomes the GND level.

  That is, as shown in FIG. 4, during the effective period of the vertical synchronization signal Vsync, the output signal OUT is at the GND level regardless of the level of the input signal IN.

  Furthermore, since the circuit node A becomes the REF level and the charge between the gates and the drains of the transistors Q11 and Q12 is discharged, the level shifter 14 is initialized, so the level of the initialization signal VS1 is the GND level. This period is a period during which the initialization signal is valid.

  2 is turned off and the transistors Q2 and Q6 are turned on while the vertical synchronizing signal Vsync is not valid, that is, when the level of the vertical synchronizing signal Vsync is the VCC level.

  When the transistor Q6 is turned on, the level of the inverted signal VS2 becomes the GND level.

  Thereby, the transistor Q7 is turned on.

  Transistor Q7 is turned on, while transistor Q2 is turned on, so transistor Q3 is turned on and transistor Q4 is turned off. As a result, the level of the initialization signal VS1 becomes the VDD level.

  As a result, the transistor Q8 is turned off. On the other hand, since the vertical synchronization signal Vsync is at the VCC level, the transistor Q5 is turned off.

  That is, as shown in FIG. 4, during the period when the vertical synchronization signal Vsync is not valid, the level of the initialization signal VS1 becomes the VDD level, and the level of the inverted signal VS2 becomes the GND level.

  As a result, the switches SW1 and SW4 shown in FIG. 3 are closed, the switches SW2 and SW3 are opened, and the transistor Q13 is turned off.

  By closing the switch SW1, the input signal IN is given to the circuit node A.

  As a result, the circuit node B that has been at the REF level becomes the same level as the level of the input signal IN.

  When the input signal IN is at the VCC level, the transistor Q11 is turned off and the transistor Q12 is turned on, so that the circuit nodes C and D are at the GND level. On the other hand, when the input signal IN is at the GND level, the transistor Q11 is turned on and the transistor Q12 is turned off.

  The output signal OUT is at the VDD level when the circuit nodes C and D are at the GND level, and is at the GND level when the circuit nodes C and D are at the VDD level.

  That is, as shown in FIG. 4, during the period when the vertical synchronization signal Vsync is not valid, the output signal OUT also changes from the GND level to the VDD level at the timing when the input signal IN changes from the GND level to the VCC level, and the input signal IN changes to the GND level. At the timing when the level is reached, the output signal OUT also becomes the GND level.

  Further, the period in which the vertical synchronization signal Vsync is not valid is also a display period in which the input signal IN is valid, and the following display is performed in the display period. In this period, for example, a DC voltage having a constant voltage is applied to the counter electrode.

  The first horizontal signal starts when the output signal OUT (for convenience, the horizontal synchronization signal Hsync) from the circuit that amplifies the amplitude of the horizontal synchronization signal Hsync, which is one of the input signals IN, becomes valid first. In the scanning period, the scanning line driving circuit 131 in FIG. 1 drives the outermost (first) scanning line Y. On the other hand, the signal line driving circuit 132 has a voltage corresponding to the value of the first column in the image to be displayed (given by the output signal OUT from each circuit in which the amplitude of the digital data signal D and the dot clock signal CK is amplified). A video signal is supplied to each signal line X.

  As a result, the pixel transistor Q connected to the first scanning line Y becomes conductive, and a video signal is written to the pixel electrode P connected to the pixel transistor Q. As a result, the amount of light transmitted at each pixel electrode P is in accordance with the written video signal, that is, in accordance with the value of the first column of the image. In this way, the first column of images is displayed.

  In the second horizontal scanning period that starts when the horizontal synchronization signal Hsync becomes valid for the second time, the second column of the image is displayed by the same processing while maintaining the display of the first column. Thereafter, similar processing is sequentially performed, and the last column of the image is displayed in the last horizontal scanning period in the display period. In this way, all the images to be displayed are displayed.

  Moreover, an image is continuously displayed by performing such a display also in each subsequent display period.

  As described above, according to the liquid crystal display device of the present embodiment, the initialization circuit 15 initializes the level shifter 14 during the effective period of the vertical synchronization signal Vsync. The level shifter 14 can be initialized without increasing the frame period. In addition, since a vertical synchronizing signal can be used, an initialization circuit is not required outside. Further, since the vertical synchronization signal is slower than the input signal IN, the operation is not affected if the delay is a little. Therefore, as in the present embodiment, the initialization circuit 15 can be configured with a level shifter that does not require initialization. it can.

1 is a configuration diagram of a liquid crystal display device 1 according to an embodiment of the present invention. 2 is a circuit diagram of an initialization circuit 15. FIG. 5 is a circuit diagram for each input signal in the level shifter 14. FIG. 3 is a timing chart used in the liquid crystal display device 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device 11 ... Array substrate 12 ... Opposite substrate 13 ... Drive circuit 14 ... Level shifter 15 ... Initialization circuit 131 ... Scan line drive circuit 132 ... Signal line drive circuit C1 ... Capacitor CK ... Dot clock signal CL ... Liquid crystal capacitance D ... Digital data signal Hsync ... Horizontal synchronization signal IN ... Input signal INV1 ... Inverter OUT ... Output signal P ... Pixel electrode Q ... Pixel transistors Q1-8, Q11-13 ... Transistor REF ... Power supply VCC ... Power supply VDD ... Power supply Vsync ... Vertical synchronization Signal X ... Signal line Y ... Scan line

Claims (3)

  A plurality of scanning lines and a plurality of signal lines intersect with each other, and at each intersection, a pixel transistor that is driven to conduct by the scanning line, and a pixel electrode to which a video signal is written from the signal line through the conducting pixel transistor, Is disposed, the counter electrode is opposed to the pixel electrode through the liquid crystal layer, and the vertical synchronization signal and the input signal that is effective during the display period when the vertical synchronization signal is not effective are input, and the amplitude of the input signal is amplified. An array substrate having a level shifter and a drive circuit for driving a scanning line and a signal line by an amplified signal is formed, and the array substrate is initialized to initialize the level shifter during an effective period of the vertical synchronization signal A liquid crystal display device in which a circuit is formed.   2. The liquid crystal display device according to claim 1, wherein the initialization circuit is a circuit that amplifies the amplitude of the vertical synchronizing signal and applies an initialization signal that is an amplified signal to the level shifter. The initialization circuit is a circuit that provides the level shifter with an initialization signal that is effective during an effective period of the vertical synchronization signal,
The level shifter is
A P-type thin film transistor in which a negative pole is connected to a reference circuit node of the level shifter, and a positive pole of a power source that outputs a positive DC voltage larger than the amplitude of the input signal is connected to a source;
An N-type thin film transistor having a drain and a gate connected to the drain and gate of the P-type thin film transistor, and a source connected to the reference circuit node;
A capacitor having one pole connected to the gates of the P-type thin film transistor and the N-type thin film transistor;
A switch for providing the input signal to the other pole of the capacitor during a period when the initialization signal is not valid;
A negative pole is connected to the reference circuit node, and a positive pole of a power source that outputs a DC voltage having a magnitude half the amplitude of the input signal is connected to the other pole of the capacitor during a period when the initialization signal is valid A switch to
The liquid crystal display device according to claim 1, further comprising: a switch that connects a gate and a drain of the P-type thin film transistor and the N-type thin film transistor during a period in which the initialization signal is valid.

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