JP2007178160A - Scan flip-flop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a scan flip-flop circuit (scan FF circuit) that has a fixed value input function, relaxes the setup timing condition about data to be input, and relaxes the hold timing condition about a scan-in signal to be input. <P>SOLUTION: In the scan flip-flop circuit, a 2-to-1 selector 13 executes a first selection operation of selecting one of the ground level received by "0" input and "1" input and the scan-in signal SIN based on a scan enable signal SEN received by a control input. A 2-to-1 selector 12 executes a second selection operation of selecting one of data DATA received by "0" input and "1" input and the output from the 2-to-1 selector 13 based on a synchronous reset signal RB received by the control input and outputting it to a data input terminal D as attachment data to the flip-flop 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a scan FF circuit having a scan flip-flop (hereinafter abbreviated as “scan FF”).

  FIG. 43 is a circuit diagram showing an internal configuration of a conventional scan FF circuit. As shown in the figure, the conventional scan FF circuit 51 includes a flip-flop 61 and a 2to1 selector 62, and has a clock terminal P11, a data input terminal P12, a scan-in terminal P13, and a scan enable terminal P14 in the input section. The output unit includes a data output terminal P21, a scan-out terminal P22, and a data output inversion terminal P23.

  The clock terminal P11 receives the clock CLOCK, the data input terminal P12 receives the data DATA, the scan-in terminal P13 receives the scan-in signal SIN, the scan enable terminal P14 receives the scan enable signal SEN, and outputs data from the data output terminal P21. Q, a scan-out signal SOUT is output from the scan-out terminal P22, and an inverted data output QB is output from the data output inversion terminal P23.

  The “0” input and “1” input of the 2to1 selector 62 are connected to the data input terminal P12 and the scan-in terminal P13, the control input is connected to the scan enable terminal P14, and the clock terminal C of the flip-flop 61 is connected to the clock terminal P11. The data input terminal D is connected to the output of the 2to1 selector 62, the data output terminal Qin is commonly connected to the data output terminal P21 and the scan-out terminal P22, and the inverted data output terminal QBin is connected to the data output inversion terminal P23. Is done.

  In such a configuration, the flip-flop 61 operates in synchronization with the clock CLOCK obtained from the clock terminal P11, and is obtained from the data input terminal P12 by setting the scan enable signal SEN to “L” (“0”) during normal operation. The data DATA is output to the data input terminal D of the flip-flop 61 as the applied data, and the scan enable signal SEN is set to “H” (“1”) at the time of scan shift, and the scan-in signal SIN obtained from the scan-in terminal P13 is applied. The data is output to the data input terminal D of the flip-flop 61. Then, the stored data is output as the data output Q and the scan-out signal SOUT from the data output terminal P21 and the scan-out terminal P22, and the inverted data of the stored data is output from the data output inversion terminal P23 as the inverted data output QB. A circuit similar to such a scan FF circuit 51 is disclosed in Patent Document 1, for example.

JP 2000-321331 A

  The LSI circuit scale is increasing due to the improvement in the degree of transistor integration accompanying the miniaturization of process technology. In order to efficiently test such a large-scale circuit, it has become essential to use a scan FF circuit.

  However, the configuration of the scan FF circuit as shown in FIG. 43 is a circuit configuration in which the 2to1 selector 62 is inserted between the flip-flop 61 and the data input terminal P12, and the delay time for one stage of the 2to1 selector 62. As a result, the setup timing condition for data DATA after signal processing such as fixed value setting becomes severe, and conversely, the scan out terminal P22 of the scan FF circuit 51 in the previous stage and the scan of the scan FF circuit 51 in the subsequent stage Since the in-terminal P13 is generally directly connected, there is a problem that the hold timing condition for the scan-in signal SIN is not strict.

  The present invention has been made to solve the above-described problems, has a fixed value input function, relaxes the setup timing condition for the input data, and holds the timing condition for the input scan-in signal. An object of the present invention is to obtain a scan FF circuit in which the above-described relaxation is achieved.

  The scan FF circuit according to claim 1 is a scan flip-flop circuit (scan FF circuit) having a clock terminal, a data input terminal, a scan-in terminal, a data output terminal, and a scan-out terminal, A flip-flop that captures the given data as stored data in synchronization with a clock input via the terminal and outputs the stored data from at least one of the data output terminal and the scan-out terminal; and a predetermined fixed value And a first selector that executes a first selection operation for selecting and outputting one of the scan-in signals obtained from the scan-in terminal, and the input data obtained from the data input terminal and the first selector Select one of the outputs to give to the flip-flop And a second selector for executing the second selection operation to output.

  A scan FF circuit according to a twelfth aspect of the present invention is a scan flip-flop circuit (scan FF circuit) having a clock terminal, a data input terminal, a scan-in terminal, a data output terminal, and a scan-out terminal. A flip-flop that captures the given data as stored data in synchronization with a clock input via the terminal, and outputs the stored data via the data output terminal; and input data obtained from the data input terminal; A first selector that executes a first selection operation of selecting one of scan-in signals obtained from the scan-in terminal and outputting the selected data as data to be provided to the flip-flop, a predetermined fixed value, and the flip-flop Select one of the stored data of the scan and select the scan out end Output from, and a second selector for executing the second selection operation.

  A scan FF circuit according to a twenty-sixth aspect of the present invention is a scan flip-flop circuit having a clock terminal, first and second data input terminals, a scan-in terminal, a scan enable terminal, a data output terminal, and a scan-out terminal ( A scan FF circuit) that captures the given data as storage data in synchronization with a clock input via the clock terminal, and stores the storage data from at least one of the data output terminal and the scan-out terminal. First input data obtained from the first data input terminal based on a flip-flop to be output, a scan enable signal obtained from the scan enable terminal, and second input data obtained from the second data input terminal Obtained from a predetermined fixed value and the scan-in terminal. Select one of the scan-in signal, and a selector for performing a selection operation to output as the application data to the flip-flop.

  The scan FF circuit according to claim 1 of the present invention selects a predetermined fixed value by the first selection operation of the first selector, and outputs the output of the first selector by the second selection operation of the second selector. By selecting, it has a fixed value input function for inputting a predetermined fixed value to the data input of the flip-flop.

  Since the input data obtained from the data input terminal is output to the flip-flop as the added data only through the second selector, the fixed value input function is provided and the setup timing condition for the input data is eased. be able to.

  Further, since the scan-in signal is output as the data input of the flip-flop via the two-stage first and second selectors, the hold timing condition for the scan-in signal can be relaxed.

  According to a tenth aspect of the present invention, the scan FF circuit selects the output of a predetermined fixed value by the second selection operation of the second selector, and passes through the first selector of the next-stage scan FF circuit. It has a fixed value input function for inputting a predetermined fixed value as data to be given to the flip-flop.

  Since the input data obtained from the data input terminal only through the first selector is output as the data to be given to the flip-flop, the above-mentioned fixed value input function is provided, and the setup timing conditions for the input data are relaxed. Can be planned.

  Furthermore, when the scan FF circuit according to claim 10 is used in a plurality of stages and the scan-out terminal of the preceding scan FF circuit is connected to the scan-in terminal of the subsequent scan FF circuit, Through the selector and the first selector of the subsequent scan FF circuit, the data output of the flip-flop of the previous scan FF circuit is fetched as the data to be applied to the flip-flop of the subsequent scan FF circuit, and the subsequent scan The hold timing conditions for the scan-in signal of the FF circuit can be relaxed.

  According to a twentieth aspect of the present invention, the scan FF circuit has a fixed value input function of inputting a predetermined fixed value as data to be given to the flip-flop by selecting a predetermined fixed value by the selection operation of the selector.

  Since the input data obtained from the data input terminal is output as the data to be given to the flip-flop only through the selector, the fixed value input function is provided and the setup timing condition for the input data can be relaxed. it can.

<Embodiment 1>
(Circuit configuration)
1 is a circuit diagram showing a circuit configuration of a scan FF circuit with a synchronous reset terminal according to a first embodiment of the present invention. As shown in the figure, the scan FF circuit 1 of the first embodiment is composed of a flip-flop 11 and 2to1 selectors 12 and 13, and has a clock terminal P11, a data input terminal P12, a scan-in terminal P13, and a scan enable terminal as input parts. P14 and a synchronous reset terminal P15 (synchronous fixed value setting terminal), and a data output terminal P21, a scan-out terminal P22, and a data output inversion terminal P23 in the output section.

  The clock terminal P11 receives a clock CLOCK, the data input terminal P12 receives data DATA (input data), the scan-in terminal P13 receives a scan-in signal SIN, the scan enable terminal P14 receives a scan enable signal SEN, and a synchronous reset terminal P15 receives a synchronous reset signal RB. On the other hand, a data output Q is output from the data output terminal P21, a scan-out signal SOUT is output from the scan-out terminal P22, and an inverted data output QB is output from the data output inversion terminal P23.

  The “0” input and “1” input of the 2to1 selector 13 (first selector) are connected to the ground level (predetermined fixed value) and the scan-in terminal P13, and the control input is connected to the scan enable terminal P14. Based on the scan enable signal SEN obtained from the scan enable terminal P14, the 2to1 selector 13 executes a first selection operation for selecting and outputting one of the ground level and the scan in signal SIN obtained from the scan in terminal P13. To do.

  The “1” input and the “0” input of the 2to1 selector 12 (second selector) are connected to the data input terminal P12 and the output of the 2to1 selector 13, and the control input is connected to the synchronous reset terminal P15. Then, the 2to1 selector 12 selects one of the data DATA obtained from the data input terminal P12 and the output of the 2to1 selector 13 based on the synchronous reset signal RB obtained from the synchronous reset terminal P15, and the data to be given to the flip-flop 11 As a result, a second selection operation for outputting to the data input terminal D is executed.

  As described above, the scan FF circuit 1 according to the first embodiment can control the 2to1 selectors 13 and 12 based on the scan enable signal SEN and the synchronous reset signal RB.

  The clock terminal C of the flip-flop 11 is connected to the clock terminal P11, the data input terminal D is connected to the output of the 2to1 selector 12, the data output terminal Qin is connected in common to the data output terminal P21 and the scan out terminal P22, and is inverted. The data output terminal QBin is connected to the data output inversion terminal P23.

  FIG. 2 is a circuit diagram showing the internal configuration of the flip-flop 11. As shown in the figure, the flip-flop 11 includes inverters G1 to G6 and transfer gates TF1 to TF4.

  The input of the inverter G1 is connected to the clock terminal C, and the input of the inverter G2 is connected to the output of the inverter G1. The output of the inverter G2 becomes the clock signal CK1, and the output of the inverter G1 becomes the inverted clock signal CK1B.

  On the other hand, the input of the inverter G3 is connected to the data input terminal D through the transfer gate TF1, and the output is connected to the input of the inverter G5 through the transfer gate TF3, and also through the inverter G4 and the transfer gate TF2. Return to the input.

  The input of the inverter G6 is connected to the output of the inverter G5, the output of the inverter G6 is connected to the inverted data output terminal QBin, and is connected to the input of the inverter G5 via the transfer gate TF4. The output of the inverter G5 becomes the data output terminal Qin.

  Both transfer gates TF1 and TF4 receive the inverted clock signal CK1B at the NMOS gate and the clock signal CK1 at the PMOS gate. Both transfer gates TF2 and TF3 receive the clock signal CK1 at the NMOS gate and the inverted clock signal CK1B at the PMOS gate.

  The flip-flop 11 configured as described above is configured to turn on / off the transfer gates TF1 to TF4 by connecting the first latch formed by the loop connection of the inverters G3 and G4 and the second latch formed by the loop connection of the inverters G5 and G6. A flip-flop operation is performed depending on the operation. More specifically, the application data input to the data input terminal D is taken into the first latch as storage data using the “H” rising edge of the clock CLOCK as a trigger, and the first latch using the “L” falling edge as a trigger. The data stored in the latch is taken into the second latch. Thereafter, similarly, the flip-flop operation using the first latch and the second latch is performed.

(Operation)
FIG. 3 is an explanatory diagram showing the operation of the scan FF circuit of the first embodiment shown in FIGS. 1 and 2 in the form of a truth table. Hereinafter, the operation of the scan FF circuit according to the first embodiment will be described with reference to FIG.

  The flip-flop 11 operates in synchronization with the clock CLOCK obtained from the clock terminal P11. During normal operation, the synchronous reset signal RB is set to “H” (“1”), and the data DATA obtained from the data input terminal P12 is set to the 2to1 selector 12. The data is output to the data input terminal D as data to be given to the flip-flop 11.

  On the other hand, at the time of scan shift, the scan enable signal SEN is set to “H”, the synchronous reset signal RB is set to “L” (“0”), and the scan-in signal SIN obtained from the scan-in terminal P13 is changed to the 2to1 selector 13 and the 2to1 selector 12. Then, the data is output to the data input terminal D as the data to be given to the flip-flop 11.

  At the time of reset, the scan enable signal SEN is set to “L”, the synchronous reset signal RB is set to “L”, and the ground level signal is supplied as data to be given to the flip-flop 11 via the 2to1 selector 13 and the 2to1 selector 12. Output to the input terminal D.

  As described above, the scan FF circuit 1 according to the first embodiment has a fixed value input function for outputting the ground level having the logical value “0” to the data input terminal D as the data applied to the flip-flop 11 at the time of reset. Yes.

  Then, the data stored in the flip-flop 11 is output from the data output terminal P21 and the scan-out terminal P22 as the data output Q and the scan-out signal SOUT, and the inverted data of the stored data is output from the data output inversion terminal P23 as the inverted data output QB. .

  As shown in FIG. 3, for example, during normal operation (when the synchronous reset signal RB is “H”), “L” / “H” of the data output Q is determined by “L” / “H” of the data DATA. At the time of scan shift (when the scan enable signal SEN is “H” and the synchronous reset signal RB is “L”), the data output Q is “L” / “H” by the scan-in signal SIN “L” / “H”. At the time of resetting (when the scan enable signal SEN is “L” and the synchronous reset signal RB is “L”), the data output Q is “0” regardless of the values of the scan-in signal SIN and the data DATA. L ".

  FIG. 4 is an explanatory diagram showing the internal configuration of the synchronous reset signal generating circuit. The scan FF circuit 1 according to the first embodiment includes the synchronous reset signal generation circuit shown in FIG.

  As shown in FIG. 4, the synchronous reset generation circuit 21 generates an original synchronous reset signal S21 that is the basis of the synchronous reset signal RB, and becomes one input of the AND gate G7. The scan enable signal SEN is input to the other input of the AND gate G7 through the inverter G27. In place of the scan enable signal SEN, a test mode signal TESTMODE that becomes “H” during the test may be used. In addition, regarding the internal configuration of the synchronous reset generation circuit 21, since the relationship with the present invention is sparse, the description thereof is omitted.

  In the synchronous reset signal generating circuit having such a configuration, when the scan enable signal SEN is “H”, the synchronous reset signal RB is forcibly set to “L”. Therefore, the scan enable signal SEN shown in FIG. The combination of “H” and the synchronous reset signal RB “H” is not input to the scan FF circuit of the first embodiment, and the scan-in signal SIN is supplied to the flip-flop 11 only under the control of the scan enable signal SEN. Can be output to the data input terminal D.

(effect)
5 and 6 are circuit diagrams for explaining the effect of the first embodiment. FIG. 5 assumes an integrated circuit that performs synchronous reset using conventional scan FF circuits 51a and 51b. The configuration of the scan FF circuits 51a and 51b is the same as that of the scan FF circuit 51 shown in FIG.

  As shown in FIG. 5, the data output terminal P21 of the scan FF circuit 51a is connected to one of the inputs of the combinational circuit 31, and the scan-out terminal P22 is connected to the scan-in terminal P13 of the scan FF circuit 51b. The output signal S31, which is one of the outputs of the combinational circuit 31, becomes one input of the AND gate G8, the other input of the AND gate G8 becomes the synchronous reset signal RB, and the output of the AND gate G8 becomes the data input of the scan FF circuit 51b. Connected to terminal P12.

  In the integrated circuit having such a configuration, the output signal S31 is applied to the data input terminal P12 of the scan FF circuit 51b via the AND gate G8. That is, the signal input based on the output signal S31 to the data input terminal D of the flip-flop 61 of the scan FF circuit 51b passes through the first data input signal propagation path composed of the AND gate G8 and the 2to1 selector 62 of the scan FF circuit 51b. Will be required.

  FIG. 6 assumes an integrated circuit that performs synchronous reset using the scan FF circuits 1a and 1b of the first embodiment. The configuration of the scan FF circuits 1a and 1b is the same as that of the scan FF circuit 1 shown in FIG.

  The data output terminal P21 of the scan FF circuit 1a is connected to one of the inputs of the combinational circuit 31, and the scan-out terminal P22 is connected to the scan-in terminal P13 of the scan FF circuit 1b. An output signal S31, which is one of the outputs of the combinational circuit 31, is connected to the data input terminal P12 of the scan FF circuit 1b. That is, the output signal S31 is directly input as the data DATA of the scan FF circuit 1b.

  In the integrated circuit having such a configuration, the output signal S31 is directly applied to the data input terminal P12 of the scan FF circuit 1b as data DATA. That is, the signal input based on the output signal S31 to the data input terminal D of the flip-flop 11 of the scan FF circuit 1b needs to pass through the second data input signal propagation path including only the 2to1 selector 62 of the scan FF circuit 1b. become.

  Thus, as is clear from the comparison of FIG. 5 and FIG. 6 (comparison of the first and second data input signal propagation paths), the AND timing is related to the setup timing condition of the data DATA input when the reset function is added. Since there is no need to provide the gate G8, the integrated circuit constituted by the scan FF circuits 1a and 1b of the first embodiment is relaxed, so that the speed of the signal propagation delay of the AND gate G8 can be increased. There is an effect.

  Further, as shown in FIGS. 5 and 6, the scan-out terminal P22 of the scan FF circuit 51a and the scan-in terminal P13 of the scan FF circuit 51b are directly connected, and the scan-out terminal P22 of the scan FF circuit 1a and the scan FF circuit 1b are connected. Since the scan-in terminal P13 is directly connected and the signal propagation delay time is small, the hold timing condition for the scan-in signal SIN becomes severe.

  Therefore, in the integrated circuit of FIG. 5, it is necessary to insert a buffer between the scan-out terminal P22 of the scan FF circuit 51a and the scan-in terminal P13 of the scan FF circuit 51b.

  However, in the integrated circuit of FIG. 5, the scan FF circuit 51 b captures the scan-in signal SIN through the data input terminal D of the flip-flop 11 through the one-stage 2 to 1 selector 62, whereas in the integrated circuit of FIG. Since the scan FF circuit 1b takes the scan-in signal SIN into the data input terminal D of the flip-flop 11 via the two-stage 2to1 selectors 13 and 12, the signal propagation time for one 2to1 selector is shown in FIG. That's all it takes.

  As is apparent from the comparison between FIG. 5 and FIG. 6, regarding the hold timing condition of the scan-in signal SIN, the two-stage 2to1 selectors 13 and 12 that are one stage higher than the configuration of FIG. The integrated circuit constituted by the scan FF circuits 1a and 1b according to the first mode has an effect of being relaxed.

(Other aspects)
FIG. 7 is a circuit diagram showing another aspect of the scan FF circuit of the first embodiment. As shown in the figure, the scan FF circuit 1X of another mode shown in FIG. 7 is different from the scan FF circuit 1 shown in FIG. 1 in that an AND gate G9 is provided in place of the 2to1 selector 13. Hereinafter, different points will be mainly described.

  The AND gate G9 has one input connected to the scan enable terminal P14, the other input connected to the scan-in terminal P13, and the output connected to the “0” input of the 2to1 selector 12.

  The AND gate G9 applies the scan-in signal SIN to the “0” input of the 2to1 selector 12 when the scan enable signal SEN is “H”, and relates to the scan-in signal SIN when the scan enable signal SEN is “L”. Instead, the fixed value “L” is output to the “0” input of the 2to1 selector 12. Therefore, the scan FF circuit 1X can perform the same behavior as the truth table shown in FIG. 3, that is, can perform an operation equivalent to the scan FF circuit 1.

  Further, even when the scan FF circuit 1X is used instead of the scan FF circuits 1a and 1b in FIG. 6, the setup timing condition of the data DATA input is relaxed and the scan-in signal SIN is held when the reset function is added. The effect of relaxing the conditions can be exhibited as well.

  Further, the scan circuit 1X has an effect that the circuit configuration can be simplified by configuring the 2to1 selector 13 of the scan FF circuit 1 with the AND gate G9.

<Embodiment 2>
(Circuit configuration)
FIG. 8 is a circuit diagram showing a circuit configuration of a scan FF circuit with a synchronous set terminal according to the second embodiment of the present invention. As shown in the figure, the scan FF circuit 2 of the second embodiment is composed of a flip-flop 11 and 2 to 1 selectors 14 and 15, and has a clock terminal P11, a data input terminal P12, a scan-in terminal P13, and a scan enable terminal at the input section. P14 and a synchronous set terminal P16 (synchronous fixed value setting terminal), and a data output terminal P21, a scan-out terminal P22, and a data output inversion terminal P23 in the output section.

  The clock terminal P11 receives the clock CLOCK, the data input terminal P12 receives the data DATA, the scan-in terminal P13 receives the scan-in signal SIN, the scan enable terminal P14 receives the scan enable signal SEN, and is synchronously set to the synchronous set terminal P16. Receives signal SB. On the other hand, a data output Q is output from the data output terminal P21, a scan-out signal SOUT is output from the scan-out terminal P22, and an inverted data output QB is output from the data output inversion terminal P23.

  The “0” input and “1” input of the 2to1 selector 15 (first selector) are connected to the power supply potential (predetermined fixed value) and the scan-in terminal P13, and the control input is connected to the scan enable terminal P14. Based on the scan enable signal SEN obtained from the scan enable terminal P14, the 2to1 selector 15 executes a first selection operation for selecting and outputting one of the power supply potential and the scan-in signal SIN obtained from the scan-in terminal P13. To do.

  The “1” input and “0” input of the 2to1 selector 14 (second selector) are connected to the data input terminal P12 and the output of the 2to1 selector 15, and the control input is connected to the synchronous set terminal P16. Then, the 2to1 selector 14 selects one of the data DATA obtained from the data input terminal P12 and the output of the 2to1 selector 15 based on the synchronization set signal SB obtained from the synchronization set terminal P16, and gives it to the flip-flop 11. A second selection operation for outputting data to the data input terminal D is executed.

  As described above, the scan FF circuit 2 according to the second embodiment can control the 2to1 selectors 15 and 14 based on the scan enable signal SEN and the synchronization set signal SB.

  The clock terminal C of the flip-flop 11 is connected to the clock terminal P11, the data input terminal D is connected to the output of the 2to1 selector 14, the data output terminal Qin is connected in common to the data output terminal P21 and the scan out terminal P22, and is inverted. The data output terminal QBin is connected to the data output inversion terminal P23. The internal configuration of the flip-flop 11 is the same as that shown in FIG.

(Operation)
FIG. 9 is an explanatory diagram showing the operation of the scan FF circuit of the second embodiment shown in FIG. 8 in the form of a truth table. Hereinafter, the operation of the scan FF circuit according to the second embodiment will be described with reference to FIG.

  The flip-flop 11 operates in synchronization with the clock CLOCK obtained from the clock terminal P11. During normal operation, the flip-flop 11 sets the synchronous set signal SB to “H” and the data DATA obtained from the data input terminal P12 through the 2to1 selector 14. 11 is output to the data input terminal D as added data.

  On the other hand, at the time of scan shift, the scan enable signal SEN is set to “H”, the synchronization set signal SB is set to “L”, and the scan-in signal SIN obtained from the scan-in terminal P13 is sent to the flip-flop 11 via the 2to1 selectors 15 and 14. The data is output to the data input terminal D as given data.

  At the time of setting, the scan enable signal SEN is set to “L”, the synchronous set signal SB is set to “L”, and the signal of the power supply potential is supplied to the flip-flop 11 via the 2to1 selectors 15 and 14 as a data input terminal. Output to D.

  As described above, the scan FF circuit 2 according to the second embodiment has a fixed value input function for outputting the power supply potential having the logical value “1” to the data input terminal D as the application data to the flip-flop 11 when set. Yes.

  Then, the stored data is output as the data output Q and the scan-out signal SOUT from the data output terminal P21 and the scan-out terminal P22, and the inverted data of the stored data is output from the data output inversion terminal P23 as the inverted data output QB.

  As shown in FIG. 9, for example, during normal operation (when the synchronization set signal SB is “H”), “L” / “H” of the data output Q is determined by “L” / “H” of the data DATA. At the time of scan shift (when the scan enable signal SEN is “H” and the synchronization set signal SB is “L”), the data output Q is “L” / “H” by the scan-in signal SIN “L” / “H”. When “H” is determined and set (when the scan enable signal SEN is “L” and the synchronous set signal SB is “L”), the data output Q is “regardless of the values of the scan-in signal SIN and the data DATA”. H ".

  FIG. 10 is an explanatory diagram showing the internal configuration of the synchronous set signal generating circuit. The scan FF circuit 2 according to the second embodiment includes the synchronization set signal generation circuit shown in FIG.

  As shown in FIG. 10, the synchronization set generation circuit 22 generates the original synchronization set signal S22 that is the basis of the synchronization set signal SB and serves as one input of the AND gate G11. A scan enable signal SEN is input to the other input of the AND gate G11 through the inverter G10. In place of the scan enable signal SEN, a test mode signal TESTMODE that becomes “H” during the test may be used. In addition, regarding the internal configuration of the synchronization set generation circuit 22, the relationship with the present invention is sparse, and the description thereof is omitted.

  In the synchronous set signal generation circuit having such a configuration, when the scan enable signal SEN is “H”, the synchronous set signal SB is forcibly set to “L”. Therefore, the scan enable signal SEN shown in FIG. The combination of “H” and the synchronization set signal SB “H” is not input to the scan FF circuit of the second embodiment, and the scan-in signal SIN is supplied to the flip-flop 11 only under the control of the scan enable signal SEN. Can be output to the data input terminal D.

(effect)
11 and 12 are circuit diagrams for explaining the effect of the second embodiment. FIG. 11 assumes an integrated circuit that performs synchronous set using conventional scan FF circuits 51a and 51b.

  As shown in FIG. 11, the data output terminal P21 of the scan FF circuit 51a is connected to one of the inputs of the combinational circuit 31, and the scan-out terminal P22 is connected to the scan-in terminal P13 of the scan FF circuit 51b. The output signal S31, which is one of the outputs of the combinational circuit 31, becomes one input of the OR gate G24, and the other input of the OR gate G24 becomes a signal obtained from the synchronous set signal SB via the inverter G23. The output is connected to the data input terminal P12 of the scan FF circuit 51b.

  In the integrated circuit having such a configuration, the output signal S31 is applied to the data input terminal P12 of the scan FF circuit 51b via the OR gate G24. That is, the signal input based on the output signal S31 to the data input terminal D of the flip-flop 61 of the scan FF circuit 51b passes through the first data input signal propagation path composed of the OR gate G24 and the 2to1 selector 62 of the scan FF circuit 51b. Will be required.

  FIG. 12 assumes an integrated circuit that performs synchronous set using the scan FF circuits 2a and 2b of the second embodiment. The configuration of the scan FF circuits 2a and 2b is the same as that of the scan FF circuit 2 shown in FIG.

  The data output terminal P21 of the scan FF circuit 2a is connected to one of the inputs of the combinational circuit 31, and the scan-out terminal P22 is connected to the scan-in terminal P13 of the scan FF circuit 2b. An output signal S31, which is one of the outputs of the combinational circuit 31, is connected to the data input terminal P12 of the scan FF circuit 2b. That is, the output signal S31 is directly input as the data DATA of the scan FF circuit 1b.

  In the integrated circuit having such a configuration, the output signal S31 is directly applied to the data input terminal P12 of the scan FF circuit 2b as data DATA. That is, the signal input based on the output signal S31 to the data input terminal D of the flip-flop 11 of the scan FF circuit 2b needs to pass through the second data input signal propagation path including only the 2to1 selector 62 of the scan FF circuit 2b. become.

  Thus, as apparent from the comparison of FIG. 11 and FIG. 12 (comparison of the first and second data input signal propagation paths), the OR gate is related to the setup timing condition of the data DATA input when the set function is added. Since the integrated circuit constituted by the scan FF circuits 2a and 2b of the second embodiment is relieved because the G24 is not required, the speed of the signal propagation delay of the OR gate G24 can be increased. Play.

  Also, as shown in FIGS. 11 and 12, the scan-out terminal P22 of the scan FF circuit 51a and the scan-in terminal P13 of the scan FF circuit 51b are directly connected, and the scan-out terminal P22 of the scan FF circuit 2a and the scan FF circuit 2b Since the scan-in terminal P13 is directly connected and the signal propagation delay time is small, the hold timing condition for the scan-in signal SIN becomes severe.

  For this reason, in the integrated circuit of FIG. 11, it is necessary to insert a buffer between the scan-out terminal P22 of the scan FF circuit 51a and the scan-in terminal P13 of the scan FF circuit 51b.

  However, in the integrated circuit of FIG. 11, the scan FF circuit 51b captures the scan-in signal SIN through the data input terminal D of the flip-flop 11 via the one-stage 2to1 selector 62, whereas in the integrated circuit of FIG. Since the scan FF circuit 2b takes the scan-in signal SIN into the data input terminal D of the flip-flop 11 via the two-stage 2to1 selectors 15 and 14, the signal propagation time for one 2to1 selector is shown in FIG. That's all it takes.

  Thus, as is apparent from the comparison between FIGS. 11 and 12, the hold timing condition of the scan-in signal SIN is one stage higher than the structure of FIG. The integrated circuit constituted by the scan FF circuits 2a and 2b according to the mode 2 has an effect of being relaxed.

(Other aspects)
FIG. 13 is a circuit diagram showing another aspect of the scan FF circuit of the second embodiment. As shown in the figure, the scan FF circuit 2X of another mode shown in FIG. 13 is different from the scan FF circuit 2 shown in FIG. 8 in that an OR gate G12 is provided instead of the 2to1 selector 15. Hereinafter, different points will be mainly described.

  One input of the OR gate G12 is connected to the scan enable terminal P14, the other input is connected to the scan-in terminal P13, and the output is connected to the “0” input of the 2to1 selector 14.

  The OR gate G12 applies the scan-in signal SIN to the “0” input of the 2to1 selector 14 when the scan enable signal SEN is “H”, and relates to the scan-in signal SIN when the scan enable signal SEN is “L”. Instead, the fixed value “H” is output to the “0” input of the 2to1 selector 14. Therefore, the scan FF circuit 2X behaves in the same manner as the truth table shown in FIG. 9, that is, can perform an operation equivalent to the scan FF circuit 2.

  Further, even when the scan FF circuit 2X is used instead of the scan FF circuits 2a and 2b in FIG. 12, the setup timing of the data DATA input and the hold timing condition of the scan-in signal SIN when the set function is added The mitigating effect can also be exhibited.

  In addition, the scan FF circuit 2X can simplify the circuit configuration by configuring the 2to1 selector 15 of the scan FF circuit 2 with the OR gate G12.

<Embodiment 3>
(Circuit configuration)
FIG. 14 is a circuit diagram showing a circuit configuration of a scan FF circuit with a synchronous reset terminal according to the third embodiment of the present invention. As shown in the figure, the scan FF circuit 3 according to the third embodiment is composed of a flip-flop 11 and 2to1 selectors 16 and 17, and as in the first embodiment, a clock terminal P11, a data input terminal P12, and a scan are input to the input unit. It has an in terminal P13, a scan enable terminal P14, and a synchronous reset terminal P15, and a data output terminal P21, a scan out terminal P22, and a data output inversion terminal P23 in the output section.

  The “0” input and “1” input of the 2to1 selector 17 (first selector) are connected to the ground level and scan-in terminal P13, and the control input is connected to the synchronous reset terminal P15. The 2to1 selector 17 executes a first selection operation for selecting and outputting one of the ground level and the scan-in signal SIN obtained from the scan-in terminal P13 based on the synchronous reset signal RB obtained from the synchronous reset terminal P15. To do.

  The “0” input and “1” input of the 2to1 selector 16 (second selector) are connected to the data input terminal P12 and the output of the 2to1 selector 17, and the control input is connected to the scan enable terminal P14. Then, the 2to1 selector 16 selects one of the data DATA obtained from the data input terminal P12 and the output of the 2to1 selector 17 based on the scan enable signal SEN obtained from the scan enable terminal P14, and the data to be given to the flip-flop 11. As a result, a second selection operation for outputting to the data input terminal D is executed.

  As described above, the scan FF circuit 3 according to the third embodiment can control the 2to1 selectors 17 and 16 based on the synchronous reset signal RB and the scan enable signal SEN.

  The clock terminal C of the flip-flop 11 is connected to the clock terminal P11, the data input terminal D is connected to the output of the 2to1 selector 16, the data output terminal Qin is connected in common to the data output terminal P21 and the scan out terminal P22, and is inverted. The data output terminal QBin is connected to the data output inversion terminal P23.

(Operation)
FIG. 15 is an explanatory diagram showing the operation of the scan FF circuit of the third embodiment shown in FIG. 14 in the form of a truth table. FIG. 16 is an explanatory diagram showing the relationship between the scan enable signal SEN and the synchronous reset signal RB in a table format.

  Hereinafter, the operation of the scan FF circuit according to the third embodiment will be described with reference to FIGS. 15 and 16.

  The flip-flop 11 operates in synchronization with the clock CLOCK obtained from the clock terminal P11. During the reset period of the normal mode, the scan enable signal SEN is set to “H”, the synchronous reset signal RB is set to “L”, and the ground level signal is set. Is output to the data input terminal D as data to be given to the flip-flop 11 via the 2to1 selector 17 and the 2to1 selector 16.

  During the reset release period of the normal mode (during normal operation), the scan enable signal SEN is set to “L”, and the data DATA obtained from the data input terminal P12 is input as data to be given to the flip-flop 11 via the 2to1 selector 16. Output to terminal D.

  On the other hand, at the time of scan shift in the test mode, the scan enable signal SEN is set to “H”, the synchronous reset signal RB is set to “H”, and the scan-in signal SIN obtained from the scan-in terminal P13 is flip-flops via the 2to1 selectors 17 and 16. 11 is output to the data input terminal D as added data.

  Note that, during the scan test in the test mode, as in the normal operation, the scan enable signal SEN is set to “L”, and the data DATA obtained from the data input terminal P12 is applied to the flip-flop 11 via the 2to1 selector 16. The data is output to the data input terminal D.

  Then, the stored data is output as the data output Q and the scan-out signal SOUT from the data output terminal P21 and the scan-out terminal P22, and the inverted data of the stored data is output from the data output inversion terminal P23 as the inverted data output QB.

  As shown in FIG. 15, for example, during normal operation (when the scan enable signal SEN is “L”), “L” / “H” of the data output Q is determined by “L” / “H” of the data DATA. At the time of scan shift (when the scan enable signal SEN is “H” and the synchronous reset signal RB is “H”), the data output Q is “L” / “H” according to the scan-in signal SIN “L” / “H”. When “H” is determined and reset (when the scan enable signal SEN is “H” and the synchronous reset signal RB is “L”), the data output Q is “0” regardless of the values of the scan-in signal SIN and the data DATA. L ".

  FIG. 17 is an explanatory diagram showing the internal configuration of the synchronous reset signal and scan enable signal generation circuit. The scan FF circuit 3 according to the third embodiment is provided with the signal generation circuit shown in FIG.

  As shown in the figure, it has a reset terminal P31 that receives a reset signal RESET, a test terminal P32 that receives a test signal TEST, and a scan terminal P33 that receives a scan signal SCAN.

  When the test signal TEST is “0”, the normal mode is instructed, and when it is “1”, the test mode is instructed. Reset signal RESET indicates “0” to indicate resetting, “1” indicates reset release, scan signal SCAN indicates “0” during scan shift, and “1” during scan test To do.

  The OR gate G22 has one input connected to the reset terminal P31, the other input connected to the test terminal P32, the AND gate G19 has an inverted one input connected to the reset terminal P31, and an inverted other input connected to the test terminal P32. The AND gate G20 has one input connected to the test terminal P32, the other input connected to the scan terminal P33, one input of the OR gate G21 connected to the output of the AND gate G19, and the other input connected to the output of the AND gate G20. Connected.

  The output of the OR gate G22 becomes the synchronous reset signal RB, and the output of the OR gate G21 becomes the scan enable signal SEN.

  Therefore, the circuit shown in FIG. 17 outputs a signal having the relationship shown in FIG. The scan test means that the data DATA obtained from the data input terminal P12 at the time of the test is taken into the flip-flop 11. The scan shift means that the scan-in signal SIN is taken into the flip-flop 11 and the scan is performed. This means that the out signal SOUT is output to the outside.

  In the scan FF circuit 3 according to the third embodiment, the scan enable signal SEN is set to “H” and the synchronization reset signal RB is set to “H” at the time of scan shift, so that the scan-in from the 2to1 selector 17 is performed based on the synchronization reset signal RB. When the signal SIN is selected, the scan-in signal SIN is always selected from the 2to1 selector 16 based on the scan enable signal SEN, so that the scan-in signal SIN is flip-flops under the control of the synchronous reset signal RB and the scan enable signal SEN. Can be input as data to be assigned to the group 11.

(effect)
When the scan FF circuit 3 according to the third embodiment is used in place of the scan FF circuits 1a and 1b in FIG. 6, as in the first embodiment, a setup timing condition for data DATA input when a reset function is added. And the effect of relaxing the hold timing condition of the scan-in signal SIN can also be exhibited.

(Other aspects)
FIG. 18 is a circuit diagram showing another aspect of the scan FF circuit of the third embodiment. As shown in the figure, the scan FF circuit 3X of another mode shown in FIG. 18 is different from the scan FF circuit 3 shown in FIG. 14 in that an AND gate G31 is provided instead of the 2to1 selector 17. Hereinafter, different points will be mainly described.

  The AND gate G31 has one input connected to the synchronous reset terminal P15, the other input connected to the scan-in terminal P13, and the output connected to the “1” input of the 2to1 selector 16.

  The AND gate G31 applies the scan-in signal SIN to the “1” input of the 2to1 selector 16 when the synchronous reset signal RB is “H”, and relates to the scan-in signal SIN when the synchronous reset signal RB is “L”. Instead, a fixed value “L” is given to the “1” input of the 2to1 selector 16. Therefore, the scan FF circuit 3X behaves in the same manner as the truth table shown in FIG. 15, that is, can perform an operation equivalent to the scan FF circuit 3.

  Further, when the scan FF circuit 3X according to another aspect of the third embodiment is used in place of the scan FF circuits 1a and 1b in FIG. 6, the data when the reset function is added as in the first embodiment. The relaxation effect of the setup timing condition of the DATA input and the hold timing condition of the scan-in signal SIN can be similarly exhibited.

  In addition, the scan FF circuit 3X can simplify the circuit configuration by configuring the 2to1 selector 17 of the scan FF circuit 3 by the AND gate G31.

<Embodiment 4>
(Circuit configuration)
FIG. 19 is a circuit diagram showing a circuit configuration of a scan FF circuit with a synchronous set terminal according to the fourth embodiment of the present invention. As shown in the figure, the scan FF circuit 2 according to the fourth embodiment is composed of a flip-flop 11 and 2 to 1 selectors 18 and 19, and as in the second embodiment, a clock terminal P11, a data input terminal P12, and a scan are input to the input unit. It has an in terminal P13, a scan enable terminal P14, and a synchronous set terminal P16, and a data output terminal P21, a scan out terminal P22, and a data output inversion terminal P23 in the output section.

  The “0” input and “1” input of the 2to1 selector 19 (first selector) are connected to the power supply potential and the scan-in terminal P13, and the control input is connected to the synchronous set terminal P16. The 2to1 selector 19 executes a first selection operation for selecting and outputting one of the power supply potential and the scan-in signal SIN obtained from the scan-in terminal P13 based on the synchronization set signal SB obtained from the synchronization set terminal P16. To do.

  The “0” input and “1” input of the 2to1 selector 18 (second selector) are connected to the data input terminal P12 and the output of the 2to1 selector 19, and the control input is connected to the scan enable terminal P14. Then, the 2to1 selector 18 selects one of the data DATA obtained from the data input terminal P12 and the output of the 2to1 selector 19 based on the scan enable signal SEN obtained from the scan enable terminal P14, and the data to be given to the flip-flop 11. As a result, a second selection operation for outputting to the data input terminal D is executed.

  As described above, the scan FF circuit 4 according to the fourth embodiment can control the 2to1 selectors 19 and 18 based on the synchronous set signal SB and the scan enable signal SEN.

  The clock terminal C of the flip-flop 11 is connected to the clock terminal P11, the data input terminal D is connected to the output of the 2to1 selector 18, the data output terminal Qin is connected in common to the data output terminal P21 and the scan out terminal P22, and is inverted. The data output terminal QBin is connected to the data output inversion terminal P23. The internal configuration of the flip-flop 11 is the same as that shown in FIG.

(Operation)
FIG. 20 is an explanatory diagram showing the operation of the scan FF circuit of the fourth embodiment shown in FIG. 19 in the form of a truth table. FIG. 21 is an explanatory diagram showing the relationship between the scan enable signal SEN and the synchronization set signal SB in a tabular form.

  Hereinafter, the operation of the scan FF circuit according to the fourth embodiment will be described with reference to FIGS.

  The flip-flop 11 operates in synchronization with the clock CLOCK obtained from the clock terminal P11, and sets the scan enable signal SEN to “L” during the normal mode set release (during normal operation) to obtain the data DATA obtained from the data input terminal P12. Is output to the data input terminal D through the 2to1 selector 18 as data to be given to the flip-flop 11.

  On the other hand, at the time of scan shift in the test mode, the scan enable signal SEN is set to “H”, the synchronization set signal SB is set to “H”, and the scan-in signal SIN obtained from the scan-in terminal P13 is flip-flops via the 2to1 selectors 19 and 18. 11 is output to the data input terminal D as added data.

  At the time of setting during the normal mode setting period, the scan enable signal SEN is set to “H”, the synchronous set signal SB is set to “L”, and the signal of the power supply potential is sent to the flip-flop 11 via the 2to1 selectors 19 and 18. To the data input terminal D.

  During the scan test in the test mode, as in the normal operation, the scan enable signal SEN is set to “L”, and the data DATA obtained from the data input terminal P12 is applied to the flip-flop 11 via the 2to1 selector 16. To the data input terminal D.

  Then, the stored data is output as the data output Q and the scan-out signal SOUT from the data output terminal P21 and the scan-out terminal P22, and the inverted data of the stored data is output from the data output inversion terminal P23 as the inverted data output QB.

  As shown in FIG. 20, for example, during normal operation (when the scan enable signal SEN is “L”), “L” / “H” of the data output Q is determined by “L” / “H” of the data DATA. At the time of scan shift (when the scan enable signal SEN is “H” and the synchronization set signal SB is “H”), the data output Q is “L” / “H” by the scan-in signal SIN “L” / “H”. When “H” is determined and set (when the scan enable signal SEN is “H” and the synchronous set signal SB is “L”), the data output Q is “irrespective of the values of the scan-in signal SIN and the data DATA”. H ".

  Note that, similarly to the scan FF circuit 3 of the third embodiment, the scan FF circuit 4 of the fourth embodiment also uses the signal generation circuit corresponding to FIG. 17 that satisfies the relationship shown in FIG. The scan FF circuit 4 is provided.

(effect)
When the scan FF circuit 4 according to the fourth embodiment is used in place of the scan FF circuits 2a and 2b in FIG. 12, the setup timing condition for data DATA input when the set function is added as in the second embodiment. And the effect of relaxing the hold timing condition of the scan-in signal SIN can also be exhibited.

(Other aspects)
FIG. 22 is a circuit diagram showing another aspect of the scan FF circuit of the fourth embodiment. As shown in the figure, the scan FF circuit 4X of another mode shown in FIG. 22 is different from the scan FF circuit 4 shown in FIG. 19 in that an OR gate G32 is provided in place of the 2to1 selector 19. Hereinafter, different points will be mainly described.

  One of the inverted inputs of the OR gate G32 is connected to the synchronous set terminal P16, the other input is connected to the scan-in terminal P13, and the output is connected to the “1” input of the 2to1 selector 18.

  The OR gate G32 applies the scan-in signal SIN to the “1” input of the 2to1 selector 18 when the synchronization set signal SB is “H”, and relates to the scan-in signal SIN when the synchronization set signal SB is “L”. Instead, a fixed value “H” is given to the “1” input of the 2to1 selector 18. Therefore, the scan FF circuit 4X behaves in the same manner as the truth table shown in FIG. 20, that is, can perform an operation equivalent to the scan FF circuit 4.

  Further, when the scan FF circuit 4X of the fourth embodiment is used in place of the scan FF circuits 2a and 2b in FIG. 12, as in the second embodiment, the setup of the data DATA input when the set function is added The relaxation effect of the timing condition and the hold timing condition of the scan-in signal SIN can be similarly exhibited.

  In addition, the scan FF circuit 4X can simplify the circuit configuration by configuring the 2to1 selector 19 of the scan FF circuit 4 with an OR gate G32.

<Embodiment 5>
(Circuit configuration)
FIG. 23 is a circuit diagram showing a circuit configuration of a scan FF circuit with a synchronous reset terminal according to the fifth embodiment of the present invention. As shown in the figure, the scan FF circuit 5 of the fifth embodiment is composed of a flip-flop 11 and 2to1 selectors 23 and 24, and as in the first embodiment, a clock terminal P11, a data input terminal P12, and a scan are input to the input section. It has an in terminal P13, a scan enable terminal P14, and a synchronous reset terminal P15, and a data output terminal P21 and a scan out terminal P22 in the output section.

  The “1” input and “0” input of the 2to1 selector 23 (first selector) are connected to the data input terminal P12 and the scan-in terminal P13, and the control input is connected to the synchronous reset terminal P15. Then, the 2to1 selector 23 selects one of the data DATA obtained from the data input terminal P12 and the scan-in signal SIN obtained from the scan-in terminal P13 based on the synchronous reset signal RB obtained from the synchronous reset terminal P15. A first selection operation for outputting to the data input terminal D as data to be given to the flip-flop 11 is executed.

  The “0” input and “1” input of the 2to1 selector 24 (second selector) are connected to the ground level and the data output terminal Qin of the flip-flop 11, and the control input is connected to the scan enable terminal P14. The output is connected to the scan-out terminal P22. The 2to1 selector 24 selects one of the ground level and the data output Q of the flip-flop 11 obtained from the data output terminal Qin based on the scan enable signal SEN obtained from the scan enable terminal P14, and scans from the scanout terminal P22. A second selection operation for outputting as the out signal SOUT is executed.

  As described above, the scan FF circuit 5 according to the fifth embodiment can control the 2to1 selectors 23 and 24 based on the synchronous reset signal RB and the scan enable signal SEN.

  The clock terminal C of the flip-flop 11 is connected to the clock terminal P11, the data input terminal D is connected to the output of the 2to1 selector 23, and the data output terminal Qin is connected to the data output terminal P21 together with the “1” input of the 2to1 selector 24. The

(Operation)
In such a configuration, the flip-flop 11 operates in synchronization with the clock CLOCK obtained from the clock terminal P11. At the time of reset, the scan enable signal SEN of the scan FF circuit 5 in the previous stage is set to “L”, and a ground level signal is output from the scan out terminal P22 as the scan out signal SOUT via the 2to1 selector 24. On the other hand, the subsequent scan FF circuit 5 sets the synchronous reset signal RB to “L” and selects the scan-in signal SIN (previous scan-out signal SOUT).

  As a result, the post-stage scan FF circuit 4 can perform a reset operation in which the ground level is input to the flip-flop 11 via the scan-in terminal P13 and the 2to1 selector 23.

  As described above, the scan FF circuit 5 according to the fifth embodiment has a fixed value input function for inputting the ground level that is the logical value “0” to the scan-in terminal P13 of the subsequent-stage scan FF circuit 5 at the time of reset. Yes.

  During normal operation, the synchronous reset signal RB is set to “H”, the scan enable signal SEN is set to “H”, and data DATA obtained from the data input terminal P12 is input as data to be given to the flip-flop 11 via the 2to1 selector 23. The data is output to the terminal D, and the data output terminal Qin is connected to the scan-out terminal P22 via the 2to1 selector 24.

  On the other hand, at the time of scan shift, the scan enable signal SEN is set to “H”, the synchronous reset signal RB is set to “L”, and the scan-in signal SIN obtained from the scan-in terminal P13 is applied to the flip-flop 11 via the 2to1 selector 23. To the data input terminal D, and the data output terminal Qin is connected to the scan-out terminal P22 via the 2to1 selector 24.

  The stored data is output as the data output Q from the data output terminal P21, and is output as the scan-out signal SOUT from the scan-out terminal P22 during the normal operation and the scan shift.

(effect)
When the scan FF circuit 5 according to the fifth embodiment is used instead of the scan FF circuits 1a and 1b in FIG. 6, the data DATA is transferred to the flip-flop 11 only through the 2to1 selector 23 as in the first embodiment. Since it can be output to the data input terminal D as the added data, it is possible to ease the setup timing condition of the data DATA input when the reset function is added.

  Further, when the scan FF circuit 5 according to the fifth embodiment is used in place of the scan FF circuits 1a and 1b in FIG. 6, the scan-out terminal P22 of the preceding scan FF circuit 5 (replacement of the scan FF circuit 1a) is When directly connected to the scan-in terminal P13 of the subsequent scan FF circuit 5 (replacement of the scan FF circuit 1b), the 2 to 1 selector 24 of the previous scan FF circuit 5 and the 2 to 1 selector 23 of the subsequent scan FF circuit 5 are connected. Thus, the data output Q of the flip-flop 11 of the preceding scan FF circuit 5 is taken in as data to be given to the flip-flop 11 of the succeeding scan FF circuit 5, and the scan-in signal for the scan FF circuit 5 of the succeeding stage is captured. The hold timing conditions can be relaxed.

(Other aspects)
FIG. 24 is a circuit diagram showing another aspect of the scan FF circuit of the fifth embodiment. As shown in FIG. 23, the scan FF circuit 5X shown in FIG. 24 differs from the scan FF circuit 5 shown in FIG. 23 in that an AND gate G33 is provided instead of the 2to1 selector 24. Hereinafter, different points will be mainly described.

  The AND gate G33 has one input connected to the data output terminal Qin of the flip-flop 11, the other input connected to the scan enable terminal P14, and the output connected to the scan out terminal P22.

  When the scan enable signal SEN is “H”, the AND gate G33 outputs a signal obtained from the data output terminal Qin as the scan-out signal SOUT from the scan-out terminal P22. On the other hand, when the scan enable signal SEN is “L”, the fixed value “L” is output as the scan-out signal SOUT from the scan-out terminal P22 regardless of the signal obtained from the data output terminal Qin. Therefore, the scan FF circuit 5X can perform operations equivalent to the scan FF circuit 5 (reset operation, normal operation, and scan shift operation).

  Further, when the scan FF circuit 5X according to another aspect of the fifth embodiment is used in place of the scan FF circuits 1a and 1b in FIG. 6, a reset function is added as in the case where the scan FF circuit 5 is used. In this case, the relaxation effect of the setup timing condition of the data DATA input and the hold timing condition of the scan-in signal SIN can be similarly exhibited.

  In addition, the scan FF circuit 5X can simplify the circuit configuration by configuring the 2to1 selector 24 of the scan FF circuit 5 with an AND gate G33.

<Embodiment 6>
(Circuit configuration)
FIG. 25 is a circuit diagram showing a circuit configuration of a scan FF circuit with a synchronous set terminal according to the sixth embodiment of the present invention. As shown in the figure, the scan FF circuit 6 of the sixth embodiment is composed of a flip-flop 11 and 2to1 selectors 25 and 26, and as in the second embodiment, a clock terminal P11, a data input terminal P12, and a scan are input to the input section. It has an in terminal P13, a scan enable terminal P14, and a synchronous set terminal P16, and a data output terminal P21 and a scan out terminal P22 in the output section.

  The “1” input and “0” input of the 2to1 selector 25 (first selector) are connected to the data input terminal P12 and the scan-in terminal P13, and the control input is connected to the synchronous set terminal P16. The 2to1 selector 25 selects one of the data DATA obtained from the data input terminal P12 and the scan-in signal SIN obtained from the scan-in terminal P13 based on the synchronization set signal SB obtained from the synchronization set terminal P16. A first selection operation for outputting to the data input terminal D as data to be given to the flip-flop 11 is executed.

  The “0” input and “1” input of the 2to1 selector 26 (second selector) are connected to the power supply potential and the data output terminal Qin of the flip-flop 11, and the control input is connected to the scan enable terminal P14. The output is connected to the scan-out terminal P22. The 2to1 selector 26 selects one of the power supply potential and the data output Q of the flip-flop 11 obtained from the data output terminal Qin based on the scan enable signal SEN obtained from the scan enable terminal P14, and scans from the scanout terminal P22. A second selection operation for outputting as the out signal SOUT is executed.

  As described above, the scan FF circuit 6 according to the sixth embodiment can control the 2to1 selectors 25 and 26 based on the synchronous set signal SB and the scan enable signal SEN.

  The clock terminal C of the flip-flop 11 is connected to the clock terminal P11, the data input terminal D is connected to the output of the 2to1 selector 25, and the data output terminal Qin is connected to the data output terminal P21 together with the “1” input of the 2to1 selector 26. The

(Operation)
In such a configuration, the flip-flop 11 operates in synchronization with the clock CLOCK obtained from the clock terminal P11. At the time of setting, the scan enable signal SEN of the scan FF circuit 6 in the previous stage is set to “L”, and the signal of the power supply potential is input as the scan out signal SOUT from the scan out terminal P22 via the 2to1 selector 26. On the other hand, the synchronization set signal SB of the subsequent scan FF circuit 6 is set to “L” to select the scan-in signal SIN (previous scan-out signal SOUT) obtained from the data input terminal P12.

  As a result, it is possible to execute a set operation in which a power supply potential is input as data to be applied to the flip-flop 11 of the scan FF circuit 6 at the subsequent stage.

  As described above, the scan FF circuit 6 of the sixth embodiment has a fixed value input function for inputting the power supply potential having the logical value “1” to the scan-in terminal P13 of the next-stage scan FF circuit at the time of setting. Yes.

  During normal operation, the synchronization set signal SB is set to “H”, the scan enable signal SEN is set to “H”, and data DATA obtained from the data input terminal P12 is input as data to be given to the flip-flop 11 via the 2to1 selector 25. The data is output to the terminal D, and the data output terminal Qin is connected to the scan-out terminal P22 via the 2to1 selector 26.

  On the other hand, at the time of scan shift, the scan enable signal SEN is set to “H”, the synchronization set signal SB is set to “L”, and the scan-in signal SIN obtained from the scan-in terminal P13 is applied to the flip-flop 11 via the 2to1 selector 25. To the data input terminal D, and the data output terminal Qin is connected to the scan-out terminal P22 via the 2to1 selector 26.

  The stored data is output as the data output Q from the data output terminal P21, and is output as the scan-out signal SOUT from the scan-out terminal P22 during the normal operation and the scan shift.

(effect)
When the scan FF circuit 6 according to the sixth embodiment is used instead of the scan FF circuits 2a and 2b in FIG. 12, the data DATA is transferred to the flip-flop 11 only through the 2to1 selector 25 as in the second embodiment. Since it can be output to the data input terminal D as added data, the setup timing condition of the data DATA input when the set function is added can be eased.

  Furthermore, when the scan FF circuit 6 according to the sixth embodiment is used instead of the scan FF circuits 2a and 2b in FIG. 12, the scan-out terminal P22 of the preceding scan FF circuit 6 (replacement of the scan FF circuit 2a) When directly connected to the scan-in terminal P13 of the subsequent scan FF circuit 6 (replacement of the scan FF circuit 2b), the 2 to 1 selector 26 of the previous scan FF circuit 6 and the 2 to 1 selector 25 of the subsequent scan FF circuit 6 are connected. Thus, the data output Q of the flip-flop 11 of the preceding-stage scan FF circuit 6 is fetched as data to be given to the flip-flop 11 of the subsequent-stage scan FF circuit 6, and the scan-in signal of the subsequent-stage scan FF circuit 6 is held. The timing conditions can be relaxed.

(Other aspects)
FIG. 26 is a circuit diagram showing another aspect of the scan FF circuit of the sixth embodiment. As shown in FIG. 25, the scan FF circuit 6X of another mode shown in FIG. 26 differs from the scan FF circuit 6 shown in FIG. 25 in that an OR gate G34 is provided instead of the 2to1 selector 26. Hereinafter, different points will be mainly described.

  The OR gate G34 has one input connected to the data output terminal Qin of the flip-flop 11, the other inverted input connected to the scan enable terminal P14, and the output connected to the scan out terminal P22.

  The OR gate G34 outputs a signal obtained from the data output terminal Qin as the scan-out signal SOUT from the scan-out terminal P22 when the scan enable signal SEN is “H”. On the other hand, when the scan enable signal SEN is “L”, the fixed value “H” is output as the scan-out signal SOUT from the scan-out terminal P22 regardless of the signal obtained from the data output terminal Qin. Accordingly, the scan FF circuit 6X can perform operations equivalent to the scan FF circuit 6 (set operation, normal operation, and scan shift operation).

  Further, in place of the scan FF circuits 2a and 2b in FIG. 12, when the scan FF circuit 6X according to another aspect of the sixth embodiment is used, a set function is added as in the case of using the scan FF circuit 6. In this case, the relaxation effect of the setup timing condition of the data DATA input and the hold timing condition of the scan-in signal SIN can be similarly exhibited.

  In addition, the scan FF circuit 6X can simplify the circuit configuration by configuring the 2 to 1 selector 26 of the scan FF circuit 6 with the OR gate G34.

<Embodiment 7>
(Circuit configuration)
FIG. 27 is a circuit diagram showing a circuit configuration of a scan FF circuit with a synchronous reset terminal according to the seventh embodiment of the present invention. As shown in the figure, the scan FF circuit 7 of the seventh embodiment is composed of a flip-flop 11 and 2to1 selectors 27 and 28, and as in the fifth embodiment, a clock terminal P11, a data input terminal P12, and a scan are input to the input unit. It has an in terminal P13, a scan enable terminal P14, and a synchronous reset terminal P15, and a data output terminal P21 and a scan out terminal P22 in the output section.

  The “0” input and “1” input of the 2to1 selector 27 (first selector) are connected to the data input terminal P12 and the scan-in terminal P13, and the scan enable terminal P14 is connected to the control input. The 2to1 selector 27 selects one of the data DATA obtained from the data input terminal P12 and the scan-in signal SIN obtained from the scan-in terminal P13 on the basis of the scan enable signal SEN obtained from the scan enable terminal P14 to select a flip-flop. 1st selection operation | movement output to the data input terminal D as provision data to 11 is performed.

  The “0” input and “1” input of the 2to1 selector 28 (second selector) are connected to the ground level and the data output terminal Qin of the flip-flop 11, and the control input is connected to the synchronous reset terminal P15. The output is connected to the scan-out terminal P22. Then, the 2to1 selector 28 selects one of the data output Q obtained from the data output terminal Qin12 of the flip-flop 11 and the ground level based on the synchronous reset signal RB obtained from the synchronous reset terminal P15, and selects from the scan-out terminal P22. A second selection operation that outputs the scan-out signal SOUT is executed.

  As described above, the scan FF circuit 7 according to the seventh embodiment can control the 2to1 selectors 27 and 28 based on the scan enable signal SEN and the synchronous reset signal RB.

  The clock terminal C of the flip-flop 11 is connected to the clock terminal P11, the data input terminal D is connected to the output of the 2to1 selector 27, and the data output terminal Qin is connected to the data output terminal P21 together with the “1” input of the 2to1 selector 28. The

(Operation)
In such a configuration, the flip-flop 11 operates in synchronization with the clock CLOCK obtained from the clock terminal P11. At the time of reset, the scan FF circuit 7 at the previous stage sets the synchronous reset signal RB to “L” and inputs a ground level signal from the scan-out terminal P22 as the scan-out signal SOUT via the 2to1 selector 28. On the other hand, the scan FF circuit 7 in the subsequent stage sets the scan enable signal SEN to “H” and selects the scan-in signal SIN (the scan-out signal SOUT of the scan FF circuit 7 in the previous stage).

  As a result, it is possible to perform a reset operation that can provide a ground level as data to be applied to the flip-flop 11 of the scan FF circuit 7 in the subsequent stage.

  During normal operation, the synchronous reset signal RB is set to “H”, the scan enable signal SEN is set to “L”, and the data DATA obtained from the data input terminal P12 is input as data to be given to the flip-flop 11 via the 2to1 selector 27. The data is output to the terminal D, and the data output terminal Qin is connected to the scan-out terminal P22 via the 2to1 selector 28.

  On the other hand, at the time of scan shift, the scan enable signal SEN is set to “H”, the synchronous reset signal RB is set to “H”, and the scan-in signal SIN obtained from the scan-in terminal P13 is applied to the flip-flop 11 via the 2to1 selector 27. Is output to the data input terminal D, and the data output terminal Qin is connected to the scan-out terminal P22 via the 2to1 selector 28.

  The stored data is output as the data output Q from the data output terminal P21, and is output as the scan-out signal SOUT from the scan-out terminal P22 during the normal operation and the scan shift.

(effect)
When the scan FF circuit 7 according to the seventh embodiment is used instead of the scan FF circuits 1a and 1b in FIG. 6, as in the fifth embodiment, the setup timing condition for the data DATA input when the reset function is added. And the effect of relaxing the hold timing condition of the scan-in signal SIN can also be exhibited.

(Other aspects)
FIG. 28 is a circuit diagram showing another aspect of the scan FF circuit of the seventh embodiment. As shown in FIG. 27, the scan FF circuit 7X of another mode shown in FIG. 28 differs from the scan FF circuit 7 shown in FIG. 27 in that an AND gate G35 is provided in place of the 2to1 selector 28. Hereinafter, different points will be mainly described.

  The AND gate G35 has one input connected to the data output terminal Qin of the flip-flop 11, the other input connected to the synchronous reset terminal P15, and the output connected to the scan-out terminal P22.

  The AND gate G35 outputs a signal obtained from the data output terminal Qin as the scan-out signal SOUT from the scan-out terminal P22 when the synchronous reset signal RB is “H”. On the other hand, when the synchronous reset signal RB is “L”, the fixed value “L” is output as the scan-out signal SOUT from the scan-out terminal P22 regardless of the signal obtained from the data output terminal Qin. Accordingly, the scan FF circuit 7X can perform operations equivalent to the scan FF circuit 7 (reset operation, normal operation, and scan shift operation).

  Further, when the scan FF circuit 7X according to another aspect of the seventh embodiment is used in place of the scan FF circuits 1a and 1b in FIG. 6, a reset function is added as in the case where the scan FF circuit 7 is used. In this case, the relaxation effect of the setup timing condition of the data DATA input and the hold timing condition of the scan-in signal SIN can be similarly exhibited.

  In addition, the scan FF circuit 7X can simplify the circuit configuration by configuring the 2to1 selector 28 of the scan FF circuit 7 with an AND gate G35.

<Eighth embodiment>
(Circuit configuration)
FIG. 29 is a circuit diagram showing a circuit configuration of a scan FF circuit with a synchronous set terminal according to an eighth embodiment of the present invention. As shown in the figure, the scan FF circuit 8 of the eighth embodiment is composed of a flip-flop 11 and 2to1 selectors 29 and 30, and as in the sixth embodiment, a clock terminal P11, a data input terminal P12, and a scan are input to the input unit. It has an in terminal P13, a scan enable terminal P14, and a synchronous set terminal P16, and a data output terminal P21 and a scan out terminal P22 in the output section.

  The “0” input and “1” input of the 2to1 selector 29 (first selector) are connected to the data input terminal P12 and the scan-in terminal P13, and the scan enable terminal P14 is connected to the control input. The 2to1 selector 29 selects one of the data DATA obtained from the data input terminal P12 and the scan-in signal SIN obtained from the scan-in terminal P13 on the basis of the scan enable signal SEN obtained from the scan enable terminal P14. 1st selection operation | movement output to the data input terminal D as provision data to 11 is performed.

  The “0” input and “1” input of the 2to1 selector 30 (second selector) are connected to the power supply potential and the data output terminal Qin of the flip-flop 11, and the control input is connected to the synchronous set terminal P16. The output is connected to the scan-out terminal P22. Then, the 2to1 selector 30 selects one of the data output Q and the power supply potential obtained from the data output terminal Qin of the flip-flop 11 based on the synchronization set signal SB obtained from the synchronization set terminal P16, from the scan-out terminal P22. A second selection operation that outputs the scan-out signal SOUT is executed.

  As described above, the scan FF circuit 8 according to the eighth embodiment can control the 2to1 selectors 29 and 30 based on the scan enable signal SEN and the synchronization set signal SB.

  The clock terminal C of the flip-flop 11 is connected to the clock terminal P11, the data input terminal D is connected to the output of the 2to1 selector 29, and the data output terminal Qin is connected to the data output terminal P21 together with the “1” input of the 2to1 selector 30. The

(Operation)
In such a configuration, the flip-flop 11 operates in synchronization with the clock CLOCK obtained from the clock terminal P11. At the time of setting, the scan FF circuit 8 at the previous stage sets the synchronous set signal SB to “L” and inputs a signal of the power supply potential from the scan-out terminal P22 via the 2to1 selector 30 as the scan-out signal SOUT. On the other hand, the subsequent scan FF circuit 8 sets the scan enable signal SEN to “H” and selects the scan-in signal SIN (previous scan-out signal SOUT).

  As a result, it is possible to perform a setting operation in which a power supply potential is applied as applied data to the flip-flop 11 of the scan FF circuit 8 in the subsequent stage.

  During normal operation, the synchronization set signal SB is set to “H”, the scan enable signal SEN is set to “L”, and data DATA obtained from the data input terminal P12 is input as data to be given to the flip-flop 11 through the 2to1 selector 29. The data is output to the terminal D, and the data output terminal Qin is connected to the scan-out terminal P22 via the 2to1 selector 30.

  On the other hand, at the time of scan shift, the scan enable signal SEN is set to “H”, the synchronization set signal SB is set to “H”, and the scan-in signal SIN obtained from the scan-in terminal P13 is applied to the flip-flop 11 via the 2to1 selector 29. To the data input terminal D, and the data output terminal Qin is connected to the scan-out terminal P22 via the 2to1 selector 30.

  The stored data is output as the data output Q from the data output terminal P21, and is output as the scan-out signal SOUT from the scan-out terminal P22 during the normal operation and the scan shift.

(effect)
When the scan FF circuit 8 of the eighth embodiment is used in place of the scan FF circuits 2a and 2b of FIG. 12, as in the sixth embodiment, the setup timing condition for data DATA input when the set function is added And the effect of relaxing the hold timing condition of the scan-in signal SIN can also be exhibited.

(Other aspects)
FIG. 30 is a circuit diagram showing another aspect of the scan FF circuit according to the eighth embodiment. As compared to the scan FF circuit 8 shown in FIG. 29, the scan FF circuit 8X of another mode shown in FIG. 30 is different in that an OR gate G36 is provided instead of the 2to1 selector 30 as shown in FIG. Hereinafter, different points will be mainly described.

  The OR gate G36 has one input connected to the data output terminal Qin of the flip-flop 11, the other inverted input connected to the synchronous set terminal P16, and the output connected to the scan-out terminal P22.

  When the synchronization set signal SB is “H”, the OR gate G36 outputs a signal obtained from the data output terminal Qin as the scan-out signal SOUT from the scan-out terminal P22. On the other hand, when the synchronization set signal SB is “L”, the fixed value “H” is output as the scan-out signal SOUT from the scan-out terminal P22 regardless of the signal obtained from the data output terminal Qin. Therefore, the scan FF circuit 8X can perform operations equivalent to the scan FF circuit 8 (set operation, normal operation, and scan shift operation).

  Further, when the scan FF circuit 8X according to another aspect of the eighth embodiment is used in place of the scan FF circuits 2a and 2b in FIG. 12, the set function is added as in the case where the scan FF circuit 8 is used. In this case, the relaxation effect of the setup timing condition of the data DATA input and the hold timing condition of the scan-in signal SIN can be similarly exhibited.

  In addition, the scan FF circuit 8X can simplify the circuit configuration by configuring the 2 to 1 selector 30 of the scan FF circuit 8 with the OR gate G36.

<Embodiment 9>
(Circuit configuration)
FIG. 31 is a circuit diagram showing a circuit configuration of a scan FF circuit with a synchronous reset terminal according to the ninth embodiment of the present invention. As shown in the figure, the scan FF circuit 9 of the ninth embodiment is composed of a flip-flop 11 and a 3to1 selector 33 (selector), and has a clock terminal P11 and data input terminals P120 and P121 (first and second) at the input section. Data input terminal), a scan-in terminal P13 and a scan enable terminal P14, and a data output terminal P21, a scan-out terminal P22 and a data output inversion terminal P23 in the output section.

  The clock terminal P11 receives the clock CLOCK, the data input terminal P120 receives data DATA0 (first input data), the data input terminal P121 receives data DATA1 (second input data), and the scan-in terminal P13 scan-in. In response to the signal SIN, the scan enable terminal P14 receives the scan enable signal SEN. On the other hand, a data output Q is output from the data output terminal P21, a scan-out signal SOUT is output from the scan-out terminal P22, and an inverted data output QB is output from the data output inversion terminal P23.

  The 3to1 selector 33 “01” input, “00” input and “1X” input are connected to the data input terminal P120, the ground level and scan-in terminal P13, and the two control inputs are connected to the scan enable terminal P14 and the data input terminal P121. Connected.

  The clock terminal C of the flip-flop 11 is connected to the clock terminal P11, the data input terminal D is connected to the output of the 3to1 selector 33, the data output terminal Qin is connected in common to the data output terminal P21 and the scan-out terminal P22, and is inverted. The data output terminal QBin is connected to the data output inversion terminal P23.

(Operation)
FIG. 32 is an explanatory diagram showing the operation of the scan FF circuit of the ninth embodiment shown in FIG. 31 in the form of a truth table. Hereinafter, the operation of the scan FF circuit according to the ninth embodiment will be described with reference to FIG.

  The flip-flop 11 operates in synchronization with the clock CLOCK obtained from the clock terminal P11. During normal operation, the scan enable signal SEN is set to “L” and the data DATA1 is set to “H” (control input of “01”). The data DATA0 obtained from P120 is output to the data input terminal D as data to be given to the flip-flop 11 via the 3to1 selector 33.

  On the other hand, at the time of scan shift, the scan enable signal SEN is set to “H” (control input of “1X”), and the scan-in signal SIN obtained from the scan-in terminal P13 is provided as data to be given to the flip-flop 11 via the 3to1 selector 33. Output to data input terminal D.

  Further, at the time of reset, the scan enable signal SEN is set to “L”, the data DATA1 is set to “L” (control input of “00”), and a ground level signal is provided as data to be given to the flip-flop 11 via the 3to1 selector 33. Output to data input terminal D.

  Then, the data stored in the flip-flop 11 is output from the data output terminal P21 and the scan-out terminal P22 as the data output Q and the scan-out signal SOUT, and the inverted data of the stored data is output from the data output inversion terminal P23 as the inverted data output QB. .

  As shown in FIG. 32, for example, in the normal operation (when the scan enable signal SEN is “L” and the data DATA1 is “H”), the data output Q is “L” by “L” / “H” of the data DATA0. "/" H is determined, and at the time of scan shift (when the scan enable signal SEN is "H"), the data output Q is "L" / "H" by the scan-in signal SIN "L" / "H". When reset (when the scan enable signal SEN is “L” and the data DATA1 is “L”), the data output Q is determined to be “L” regardless of the values of the scan-in signal SIN and the data DATA. Is done.

(effect)
33 and 34 are circuit diagrams for explaining the effect of the ninth embodiment. FIG. 33 assumes an integrated circuit that performs synchronous reset using conventional scan FF circuits 51a and 51b. The configuration of the scan FF circuits 51a and 51b is the same as that of the scan FF circuit 51 shown in FIG.

  As shown in FIG. 33, the data output terminal P21 of the scan FF circuit 51a is connected to one of the inputs of the combinational circuit 31, and the scan-out terminal P22 is connected to the scan-in terminal P13 of the scan FF circuit 51b.

  An output signal S31 that is one of the outputs of the combinational circuit 31 becomes the other input of the AND gate G13, and one input of the AND gate G13 becomes an output signal S32 that is one of the outputs of another combinational circuit 32. The output of the AND gate G13 is connected to the data input terminal P12 of the scan FF circuit 51b.

  In the integrated circuit having such a configuration, the output signal S31 is applied to the data input terminal P12 of the scan FF circuit 51b via the AND gate G13. That is, the signal input based on the output signal S31 to the data input terminal D of the flip-flop 61 of the scan FF circuit 51b passes through the first data input signal propagation path composed of the AND gate G13 and the 2to1 selector 62 of the scan FF circuit 51b. Will be required.

  FIG. 34 assumes an integrated circuit that performs synchronous reset using the conventional scan FF circuit 51a and the scan FF circuit 9 of the ninth embodiment.

  FIG. 35 is a circuit diagram showing details of the 3to1 selector 33 in the scan FF circuit 9. As shown in the figure, the 3to1 selector 33 includes a 2to1 selector 42 (first selector) and a second selector including an inverter G14, an AND gate G15, and a 2to1 selector 41.

  The input of the inverter G14 is connected to the scan enable terminal P14, one input of the AND gate G15 is connected to the output of the inverter G14, and the other input is connected to the data input terminal P121.

  The “0” input of the 2to1 selector 42 is connected to the ground level, the “1” input is connected to the scan-in terminal P13, and the control input is connected to the scan enable terminal P14. The 2to1 selector 42 executes a first selection operation for selecting and outputting one of the ground level and the scan-in signal SIN obtained from the scan-in terminal P13 based on the scan enable signal SEN obtained from the scan enable terminal P14. To do.

  The “1” input of the 2to1 selector 41 is connected to the data input terminal P120, the “0” input is connected to the output of the 2to1 selector 42, and the control input is connected to the output of the AND gate G15. Then, the 2to1 selector 41 selects one of the data DATA0 obtained from the data input terminal P120 and the output of the 2to1 selector 42 based on the output of the AND gate G15, and applies it to the data input terminal D as data to be given to the flip-flop 11. The second selection operation to be output is executed.

  The 3to1 selector 33 configured as described above performs a selection operation based on the scan enable signal SEN and the data DATA1 in accordance with the trial value table shown in FIG.

  As described above, the scan FF circuit 9 according to the ninth embodiment can control the 2to1 selector 42 based on the scan enable signal SEN, and based on the combination of the scan enable signal SEN and the data DATA1, the 2to1 selector 41, the inverter G14, and the AND. The second selector composed of the gate G15 can be controlled.

  In addition, when the scan enable signal SEN indicates a logical value “0” (“L”), the scan FF circuit 9 according to the ninth embodiment performs a logical product of data DATA0 and data DATA1, as shown in FIG. Can be output from the 2to1 selector 41.

  Returning to FIG. 34, the data output terminal P 21 of the scan FF circuit 51 a is connected to one of the inputs of the combinational circuit 31, and the scan-out terminal P 22 is connected to the scan-in terminal P 13 of the scan FF circuit 9. An output signal S31 that is one of the outputs of the combinational circuit 31 is connected to the data input terminal P121, and an output signal S32 that is one of the outputs of another combinational circuit 32 is connected to the data input terminal P120 of the scan FF circuit 9. Connected. That is, the output signal S32 is directly input as the data DATA0 of the scan FF circuit 9.

  In the integrated circuit having such a configuration, the output signal S32 is directly applied to the data input terminal P12 of the scan FF circuit 9 as data DATA0. That is, the signal input based on the output signal S31 to the data input terminal D of the flip-flop 11 of the scan FF circuit 9 needs to pass through the second data input signal propagation path including only the 2to1 selector 41 in the 3to1 selector 33. become.

  Thus, as is clear from the comparison of FIG. 33 and FIG. 34 (comparison of the first and second data input signal propagation paths), when the reset function is added, regarding the setup timing condition regarding the input of the data DATA0, Since there is no need to provide the AND gate G13, the integrated circuit constituted by the scan FF circuit 9 according to the ninth embodiment is relaxed, so that the signal propagation delay of the AND gate G13 can be increased. Play.

  Further, the 3to1 selector 33 is not configured as shown in FIG. 35, and the data DATA0, the ground level and the scan-in signal SIN are selectively sent to the flip-flop 11 and the data input terminal D through one transfer gate or the like. Even in the one-stage configuration to be connected, it is not necessary to provide the AND gate G13 with respect to the data DATA0, so that the setup timing condition can be relaxed.

  33 and 34, the scan-out terminal P22 of the scan FF circuit 51a and the scan-in terminal P13 of the scan FF circuit 51b are directly connected, and the scan-out terminal P22 of the scan FF circuit 51a and the scan FF circuit 9 Since the scan-in terminal P13 is directly connected and the signal propagation delay time is small, the hold timing condition for the scan-in signal SIN becomes severe.

  Therefore, in the case of the integrated circuit of FIG. 33, it is necessary to insert a buffer between the scan-out terminal P22 of the scan FF circuit 51a and the scan-in terminal P13 of the scan FF circuit 51b.

  However, in the integrated circuit of FIG. 33, the scan FF circuit 51b captures the scan-in signal SIN through the data input terminal D of the flip-flop 11 via the one-stage 2to1 selector 62, whereas in the integrated circuit of FIG. Since the scan FF circuit 9 takes in the scan-in signal SIN as data to be given to the flip-flop 11 via the two-stage 2to1 selectors 42 and 41, the signal propagation time for one 2to1 selector is shown. More than 33 integrated circuits.

  As can be seen from the comparison between FIG. 33 and FIG. 34, the scan FF circuit 9 of the ninth embodiment is used because the two-stage 2-to-1 selectors 42 and 41 are provided for the hold timing condition of the scan-in signal SIN. The integrated circuit constructed as described above has the effect of being relaxed.

(Other aspects)
FIG. 36 is a circuit diagram showing another aspect of the scan FF circuit of the ninth embodiment. As shown in FIG. 35, the scan FF circuit 9X of another mode shown in FIG. 36 differs from the scan FF circuit 9 shown in FIG. 35 in that an AND gate G16 is provided instead of the 2to1 selector 42. Hereinafter, different points will be mainly described.

  The AND gate G16 has one input connected to the scan-in terminal P13, the other input connected to the scan enable terminal P14, and the output connected to the “0” input of the 2to1 selector 413.

  The AND gate G16 applies the scan-in signal SIN to the “0” input of the 2to1 selector 41 when the scan enable signal SEN is “H”, and relates to the scan-in signal SIN when the scan enable signal SEN is “L”. Instead, the fixed value “L” is output to the “0” input of the 2to1 selector 41. Therefore, the scan FF circuit 9X behaves in the same manner as the truth table shown in FIG. 32, that is, can perform an operation equivalent to the scan FF circuit 9.

  Further, when the scan FF circuit 9X is used instead of the scan FF circuit 9 in FIG. 34, the setup timing condition of the input of the data DATA0 is relaxed and the hold timing condition of the scan-in signal SIN when the reset function is added. The mitigating effect can also be exhibited.

  Further, the scan circuit 9X can simplify the circuit configuration by configuring the 2to1 selector 42 of the scan FF circuit 9 with the AND gate G16.

<Embodiment 10>
(Circuit configuration)
FIG. 37 is a circuit diagram showing a circuit configuration of a scan FF circuit with a synchronous set terminal according to the tenth embodiment of the present invention. As shown in the figure, the scan FF circuit 10 according to the tenth embodiment is composed of a flip-flop 11 and a 3to1 selector 34 (selector), and has a clock terminal P11, data input terminals P120 and P121, a scan-in terminal P13, and an input section. It has a scan enable terminal P14, and has a data output terminal P21, a scan-out terminal P22, and a data output inversion terminal P23 in the output section.

  The clock terminal P11 receives the clock CLOCK, the data input terminal P120 receives the data DATA0, the data input terminal P121 receives the data DATA1, the scan-in terminal P13 receives the scan-in signal SIN, and the scan enable terminal P14 receives the scan enable signal SEN. Receive. On the other hand, a data output Q is output from the data output terminal P21, a scan-out signal SOUT is output from the scan-out terminal P22, and an inverted data output QB is output from the data output inversion terminal P23.

  The “01” input, “00” input and “1X” input of the 3to1 selector 34 are connected to the power supply potential, the data input terminal P120 and the scan-in terminal P13, and the two control inputs are the scan enable terminal P14 and the data input terminal P121. Connected to.

  The clock terminal C of the flip-flop 11 is connected to the clock terminal P11, the data input terminal D is connected to the output of the 3to1 selector 34, the data output terminal Qin is connected in common to the data output terminal P21 and the scan-out terminal P22, and is inverted. The data output terminal QBin is connected to the data output inversion terminal P23.

(Operation)
FIG. 38 is an explanatory diagram showing the operation of the scan FF circuit of the tenth embodiment shown in FIG. 37 in the form of a truth table. Hereinafter, the operation of the scan FF circuit according to the tenth embodiment will be described with reference to FIG.

  The flip-flop 11 operates in synchronization with the clock CLOCK obtained from the clock terminal P11. During normal operation, the scan enable signal SEN is set to “L”, the data DATA1 is set to “L” (control input “00”), and the data input terminal P120. The data DATA0 obtained is output to the data input terminal D as data to be given to the flip-flop 11 through the 3to1 selector 34.

  On the other hand, at the time of scan shift, the scan enable signal SEN is set to “H” (control input “1X”), and the scan-in signal SIN obtained from the scan-in terminal P13 is supplied as data to be given to the flip-flop 11 via the 3to1 selector 34. Output to the input terminal D.

  At the time of setting, the scan enable signal SEN is set to “L”, the data DATA1 is set to “H” (control input “01”), and the signal of the power supply potential is supplied as data to be given to the flip-flop 11 via the 3to1 selector 34. Output to the input terminal D.

  Then, the data stored in the flip-flop 11 is output from the data output terminal P21 and the scan-out terminal P22 as the data output Q and the scan-out signal SOUT, and the inverted data of the stored data is output from the data output inversion terminal P23 as the inverted data output QB. .

  As shown in FIG. 38, for example, in normal operation (when the scan enable signal SEN is “L” and the data DATA1 is “L”), the data output Q is “L” by the “L” / “H” of the data DATA0. "/" H is determined, and at the time of scan shift (when the scan enable signal SEN is "H"), the data output Q is "L" / "H" by the scan-in signal SIN "L" / "H". When set (when the scan enable signal SEN is “L” and the data DATA1 is “H”), the data output Q is determined to be “H” regardless of the values of the scan-in signal SIN and the data DATA. Is done.

(effect)
39 and 40 are circuit diagrams for explaining the effect of the tenth embodiment. FIG. 39 assumes an integrated circuit that performs synchronous setting using conventional scan FF circuits 51a and 51b. The configuration of the scan FF circuits 51a and 51b is the same as that of the scan FF circuit 51 shown in FIG.

  As shown in FIG. 39, the data output terminal P21 of the scan FF circuit 51a is connected to one of the inputs of the combinational circuit 31, and the scan-out terminal P22 is connected to the scan-in terminal P13 of the scan FF circuit 51b.

  An output signal S31 that is one of the outputs of the combinational circuit 31 becomes the other input of the OR gate G17, and one input of the OR gate G17 becomes an output signal S32 that is one of the outputs of another combinational circuit 32. The output of the OR gate G17 is connected to the data input terminal P12 of the scan FF circuit 51b.

  In the integrated circuit having such a configuration, the output signal S31 is applied to the data input terminal P12 of the scan FF circuit 51b via the OR gate G17. That is, the signal input based on the output signal S31 to the data input terminal D of the flip-flop 61 of the scan FF circuit 51b passes through the first data input signal propagation path composed of the OR gate G17 and the 2to1 selector 62 of the scan FF circuit 51b. Will be required.

  FIG. 40 assumes an integrated circuit that performs a synchronous set using the conventional scan FF circuit 51a and the scan FF circuit 10 of the tenth embodiment.

  FIG. 41 is a circuit diagram showing details of the 3to1 selector 34 in the scan FF circuit 10. As shown in the figure, the 3to1 selector 34 includes a 2to1 selector 44 (first selector) and a second selector including an OR gate G25 and a 2to1 selector 43.

  One input of the OR gate G25 is connected to the scan enable terminal P14, and the other input is connected to the data input terminal P121.

  The “0” input of the 2to1 selector 44 is connected to the power supply potential, the “1” input is connected to the scan-in terminal P13, and the control input is connected to the scan enable terminal P14. Based on the scan enable signal SEN obtained from the scan enable terminal P14, the 2to1 selector 44 executes a first selection operation for selecting and outputting one of the power supply potential and the scan-in signal SIN obtained from the scan-in terminal P13. To do.

  The “1” input of the 2to1 selector 43 is connected to the data input terminal P120, the “0” input is connected to the output of the 2to1 selector 44, and the control input is connected to the output of the OR gate G25. Then, the 2to1 selector 43 selects one of the data DATA0 obtained from the data input terminal P120 and the output of the 2to1 selector 42 based on the output of the OR gate G25 and applies it to the data input terminal D as the data to be given to the flip-flop 11. The second selection operation to be output is executed.

  The 3to1 selector 34 configured as described above performs a selection operation based on the scan enable signal SEN and the data DATA1 in accordance with the trial value table shown in FIG.

  As described above, the scan FF circuit 10 according to the tenth embodiment can control the 2to1 selector 44 based on the scan enable signal SEN, and based on the combination of the scan enable signal SEN and the data DATA1, based on the 2to1 selector 43 and the OR gate G25. The second selector can be controlled.

  Returning to FIG. 40, the data output terminal P <b> 21 of the scan FF circuit 51 a is connected to one of the inputs of the combinational circuit 31, and the scan-out terminal P <b> 22 is connected to the scan-in terminal P <b> 13 of the scan FF circuit 10. An output signal S31 that is one of the outputs of the combinational circuit 31 is connected to the data input terminal P121, and an output signal S32 that is one of the outputs of another combinational circuit 32 is connected to the data input terminal P120 of the scan FF circuit 10. Connected. That is, the output signal S32 is directly input as the data DATA0 of the scan FF circuit 10.

  In the integrated circuit having such a configuration, the output signal S32 is directly applied to the data input terminal P12 of the scan FF circuit 10 as data DATA0. That is, the signal input based on the output signal S31 to the data input terminal D of the flip-flop 11 of the scan FF circuit 10 needs to pass through the second data input signal propagation path including only the 2to1 selector 43 in the 3to1 selector 34. become.

  Thus, as is clear from the comparison of FIG. 39 and FIG. 40 (comparison of the first and second data input signal propagation paths), the OR is related to the setup timing condition regarding the input of the data DATA0 when the set function is added. Since there is no need to provide the gate G17, the integrated circuit constituted by the scan FF circuit 10 according to the tenth embodiment is relaxed, so that the signal propagation delay of the OR gate G17 can be increased. Play.

  Further, the 3to1 selector 34 is not configured as shown in FIG. 41, and the data DATA0, the power supply potential, and the scan-in signal SIN are selectively sent to the flip-flop 11 and the data input terminal D through one transfer gate or the like. Even in the case of the one-stage configuration to be connected, it is not necessary to provide the OR gate G17 for the data DATA0, so that the setup timing condition can be relaxed.

  In addition, when the scan enable signal SEN indicates the logical value “0”, the scan FF circuit 10 according to the tenth embodiment outputs the logical sum of the data DATA0 and the data DATA1 from the 2to1 selector 43 as shown in FIG. Can be output.

  As shown in FIGS. 39 and 40, the scan-out terminal P22 of the scan FF circuit 51a and the scan-in terminal P13 of the scan FF circuit 51b are directly connected, and the scan-out terminal P22 of the scan FF circuit 51a and the scan FF circuit 10 are connected. Since the scan-in terminal P13 is directly connected and the signal propagation delay time is small, the hold timing condition for the scan-in signal SIN becomes severe.

  Therefore, in the integrated circuit of FIG. 39, it is necessary to insert a buffer between the scan-out terminal P22 of the scan FF circuit 51a and the scan-in terminal P13 of the scan FF circuit 51b.

  However, in the integrated circuit of FIG. 39, the scan FF circuit 51b takes in the scan-in signal SIN to the data input terminal D of the flip-flop 11 through the one-stage 2to1 selector 62, whereas in the integrated circuit of FIG. Since the scan FF circuit 10 takes in the scan-in signal SIN to the data input terminal D of the flip-flop 11 via the two-stage 2to1 selectors 44 and 43, the signal propagation time for one 2to1 selector is integrated in FIG. More than a circuit.

  As is apparent from the comparison between FIGS. 39 and 40, the scan FF circuit 10 according to the tenth embodiment is used because the two-stage 2-to-1 selectors 44 and 43 are provided for the hold timing condition of the scan-in signal SIN. The integrated circuit constructed as described above has the effect of being relaxed.

(Other aspects)
FIG. 42 is a circuit diagram showing another aspect of the scan FF circuit of the tenth embodiment. As shown in FIG. 41, the scan FF circuit 10X of another mode shown in FIG. 42 is different from the scan FF circuit 10 shown in FIG. Hereinafter, different points will be mainly described.

  The OR gate G18 has one input connected to the scan-in terminal P13, the other input connected to the scan enable terminal P14, and the output connected to the “0” input of the 2to1 selector 433.

  The OR gate G18 applies the scan-in signal SIN to the “0” input of the 2to1 selector 43 when the scan enable signal SEN is “H”, and relates to the scan-in signal SIN when the scan enable signal SEN is “L”. Instead, the fixed value “H” is output to the “0” input of the 2to1 selector 43. Therefore, the scan FF circuit 10X behaves in the same manner as the truth table shown in FIG. 38, that is, can perform an operation equivalent to the scan FF circuit 10.

  Furthermore, when the scan FF circuit 10X is used instead of the scan FF circuit 10 of FIG. 40, the setup timing condition of the input of the data DATA0 is relaxed and the hold timing condition of the scan-in signal SIN when the set function is added. The mitigating effect can also be exhibited.

  Further, the scan circuit 10X can simplify the circuit configuration by configuring the 2to1 selector 44 of the scan FF circuit 10 with the OR gate G18.

It is a circuit diagram which shows the circuit structure of the scan FF circuit with a synchronous reset terminal which is Embodiment 1 of this invention. FIG. 2 is a circuit diagram showing an internal configuration of the flip-flop shown in FIG. 1. It is explanatory drawing which showed operation | movement of the scan FF circuit of Embodiment 1 shown in FIG.1 and FIG.2 in the truth table format. It is explanatory drawing which shows the internal structure of a synchronous reset signal generation circuit. FIG. 3 is a circuit diagram (conventional configuration) for explaining the effect of the first embodiment. FIG. 3 is a circuit diagram (configuration of the embodiment) for explaining the effect of the first embodiment. FIG. 6 is a circuit diagram illustrating another aspect of the scan FF circuit according to the first embodiment. It is a circuit diagram which shows the circuit structure of the scan FF circuit with a synchronous set terminal which is Embodiment 2 of this invention. It is explanatory drawing which showed the operation | movement of the scan FF circuit of Embodiment 2 shown in FIG. 8 in the truth table format. It is explanatory drawing which shows the internal structure of a synchronous set signal generation circuit. FIG. 10 is a circuit diagram (conventional configuration) for explaining the effect of the second embodiment. FIG. 10 is a circuit diagram (configuration of the embodiment) for explaining the effect of the second embodiment. FIG. 10 is a circuit diagram illustrating another aspect of the scan FF circuit according to the second embodiment. It is a circuit diagram which shows the circuit structure of the scan FF circuit with a synchronous reset terminal which is Embodiment 3 of this invention. FIG. 15 is an explanatory diagram showing the operation of the scan FF circuit of the third embodiment shown in FIG. 14 in a truth table format. It is explanatory drawing which shows the relationship between a scan enable signal and a synchronous reset signal in a tabular form. It is explanatory drawing which shows the internal structure of a synchronous reset signal and a scan enable signal generation circuit. FIG. 10 is a circuit diagram illustrating another aspect of the scan FF circuit according to the third embodiment. It is a circuit diagram which shows the circuit structure of the scan FF circuit with a synchronous set terminal which is Embodiment 4 of this invention. FIG. 20 is an explanatory diagram showing the operation of the scan FF circuit of the fourth embodiment shown in FIG. 19 in a truth table format. It is explanatory drawing which shows the relationship between a scan enable signal and a synchronous set signal in a table format. FIG. 10 is a circuit diagram illustrating another aspect of the scan FF circuit according to the fourth embodiment. It is a circuit diagram which shows the circuit structure of the scan FF circuit with a synchronous reset terminal which is Embodiment 5 of this invention. FIG. 10 is a circuit diagram illustrating another aspect of the scan FF circuit according to the fifth embodiment. It is a circuit diagram which shows the circuit structure of the scan FF circuit with a synchronous set terminal which is Embodiment 6 of this invention. FIG. 22 is a circuit diagram illustrating another aspect of the scan FF circuit according to the sixth embodiment. It is a circuit diagram which shows the circuit structure of the scan FF circuit with a synchronous reset terminal which is Embodiment 7 of this invention. FIG. 22 is a circuit diagram showing another aspect of the scan FF circuit according to the seventh embodiment. It is a circuit diagram which shows the circuit structure of the scan FF circuit with a synchronous set terminal which is Embodiment 8 of this invention. FIG. 20 is a circuit diagram illustrating another aspect of the scan FF circuit according to the eighth embodiment. It is a circuit diagram which shows the circuit structure of the scan FF circuit with a synchronous reset terminal which is Embodiment 9 of this invention. FIG. 32 is an explanatory diagram showing the operation of the scan FF circuit of the ninth embodiment shown in FIG. 31 in a truth table format. FIG. 20 is a circuit diagram (conventional configuration) for explaining the effect of the ninth embodiment. FIG. 22 is a circuit diagram for explaining the effect of the ninth embodiment (configuration of the embodiment); FIG. 20 is a circuit diagram illustrating details of a 3to1 selector in a scan FF circuit according to a ninth embodiment. FIG. 23 is a circuit diagram illustrating another aspect of the scan FF circuit according to the ninth embodiment. It is a circuit diagram which shows the circuit structure of the scan FF circuit with a synchronous set terminal which is Embodiment 10 of this invention. FIG. 38 is an explanatory diagram showing the operation of the scan FF circuit of the tenth embodiment shown in FIG. 37 in a truth table format. FIG. 22 is a circuit diagram (conventional configuration) for explaining the effect of the tenth embodiment. FIG. 22 is a circuit diagram for explaining the effect of the tenth embodiment (configuration of the embodiment). FIG. 29 is a circuit diagram illustrating details of a 3to1 selector in the scan FF circuit according to the tenth embodiment. FIG. 38 is a circuit diagram illustrating another aspect of the scan FF circuit according to the tenth embodiment. It is a circuit diagram which shows the internal structure of the conventional scan FF circuit.

Explanation of symbols

1-10, 1a, 1b, 1X, 2a, 2b, 2X-10X scan FF circuit, 11 flip-flop, 12-19, 23-30, 41-442 2to1 selector, 33, 34 3to1 selector, G9, G15, G16 , G31, G33, G35 AND gate, G12, G17, G18, G32, G34, G36 OR gate, G14 inverter.

Claims (26)

A scan flip-flop circuit (scan FF circuit) having a clock terminal, a data input terminal, a scan-in terminal, a data output terminal, and a scan-out terminal,
A flip-flop that captures the given data as stored data in synchronization with a clock input via the clock terminal, and outputs the stored data from at least one of the data output terminal and the scan-out terminal;
A first selector that performs a first selection operation of selecting and outputting one of a predetermined fixed value and a scan-in signal obtained from the scan-in terminal;
A second selector that selects one of the input data obtained from the data input terminal and the output of the first selector, and executes a second selection operation that outputs the selected data as data to be given to the flip-flop. ,
Scan FF circuit. The scan FF circuit according to claim 1,
A scan enable terminal and a synchronous fixed value setting terminal;
The first selector performs the first selection operation based on a scan enable signal obtained from the scan enable terminal;
The second selector performs the second selection operation based on a fixed value instruction signal obtained from the synchronous fixed value setting terminal;
Scan FF circuit. The scan FF circuit according to claim 2,
A signal setting function in which, when the scan enable signal instructs selection of the scan-in signal, the fixed value instruction signal is forcibly set to a value instructing selection of an output of the first selector;
Scan FF circuit. The scan FF circuit according to claim 1,
A scan enable terminal and a synchronous fixed value setting terminal;
The first selector performs the first selection operation based on a fixed value instruction signal obtained from the synchronous fixed value setting terminal;
The second selector performs the second selection operation based on a scan enable signal obtained from the scan enable terminal.
Scan FF circuit. The scan FF circuit according to claim 4,
At the time of scan shift, the fixed value instruction signal instructs selection of the scan-in signal, and the scan enable signal further includes a signal setting function that instructs selection of the output of the first selector.
Scan FF circuit. A scan FF circuit according to any one of claims 2 to 5,
The synchronous fixed value setting terminal includes a synchronous reset terminal for inputting a synchronous reset signal,
The predetermined fixed value includes a fixed value indicating a logical value “0”.
Scan FF circuit. A scan FF circuit according to any one of claims 2 to 5,
The synchronous fixed value setting terminal includes a synchronous set terminal for inputting a synchronous set signal,
The predetermined fixed value includes a fixed value indicating a logical value “1”.
Scan FF circuit. The scan FF circuit according to claim 2,
The synchronous fixed value setting terminal includes a synchronous reset terminal for inputting a synchronous reset signal,
The predetermined fixed value includes a fixed value indicating a logical value “0”;
The scan enable signal includes a signal indicating a logical value “1” at the time of scan shift,
The first selector includes an AND gate having the scan-in terminal and the scan enable terminal as one input and the other input,
Scan FF circuit. The scan FF circuit according to claim 2,
The synchronous fixed value setting terminal includes a synchronous set terminal for inputting a synchronous set signal,
The predetermined fixed value includes a fixed value indicating a logical value “1”;
The scan enable signal includes a signal indicating a logical value “1” at the time of scan shift,
The first selector includes an OR gate having the scan-in terminal and the scan enable terminal as one input and an inverted other input,
Scan FF circuit. The scan FF circuit according to claim 4,
The synchronous fixed value setting terminal includes a synchronous reset terminal for inputting a synchronous reset signal,
The predetermined fixed value includes a fixed value indicating a logical value “0”;
The synchronous reset signal includes a signal indicating a logical value “0” at the time of resetting;
The first selector includes an AND gate having the scan-in terminal and the synchronous reset terminal as one and the other inputs,
Scan FF circuit. The scan FF circuit according to claim 4,
The synchronous fixed value setting terminal includes a synchronous set terminal for inputting a synchronous set signal,
The predetermined fixed value includes a fixed value indicating a logical value “1”;
The synchronous set signal includes a signal indicating a logical value “0” when set,
The first selector includes an OR gate having the scan-in terminal and the synchronous set terminal as one input and an inverted other input,
Scan FF circuit. A scan flip-flop circuit (scan FF circuit) having a clock terminal, a data input terminal, a scan-in terminal, a data output terminal, and a scan-out terminal,
A flip-flop that captures the given data as storage data in synchronization with a clock input via the clock terminal and outputs the storage data via the data output terminal;
A first selection operation is performed in which one of the input data obtained from the data input terminal and the scan-in signal obtained from the scan-in terminal is selected and output as data to be given to the flip-flop. A selector,
A second selector that selects one of a predetermined fixed value and the stored data of the flip-flop and outputs the selected data from the scan-out terminal;
Scan FF circuit. The scan FF circuit according to claim 12,
A scan enable terminal and a synchronous fixed value setting terminal;
The first selector performs the first selection operation based on a fixed value instruction signal obtained from the synchronous fixed value setting terminal;
The second selector performs the second selection operation based on a scan enable signal obtained from the scan enable terminal.
Scan FF circuit. The scan FF circuit according to claim 12,
A scan enable terminal and a synchronous fixed value setting terminal;
The first selector performs the first selection operation based on a scan enable signal obtained from the scan enable terminal;
The second selector performs the second selection operation based on a fixed value instruction signal obtained from the synchronous fixed value setting terminal;
Scan FF circuit. The scan FF circuit according to claim 13 or 14,
The synchronous fixed value setting terminal includes a synchronous reset terminal for inputting a synchronous reset signal,
The predetermined fixed value includes a fixed value indicating a logical value “0”.
Scan FF circuit. The scan FF circuit according to claim 13 or 14,
The synchronous fixed value setting terminal includes a synchronous set terminal for inputting a synchronous set signal,
The predetermined fixed value includes a fixed value indicating a logical value “1”.
Scan FF circuit. The scan FF circuit according to claim 13,
The synchronous fixed value setting terminal includes a synchronous reset terminal for inputting a synchronous reset signal,
The predetermined fixed value includes a fixed value indicating a logical value “0”;
The scan enable signal includes a signal indicating a logical value “1” at the time of scan shift,
The first selector includes an AND gate having the stored data and the scan enable terminal of the flip-flop as one and the other inputs,
Scan FF circuit. The scan FF circuit according to claim 13,
The synchronous fixed value setting terminal includes a synchronous set terminal for inputting a synchronous set signal,
The predetermined fixed value includes a fixed value indicating a logical value “1”;
The scan enable signal includes a signal indicating a logical value “1” at the time of scan shift,
The first selector includes an OR gate having the storage data and the scan enable terminal of the flip-flop as one input and an inverted other input,
Scan FF circuit. The scan FF circuit according to claim 14,
The synchronous fixed value setting terminal includes a synchronous reset terminal for inputting a synchronous reset signal,
The predetermined fixed value includes a fixed value indicating a logical value “0”;
The synchronous reset signal includes a signal indicating a logical value “0” at the time of resetting;
The first selector includes an AND gate having the stored data and the synchronous reset terminal of the flip-flop as one and the other inputs,
Scan FF circuit. The scan FF circuit according to claim 14,
The synchronous fixed value setting terminal includes a synchronous set terminal for inputting a synchronous set signal,
The predetermined fixed value includes a fixed value indicating a logical value “1”;
The synchronous set signal includes a signal indicating a logical value “0” when set,
The first selector includes an OR gate having the stored data and the synchronous set terminal of the flip-flop as one input and an inverted other input,
Scan FF circuit. The scan FF circuit according to claim 1,
The data input terminal includes a first data input terminal for receiving first input data;
A scan enable terminal and a second data input terminal;
The first selector performs the first selection operation based on a scan enable signal obtained from the scan enable terminal;
The second selector executes the second selection operation based on the scan enable signal and second input data obtained from the second data input terminal;
Scan FF circuit. The scan FF circuit according to claim 21,
The predetermined fixed value includes a fixed value indicating a logical value “0”;
The scan enable signal includes a signal indicating a logical value “1” at the time of scan shift,
The first selector outputs the predetermined fixed value when the scan enable signal indicates a logical value “0”;
When the scan enable signal indicates a logical value “0”, the second selector selects the first input data / the predetermined fixed value based on “1” / “0” of the second input data. Output,
Scan FF circuit. The scan FF circuit according to claim 22,
The first selector includes an AND gate having the scan-in signal and the scan enable signal as one input and the other input,
Scan FF circuit. The scan FF circuit according to claim 21,
The predetermined fixed value includes a fixed value indicating a logical value “1”;
The scan enable signal includes a signal indicating a logical value “1” at the time of scan shift,
The first selector outputs the predetermined fixed value when the scan enable signal indicates a logical value “0”;
When the scan enable signal indicates a logical value “0”, the second selector selects the first input data / the predetermined fixed value based on “0” / “1” of the second input data. Output,
Scan FF circuit. The scan FF circuit according to claim 24,
The first selector includes an OR gate having the scan-in signal and the scan enable signal as one input and an inverted other input,
Scan FF circuit. A scan flip-flop circuit (scan FF circuit) having a clock terminal, first and second data input terminals, a scan-in terminal, a scan enable terminal, a data output terminal, and a scan-out terminal;
A flip-flop that captures the given data as stored data in synchronization with a clock input via the clock terminal, and outputs the stored data from at least one of the data output terminal and the scan-out terminal;
Based on a scan enable signal obtained from the scan enable terminal and second input data obtained from the second data input terminal, first input data obtained from the first data input terminal, a predetermined fixed value, and A selector that selects one of the scan-in signals obtained from the scan-in terminal and performs a selection operation that outputs the selected signal as data to be given to the flip-flop;
Scan FF circuit.

Images