JP2007164415A - Data transfer controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer controller capable of easily changing a bus width of an external memory device according to processing contents required to a system, and efficiently using the band width with an architecture wherein burst access is remarked. <P>SOLUTION: This data transfer controller has: a buffer group 21 incorporating FIFO type buffers 21-1 to 21-n of one kind each having a bit width larger than a client data width; a command generation circuit 25 generating a command and an address of a memory device 30 based on at least a command and an address received from a master device; and a command decoding circuit 26 issuing the address and the command for making access be performed by a burst length preset according to the bus width of the memory device 30 based on the command and the address generated in the command generation circuit 25, and controlling writing or reading of data to the buffer group 21. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer control device that controls access to an external memory device when the data bus width of the memory and the input / output interface side are different, and in particular from a plurality of devices (clients) to the external memory device. The present invention relates to a data transfer control device that controls access to the data.

  Various devices have been proposed for controlling access to an external memory device when the data bus width of the memory is different from that of the input / output interface (see, for example, Patent Documents 1, 2, or 3).

The apparatus described in Patent Document 1 is a data processing apparatus that is connected to a plurality of master devices and one memory device, and performs data transfer between the memory device and each master device.
This data processing apparatus has two points, a memory bus connected to the memory device at one point, each having two or more points, and each master device at one or more points. Reads data from and writes data to a plurality of connected local buses and memory devices. On each local bus, data is transferred at a transfer rate required by each master device. A transfer controller for transferring data at a transfer rate required by the device, a plurality of buffers connected at the other point of the memory bus and one point of each local bus, the memory bus and the local bus Multiple local buffers that input and output data to absorb differences in transfer rates between The has.

  In the DMA transfer method described in Patent Document 2, in a data transfer by DMA between devices having different bit widths on the same bus, a bi-directional FIFO capable of bit width conversion between the devices and incorporating a DMA control function is used. Relay.

The data transfer device described in Patent Document 3 is a data transfer device that DMA-transfers data between an input / output I / F and a memory, and includes a data bus width of the input / output I / F, a memory A register unit that stores information on the data bus width and DMA transfer direction, and data from a transfer source that is one of the input / output I / F and the memory are input, and the other of the input / output I / F and the memory The transfer unit adjusts the number of bits of data from the transfer source to the number of bits according to the data bus width of the transfer destination based on the information stored in the register unit. The adjustment part which performs.
Japanese Patent No. 332790 Japanese Patent No. 3544146 JP 2002-132705 A

However, in the device described in Patent Document 1, the arbitration circuit is influenced by the transfer rate of the local bus, and the memory bus is separated and connected to the local bus. Can not do it.
Therefore, the power consumption of the external memory device is small and the demand for DDR and DDR2 having a high bandwidth cannot be satisfied.

The devices described in Patent Documents 2 and 3 are accesses between one master device (client) and one memory device, and access between a plurality of master devices (clients) and one memory device is completely different. Not disclosed.
Furthermore, in the apparatus of Patent Document 2, it is necessary to incorporate two types of FIFO buffers inside, and as a result, each client depends on the data width of the external device in the interface design.

  It is an object of the present invention to provide a data transfer control device that can easily change the bus width of an external memory device according to the processing content required for the system and can efficiently use the bandwidth with an architecture that is aware of burst access. is there.

  A first aspect of the present invention is a data transfer control device that is connected to a plurality of master devices and a memory device and performs data transfer control between the memory device and each master device. A buffer group including a plurality of FIFO buffers having a bit width larger than the client data width corresponding to the master device and having the same bit width, and the master device Based on at least the address and command received from the memory device, the address of the memory device, a command generation circuit for generating the command, and the address and command generated by the command generation circuit, depending on the bus width of the memory device. Access using a preset burst length That the command and address issued to the memory device, and a command decode circuit for controlling reading or writing of data to the buffer group.

  A second aspect of the present invention is a data transfer control device that is connected to a plurality of master devices and a memory device and performs data transfer control between the memory device and each master device. A buffer group including a plurality of FIFO buffers having a bit width larger than the client data width corresponding to the master device and having the same bit width, and the master device Based on at least the address and command received from the memory device, the address of the memory device, a command generation circuit for generating the command, and the address and command generated by the command generation circuit, depending on the bus width of the memory device. Access using a preset burst length Command decode circuit that controls the reading and writing of data to the buffer group and a processing request to access the memory device with the highest priority from one master device. And an arbitration circuit that gives a memory access right to the one master device with the highest priority and outputs at least an address and a command from the master device to the command generation circuit.

  Preferably, the arbitration circuit outputs the address and command to the command generation circuit in response to a request signal from the command generation circuit.

  Preferably, when the command generation circuit receives a request signal from the command decoding circuit, the command generation circuit issues the request signal to the arbitration circuit.

  Preferably, when the access to the memory device is an access for writing (write), the command decode circuit reads data from the corresponding FIFO buffer in a cycle according to the bus width of the memory device, Data read from the buffer is shifted by a data unit corresponding to a predetermined bus width, and the memory device is accessed.

  Preferably, when the access to the memory device is an access for reading (reading), the command decoding circuit writes the read data into the corresponding FIFO type buffer at different timings for each bus width of the memory device. .

  Preferably, when the access to the memory device is an access for reading (reading), the command decode circuit writes the FIFO buffer in the bit width unit in the FIFO buffer corresponding to the read data, and At the time of writing, data is written to the FIFO buffer in a cycle corresponding to the bus width of the memory device.

According to the present invention, the bus width of the external memory device can be easily changed according to the processing content required for the system.
In addition, there is an advantage that the bandwidth can be efficiently used in an architecture in consideration of burst access.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a first configuration example of the data transfer control system according to the embodiment of the present invention, and FIG. 2 is a block diagram showing a second configuration example of the data transfer control system according to the embodiment. FIG. FIG. 1 and FIG. 2 show the overall configuration when DDR2 is used with an external device memory as a target.

The data transfer control systems 10 and 10 </ b> A have a CPU 50 as a processing device including a data transfer control device 20, an external memory device 30, a plurality of master devices 40-0 to 40 -n, and a setting register 51.
The bus width of the external memory device 30 in FIG. 1 according to this embodiment is 32 bits (bit), and the bus width of the external memory device 30A in FIG. 2 is 16 bits (bit).
The data transfer control system 10 in FIG. 1 differs from the data transfer control system 10A in FIG. 2 in that the bus width of the external memory device 30 is 32 bits and 16 bits, and the other basic architecture is the same. It is. Therefore, in FIG. 1 and FIG. 2, the same functional parts are represented by the same reference numerals.

  As shown in the figure, the data transfer control device 20 includes a buffer group 21 having 128-bit FIFO type buffers 21-1 to 21-n, an arbitration circuit 22, a write (write) data ordering circuit 23, and a read (read) data. An ordering circuit 24, a DDR command generation circuit 25, and a DDR command decode circuit 26 are provided.

As a feature of using DDR2, since the external memory device 30 is operated at an operating frequency that is twice the internal bus operating frequency, it is possible to access data that is four times the data width of the external memory device 30 per cycle of the internal bus operating clock. It is.
The operating frequencies of the internal blocks are the same except for the FIFO type buffers 21-1 to 21-n. Each master device (each client) 40-1 to 40-n need not have the same frequency.

  As a feature of the present embodiment, access from a plurality of master devices (clients) 40-0 to 40-n passes through the internal 128-bit FIFOs 21-1 to 21-n so that the internal data width is aligned to 128 bits. In addition, the circuit configuration takes into account the burst access to the external memory device 30 in the basic operation.

  In this embodiment, when the external memory device is 32 bits wide, it is determined to be 4 bursts, and when it is 16 bits wide, it is determined to be 8 burst accesses. Further, by multiplexing commands of 4 banks, 512 bits are the smallest unit access. Is configured to do.

FIGS. 3A to 3G are diagrams illustrating command examples of 4 bursts × 2 access per bank in the present embodiment.
In this embodiment, the reason why the burst length is fixed is that when the external memory device 30 is 32 bits, this 128-bit data becomes data for one access (because the burst length is fixed to 4), In the case of 16 bits, this 128 bit data becomes data for two accesses (because the burst length is fixed at 8), and the burst access to the external memory device 30 can be controlled by the internal bus clock CLK and the bus band. This is to make effective use of the width.

  Next, the configuration and function of each block of the data transfer control device 20 of this embodiment will be described.

When there is a processing request that has to be stored in the external memory device 30 or read from the external memory device 30 with the highest priority from a certain master device (client), the arbitration circuit 22 receives the request from the master device (in FIG. 1). The memory access right is given to the master device 40-0) with the highest priority.
For example, in a video signal processing system, a master device (client) that must store an image in a memory with the highest priority must guarantee the latency and bandwidth. Rights are granted.
However, it is necessary to perform asynchronous control inside the master device (client).
Upon receiving the request signal REQ25 from the DDR command generation circuit 25, the arbitration circuit 22 outputs the address ADR, the read / write command R / WCMD22, and the count value CNT22 to the DDR command generation circuit 25.

The buffer group 21 includes one type of FIFO buffer larger than the client data width for each master device (client) 40-0 to 40-n.
In the present embodiment, 128-bit width FIFO type buffers 21-1 to 21-n are incorporated.
As described above, in the present embodiment, the FIFO buffer larger than the client data width is incorporated in order to make the circuit configuration easy to control in order to make use of the features of DDR and DDR2 and burst access.
In this case, since the data width of the internal FIFO type buffers 21-1 to 21-n does not change even if the data width of the external memory device 30 changes, each client can be designed as an interface independent of the data width of the external device. Can be shared by each client.
In the buffer group 21, although the priority is lower than that of the highest-priority master device (client), an image format conversion client or the like that must guarantee the latency and the bandwidth passes the FIFO buffer, thereby ensuring the latency and the bandwidth. Is realized.
Since the image format conversion client or the like can realize asynchronous control with a FIFO buffer, it is not necessary to have an asynchronous control circuit in each master device (client).

  A write data ordering circuit 23 converts data into a data format (endian, data mask, etc.) corresponding to an access command requested by each master device (client) 40-0 to 40-n.

  A read data ordering circuit 24 converts data read from the external memory device 30 into a data format required by each master device (client) 40-0 to 40-n.

The DDR command generation circuit 25 receives the address ADR, the read / write command R / WCMD22, and the count value CNT22 issued from each master device (client) 40-0 to 40-n from the arbitration circuit 22, and receives the DDR2 Address generation and DDR2 internal command CMD2.
The DDR command generation circuit 25 also detects an address error.

4A to 4H are diagrams showing examples of timing charts of the DDR command generation circuit 25 according to this embodiment. FIG. 4A shows the internal clock CLK, and FIG. 4B shows the arbitration circuit 22. Read / write command R / WCMD22, FIG. 4C shows the count value CNT22 from the arbitration circuit 22, FIG. 4D shows the valid signal VLD22 of the arbitration circuit 22, and FIG. 4F shows the internal command CMD2, FIG. 4G shows the valid signal VLD25 of the command generation circuit 25, and FIG. 4H shows the request signal REQ26 from the command decode circuit 26, respectively. Show.

  In terms of processing, when the DDR command generation circuit 25 receives the request signal REQ26 from the DDR command decode circuit 26, it issues the request signal REQ25 to the arbitration circuit 22, and receives the address ADR, the read / write command R / WCMD22, and the count value CNT22. The internal command CMD2 is generated from the read / write command R / WCMD22 and the count value CNT22.

4A to 4H, a command CMD2 “Read2” is generated as shown in FIG. 4F, and the DDR2 command decode circuit 26 is internally connected as shown in FIG. 4G. The valid signal VLD is set to a high level so that it can be seen that the command generation is completed.
As shown in FIGS. 4G and 4H, if the valid signal VLD25 is at a high level and the request signal REQ26 is input from the DDR command decode circuit 26, the valid signal VLD25 is set to a low level in the next cycle. In order to receive the next address ADR, the read / write command R / WCMD22, and the count value CNT22, the request signal REQ25 is output to the arbitration circuit 22.

FIG. 5 is a flowchart showing an operation procedure of the DDR command generation circuit 25 according to the present embodiment.
Here, although there is a part overlapping the above description, a more specific operation in the DDR command generation circuit 25 will be described with reference to the flowchart of FIG.

Step ST1 :
When receiving the request signal REQ 26 from the DDR command decoding circuit 26, the DDR command generation circuit 25 issues a request signal REQ 25 to the arbitration circuit 22.
Step ST2 :
The DDR command generation circuit 25 receives the address ADR, the read / write command R / WCMD, and the count value CNT output from the arbitration circuit 22 in response to the request signal REQ25.

Step ST3 :
The DDR command generation circuit 25 generates an address for DDR based on the address ADR received from the arbitration circuit 22 and the count value CNT22.
Step ST4 :
The DDR command generation circuit 25 compares the generated address with the memory capacity and checks whether it is within the capacity range.
Step ST5 :
When it is determined in step ST4 that the address is within the memory capacity range, the DDR command generation circuit 25 outputs the generated address to the DDR command decode circuit 26.
Step ST6 :
In step ST4, if the address is outside the memory capacity range, the DDR command generation circuit 25 issues an address error.

Step ST7 :
The DDR command generation circuit 25 generates an internal command CMD2 from the read / write command R / WCMD received from the arbitration circuit 22 and the count value CNT22.
Step ST8 :
Then, the DDR command generation circuit 25 sets the valid signal VLD25 to the DDR command decode circuit 26 to a high level and outputs the generated command CMD2 to the DDR command decode circuit 26.
Step ST9 :
Upon receiving the request signal REQ26 from the DDR command decode circuit 26, the DDR command generation circuit 25 switches the valid signal VLD25 to the low level and issues the request signal REQ25 to the arbitration circuit 22.

The DDR command decode circuit 26 decodes the internal command CMD2 for DDR2 generated by the DDR command generation circuit 25, and issues a command and address for performing access with a burst length fixed to 4 to the external memory device 30 side. Is configured to do.
In the present embodiment, the specification is such that the commands of the four banks of the external memory device 30 are multiplexed and the external memory device 30 is accessed in units of a minimum of 512 bits (128 × 4).
This 4-bank command multiplexing corresponds to the execution command line shown in FIG.

  The burst length in the DDR command decode circuit 26 is fixed, and access to the external memory device 30 by command multiplexing of four banks can effectively use the bandwidth of the bus.

  Further, in the present embodiment, as shown in FIG. 2, even if the bus width of the external memory device 30 is 16 bits, which is 1/2 of 32 bits, the burst length is doubled to 8 so that the 512 bit unit is obtained. An access specification is realized, and a memory controller independent of an external memory device is realized.

Write access to the external memory device 30 converts 128-bit data into 32-bit data as shown in FIGS. 6A to 6E regardless of the data width of the external memory device. Depending on the bus width, the configuration of this 32-bit data differs.
When the bus width of the external memory device 30 is 32 bits, the DDR command decode circuit 26 reads out 128 bits of data every cycle and shifts the data in units of 32 bits as shown in FIGS. 7A to 7C. 30 is accessed.
On the other hand, when the external memory device 30 is 16 bits, as shown in FIGS. 8A to 8C, the 128-bit data is read once every two cycles, and the 128-bit data filled with the dummy data (0) is read. The data is generated and shifted in 32-bit data units in which the upper 16 bits are zero-padded to access the external memory device 30.

In addition, as shown in FIGS. 9A to 9L, the read access is performed by combining 32-bit data into 128-bit data and writing them into the FIFO type buffers 21-1 to 21-n regardless of the external memory device 30. Depending on the data width of the memory device 30, the write timing to the FIFO type buffers 21-1 to 21-n differs.
When the external memory device 30 is 32 bits, the DDR command decode circuit 26 writes 128-bit data to the FIFO type buffers 21-1 to 21-n every cycle as shown in FIGS.
On the other hand, when the external memory device 30 is 16 bits, as shown in FIGS. 11A to 11C, 128-bit data is written to the FIFO buffers 21-1 to 21-n once every two cycles.

  FIG. 12 is a flowchart showing an operation procedure of the DDR command decode circuit 26 according to the present embodiment.

Step ST11 :
The DDR command decode circuit 26 accesses the setting register 51 and determines the data width of the external memory device 30 based on the setting data.
Step ST12 :
If it is determined in step ST11 that the bit width is 32 bits corresponding to the circuit of FIG. 1, the DDR command decode circuit 26 uses the internal command CMD2 transferred from the DDR command generation circuit 25 to determine whether it is a write access. Determine whether the access is for the lead.
Step ST13 :
If it is determined in step ST12 that the access is for writing, the DDR command decode circuit 26 reads out data in every cycle from the internal FIFO type buffer 21 (-1 to -n) in accordance with the count number in units of 128 bits.
Step ST14 :
The DDR command decode circuit 26 measures the output timing based on the write command timing, and outputs the write data to the data line to the external memory device 30 by 32 bits.
Step ST15 :
On the other hand, if it is determined in step ST12 that the access is for reading, the DDR command decoding circuit 26 issues a timing at which data is read after issuing a read command from information such as CAS latency in the setting register 51. Measured, 4 burst data, that is, 128 bits are taken into the FIFO buffer 21 (-1 to -n).

Step ST16 :
If it is determined in step ST11 that the bit width is 16 bits corresponding to the circuit of FIG. 2, the DDR command decode circuit 26 determines whether the access time, that is, the write access is based on the internal command CMD2 transferred from the DDR command generation circuit 25. Determine whether the access is for the lead.
Step ST17 :
If it is determined in step ST15 that the access is for writing, the DDR command decode circuit 26 receives data from the internal FIFO type buffer 21 (-1 to -n) at a timing of once every two cycles in accordance with the count number. Read in 128-bit units.
Step ST18 :
The DDR command decode circuit 26 divides the read 128-bit data into 16-bit units, and embeds (sets) the 128-bit data embedded in the port side where no external memory device exists so as to be output for two cycles. Generate.
Step ST19 :
The DDR command decode circuit 26 measures the output timing based on the write command timing, and outputs the valid data to the data line to the external memory device 30 16 bits at a time. 0 is output to a port (16 bits) in which no memory exists.
Step ST20 :
On the other hand, if it is determined in step ST16 that the access is for reading, the DDR command decoding circuit 26 issues a timing at which data is read after issuing a read command from information such as CAS latency in the setting register 51. Measured, 4 burst data, that is, 128 bits are taken into the FIFO buffer 21 (-1 to -n).
Step ST21 :
Since this data includes dummy data, the dummy data is removed from the 256-bit data for two cycles, 128-bit valid data is generated, and taken into the FIFO buffer 21 (−1 to −n).

In a system in which the transfer rate of the external memory device is less than half as a system request by realizing the data transfer control device 20 as a memory controller independent of the external memory device 30, a mode in which a command with a burst length fixed to 8 is generated Can be handled by simply halving the data width of the external memory device, leading to a reduction in the cost of the external memory device.
In addition, it is possible to avoid manufacturing LSIs specialized for high-speed specifications and low-spec specifications, thereby reducing manufacturing costs and mass production, resulting in reduction of costs.

Finally, as an application example, a case where DDR is used for an external memory device will be described.
First, since the memory command is different from that of DDR2, the DDR command decoding circuit is modified for DDR.
Then, the external memory device 30 is replaced with a 32-bit width DDR, the burst length is fixed to 4, and the commands of 4 banks are multiplexed to perform access, but the DDR is per cycle of the internal bus operation clock. Since data twice as large as the external memory data width can be accessed, there is a demerit that the bandwidth is halved compared to DDR2.
In such a case, the data width of the external device is set to double 64 bits, and the data width of the code circuit is corrected to 64 bits with a DDR command.
As for the command itself, the burst length is fixed to 4, and there is no change in access by command multiplexing of 4 banks. Therefore, a bus control device for a DDR memory can be realized only by correcting the DDR command decode circuit.

  In addition, a similar system other than the video signal processing system can be applied.

As described above, according to the present embodiment, each internal client is not affected by the size of the external memory device, so that this LSI is diverted to a system with low specification specifications at an external memory device cost suitable for the system. it can.
Since the access to the external memory device is fixed to only burst access of a certain burst length, the command issue timing can be optimized, and the bandwidth of the external memory device can be used more efficiently. As a result, the bandwidth of the internal bus Higher values can be obtained, and the bandwidth required by each client can be satisfied.

In this embodiment, each master device (client) is different in that one kind of FIFO buffer larger than the client data width is incorporated. The reason why the FIFO buffer larger than the client data width is built in the present invention is to make the circuit configuration easy to control in order to take advantage of the features of DDR and DDR2 and burst access.
Even if the data width of the external device changes, the data width of the internal FIFO does not change. Therefore, each client can be designed to have an interface independent of the data width of the external device and can be shared by each client.

  Furthermore, the present invention can efficiently use the bandwidth of the memory device by limiting the access to the external memory device to burst access.

That is, the data transfer control device 20 according to the present embodiment is a bus control device that can easily change the bus width of the external memory device in accordance with the processing content required for the system. , You can access it without worrying, and you don't have to make logical changes. Since the plurality of clients are structured to access the internal FIFO without being aware of the bus width of the external memory device, it is not necessary to logically modify the client.
A memory bus control device conscious of burst transfer, which is a feature of DDR / SDRAM and DDR2 / SDRAM, can efficiently use the bandwidth of a memory device in access control from a plurality of clients to one memory device.

It is a block diagram which shows the 1st structural example of the data transfer control system which concerns on embodiment of this invention. It is a block diagram which shows the 2nd structural example of the data transfer control system which concerns on embodiment of this invention. In this embodiment, it is a figure which shows the example of a command of 4 burst x2 access per bank. It is a figure which shows the example of a timing chart of the DDR command generation circuit which concerns on this embodiment. It is a flowchart which shows the operation | movement procedure of the DDR command generation circuit which concerns on this embodiment. 4 is a timing chart of write access to an external memory device of a DDR command decode circuit according to the present embodiment. 6 is a timing chart of write access when the bus width of the external memory device is 32 bits. 10 is a timing chart of write access when the bus width of the external memory device is 16 bits. 6 is a timing chart showing the timing of writing to the FIFO buffer at the time of read access to the external memory device of the DDR command decode circuit according to the present embodiment. 10 is a timing chart showing the timing of writing to a FIFO buffer during read access when the bus width of the external memory device is 32 bits. 10 is a timing chart showing the timing of writing to a FIFO buffer during read access when the bus width of the external memory device is 16 bits. 3 is a flowchart showing an operation procedure of a DDR command decode circuit 26 according to the present embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,10A ... Data transfer control system, 20 ... Data transfer control apparatus, 21 ... Buffer group, 21-1 to 21-n ... 128 bit width FIFO type buffer, 22 ... Arbitration circuit , 23 ... Write (write) data ordering circuit, 24 ... Read (read) data ordering circuit, 25 ... DDR command generation circuit, 26 ... DDR command decode circuit, 30, 30A ... External Memory device, 40-0 to 40-n... Master device, 50... CPU, 51.

Claims (14)

A data transfer control device that is connected to a plurality of master devices and a memory device and performs data transfer control between the memory device and each master device,
A buffer group which is arranged in a data interface unit with each master device and includes a plurality of FIFO buffers having a bit width larger than a client data width corresponding to the master device and unified in the bit width; ,
A command generation circuit for generating an address and a command of the memory device based on at least an address and a command received from the master device;
Based on the address and command generated by the command generation circuit, the memory device is issued with a command and an address to be accessed with a burst length set in advance according to the bus width of the memory device, and the buffer group And a command decode circuit for controlling reading or writing of data with respect to the data transfer control device. When the access to the memory device is an access for writing (write), the command decode circuit reads data from the corresponding FIFO buffer in a cycle corresponding to the bus width of the memory device, and has a predetermined bus width. The data transfer control device according to claim 1, wherein data read from the buffer is shifted in units of data corresponding to the data to access the memory device. 2. When the access to the memory device is an access for reading (reading), the command decoding circuit writes the read data to the corresponding FIFO type buffer at a different timing for each bus width of the memory device. Data transfer control device. When the access to the memory device is an access for reading (reading), the command decoding circuit writes the read type data into the corresponding FIFO type buffer in the bit width unit, and at the time of the writing, 4. The data transfer control device according to claim 3, wherein the data is written into the FIFO buffer in a cycle corresponding to the bus width of the memory device. When the access to the memory device is an access for writing (write), the command decode circuit reads data from the corresponding FIFO buffer in a cycle corresponding to the bus width of the memory device, and has a predetermined bus width. The read data from the buffer is shifted by the data unit corresponding to the above, and the memory device is accessed,
2. When the access to the memory device is an access for reading (reading), the command decoding circuit writes the read data to the corresponding FIFO type buffer at a different timing for each bus width of the memory device. Data transfer control device. When the access to the memory device is an access for writing (write), the command decode circuit reads data from the corresponding FIFO buffer in a cycle corresponding to the bus width of the memory device, and has a predetermined bus width. The read data from the buffer is shifted by the data unit corresponding to the above, and the memory device is accessed,
When the access to the memory device is an access for reading (reading), the command decoding circuit writes the read type data into the corresponding FIFO type buffer in the bit width unit, and at the time of the writing, The data transfer control device according to claim 1, wherein the data is written into the FIFO type buffer in a cycle corresponding to the bus width of the memory device. A data transfer control device that is connected to a plurality of master devices and a memory device and performs data transfer control between the memory device and each master device,
A buffer group which is arranged in a data interface unit with each master device and includes a plurality of FIFO buffers having a bit width larger than a client data width corresponding to the master device and unified in the bit width; ,
A command generation circuit for generating an address and a command of the memory device based on at least an address and a command received from the master device;
Based on the address and command generated by the command generation circuit, the memory device is issued with a command and an address to be accessed with a burst length set in advance according to the bus width of the memory device, and the buffer group A command decode circuit for controlling reading or writing of data with respect to
When there is a processing request to access the memory device with the highest priority from one master device, the memory access right is given to the one master device with the highest priority, and at least the address and command from the master device are generated. A data transfer control device comprising: an arbitration circuit that outputs the circuit. The data transfer control device according to claim 7, wherein the arbitration circuit outputs the address and command to the command generation circuit in response to a request signal from the command generation circuit. The data transfer control device according to claim 8, wherein the command generation circuit issues a request signal to the arbitration circuit when receiving a request signal from the command decoding circuit. When the access to the memory device is an access for writing (write), the command decode circuit reads data from the corresponding FIFO buffer in a cycle corresponding to the bus width of the memory device, and has a predetermined bus width. The data transfer control device according to claim 7, wherein data read from the buffer is shifted in units of data corresponding to the data to access the memory device. 8. When the access to the memory device is an access for reading (reading), the command decoding circuit writes the read data into the corresponding FIFO type buffer with different timing for each bus width of the memory device. Data transfer control device. When the access to the memory device is an access for reading (reading), the command decoding circuit writes the read type data into the corresponding FIFO type buffer in the bit width unit, and at the time of the writing, The data transfer control device according to claim 11, wherein the data is written into the FIFO buffer in a cycle corresponding to the bus width of the memory device. When the access to the memory device is an access for writing (write), the command decode circuit reads data from the corresponding FIFO buffer in a cycle corresponding to the bus width of the memory device, and has a predetermined bus width. The read data from the buffer is shifted by the data unit corresponding to the above, and the memory device is accessed,
8. When the access to the memory device is an access for reading (reading), the command decoding circuit writes the read data into the corresponding FIFO type buffer with different timing for each bus width of the memory device. Data transfer control device. When the access to the memory device is an access for writing (write), the command decode circuit reads data from the corresponding FIFO buffer in a cycle corresponding to the bus width of the memory device, and has a predetermined bus width. The read data from the buffer is shifted by the data unit corresponding to the above, and the memory device is accessed,
When the access to the memory device is an access for reading (reading), the command decoding circuit writes the read type data into the corresponding FIFO type buffer in the bit width unit, and at the time of the writing, 8. The data transfer control device according to claim 7, wherein the data is written into the FIFO buffer in a cycle corresponding to the bus width of the memory device.

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