JP2007164354A - Information processor and method of controlling same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor for changing the operation mode of hardware while maintaining a system operation. <P>SOLUTION: The information processor includes a processor 100 for performing various arithmetic processing according to an applied instruction S1 and a console 600 having a plurality of operation modes for specifying the operating state of the processor 100 for monitoring the operating state of the processor 100. The console 600 outputs an operation mode change request S2 to change the operation mode according to the operating state of the processor 100, and the processor 100 outputs instruction completion notification S3 when the arithmetic processing which is processed at present ends. This information processor is provided with an instruction management part 170 for, when the operation mode change request S2 is output from the console 600, instructing the processor 100 to change the operation mode after the instruction notification S3 is output from the processor 100. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, and more particularly to control capable of dynamically changing an operation mode of a processor.

  Conventionally used information processing apparatuses are provided with a plurality of operation modes suitable for processing in general, and an appropriate operation mode is selected from these operation modes as required.

  In such an information processing apparatus, a hardware operation mode realized in hardware has not been dynamically changed in a state where a conventional operation system and a user process are operating.

  This is because malfunction may occur when the operation mode is dynamically changed depending on the operation state in the information processing apparatus.

  In addition, because it was difficult to dynamically change the operation mode of the information processing device, when the hardware operation mode was changed, the operation system that once operated the information processing device was shut down to operate the entire information processing device. The operation mode of the hardware was changed after stopping.

  Also, when changing the operating mode in software, it is necessary to monitor the status of the process being executed by the operating system, interrupt the task, and insert a hardware mode changing routine. It was. For this reason, changing the operation mode in software during execution of a large-scale program that operates on a multiprocessor has a great influence.

  As a conventional example of such an information processing apparatus, there is a register setting method in which the contents of the data generation unit are set to the operation mode in accordance with the contents of the address generation unit via an external interface when a switch is switched or a system reset occurs. It is disclosed (see Patent Document 1).

Also disclosed is an information processing apparatus that operates dynamically in two or more operation modes and operates an application in each operation mode, and that normally operates device drivers and resident programs that are unaware of the operation mode switching. (See Patent Document 2).
Japanese Patent Laid-Open No. 11-098213 Japanese Patent Laid-Open No. 06-236286

  As described above, when changing the hardware operation mode in the conventional information processing apparatus system, the hardware level operation mode cannot be changed dynamically without malfunction during the system operation. There was a problem that the operation mode could not be changed without re-initialization.

  In addition, when changing the operation mode in software, it is impossible to grasp all the operation states of complex processors on the software side, so it is easy to generate hardware operation mode change timing in software. There was a problem that could not.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus capable of reliably changing the hardware operation mode without malfunctioning while continuing system operation even in a computer system in which it is difficult to stop the system for operation. is there.

In order to achieve the above object, a first invention of an information processing apparatus according to the present invention has a processor that performs various arithmetic processes according to a given instruction sequence, and has a plurality of operation modes that define the operating state of the processor. In an information processing apparatus having a console for monitoring the operating state of the processor,
The console outputs an operation mode change request to change the operation mode according to the operation state of the processor;
The processor outputs an instruction completion notice when the arithmetic processing currently being processed is completed,
When the operation mode change request is output from the console, the information processing apparatus includes an instruction management unit that instructs the processor to change the operation mode after the instruction completion notification is output from the processor.

A second invention is the information processing apparatus according to the first invention, wherein:
The in-order processing until the processing of the in-order pre-instruction is completed when the instruction sequence includes an in-order pre-instruction for performing predetermined processing and an in-order processing instruction requiring processing by the in-order pre-instruction. An issuance control unit for stopping the issuance of an instruction and outputting a notice to that effect to the instruction management unit;
The command management unit outputs a standby end notification to the issue control unit when the command completion notification is output after the issue standby notification is output,
The issuance control unit is configured to issue the in-order processing command upon receiving the standby end notification.

A third invention is the information processing apparatus according to the first or second invention, wherein
When the operation mode change request is output from the console, the diagnostic processor further outputs to the command management unit as a mode change notification in response to the operation mode change request,
The instruction management unit
The E bit that is set when the instruction completion notification is received from the processor, the I bit that is set when the issuance waiting notification is received from the issuance control unit, and the mode change notification are received from the diagnostic processor A status register consisting of a C bit set when
Reset the E bit when the instruction sequence is being executed by the processor;
Resetting the I bit when the instruction management unit outputs the standby end notification,
The C bit is reset when an instruction to change the operation mode to the processor is completed.

A fourth invention is the information processing apparatus according to the third invention, wherein
The instruction management unit notifies the issuance control unit of an operation status indicating an instruction execution state of the processor with respect to a set or reset state of each of the E bit, the I bit, and the C bit.

A fifth invention is the information processing apparatus according to the fourth invention, wherein:
In response to the mode change notification, an instruction to start changing the operation mode issued from the instruction management unit to the diagnostic processor is rewritable by the diagnostic processor, and further includes an operation mode register corresponding to the operation mode,
When the C bit is set in response to the mode change notification, the instruction management unit sets the operation mode register to the diagnostic processor when the E bit is set and the I bit is reset. The operation mode is instructed by rewriting through the network.

According to a sixth aspect of the present invention, there is provided a processor that performs various arithmetic processes according to a given instruction sequence, an instruction management unit that defines an operation state of the processor in one of a plurality of operation modes according to an output of the processor, In a control method of an information processing apparatus comprising a console that monitors the operating state of a processor,
Outputting an operation mode change request for changing the operation mode according to the operation state of the processor, performed at the console;
A step of outputting an instruction completion notification when the arithmetic processing performed by the processor is being performed;
And an instruction for instructing the processor to change the operation mode when the instruction completion notification is output from the processor after the operation mode change request from the console. It is a control method of a processing apparatus.

According to a seventh aspect of the present invention, there is provided a processor that performs various kinds of arithmetic processing according to a given instruction sequence, an instruction management unit that defines an operation state of the processor in one of a plurality of operation modes according to an output of the processor, In a control method of an information processing apparatus comprising a console that monitors the operating state of a processor,
Outputting an operation mode change request for changing the operation mode according to the operation state of the processor, performed at the console;
A step of outputting an instruction completion notification when the arithmetic processing performed by the processor is being performed;
Instructing the processor to change the operation mode when the instruction completion notification is output from the processor after the operation mode change request from the console, performed in the instruction management unit;
When the instruction sequence performed by the issue control unit includes an in-order prefix instruction for performing a predetermined process and an in-order processing instruction that requires processing by the in-order prefix instruction, the in-order prefix instruction Performing a control to stop issuing the in-order processing instruction until the processing is completed, and outputting the fact to the instruction management unit as an issue standby notification;
Outputting the standby end notification to the issuance control unit when the instruction completion notification is output after the issuance standby notification is output, which is performed in the instruction management unit;
And a step of issuing the in-order processing command after receiving the standby end notification, which is performed by the issuance control unit.

  In this information processing apparatus, the instruction management unit recognizes the presence of an in-process instruction and the presence / absence of an operation mode change request in a processor that performs various arithmetic processes according to a given instruction sequence, and receives an operation mode change request from the console. The operation mode is changed in anticipation of the timing when the processor is in a hardware state where there is no instruction in progress.

  For this reason, the information processing apparatus issues an instruction based on the instruction sequence from the issuance control unit to the processor, and that the processor is performing various arithmetic processing according to the instruction based on the instruction sequence. An instruction management unit is provided for recognizing the instruction issuance notification and recognizing the completion of the processing according to the instruction sequence by the processor by the instruction completion notification from the processor.

  When the instruction management unit receives the mode change notification from the diagnostic processor, the instruction management unit further receives the instruction completion notification, thereby knowing that the processor is in a state of accepting the change of the operation mode, and operates on the processor in this state. Instruct mode change.

  In this way, it is possible to change the operation mode while the system is operating without stopping the system operation of the information processing apparatus, and there is no problem in the operation of the information processing apparatus.

  ADVANTAGE OF THE INVENTION According to this invention, the information processing apparatus which can change the operation mode of hardware while continuing system operation | movement can be obtained.

  Embodiments for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration example of the information processing apparatus according to the present embodiment.

  As shown in the figure, the information processing apparatus performs various arithmetic processes such as four arithmetic operations and logical operations in accordance with the control instruction S11 decoded from the instruction sequence S1 given in advance, and the arithmetic processing currently being processed is completed. In this case, the function processing unit 200 having the processor 100 that outputs the instruction completion notification S3, the main storage unit 340 that stores information necessary for the information processing apparatus such as the instruction sequence S1, and the operation of the main storage unit 340 are controlled. Mode control notification 345 when there is an operation mode change request S2 from the console 600, and an input / output control unit 350 that controls input / output between various peripheral devices (not shown) connected to the information processing device. Is output as a mode change notification that is one of the above, and performs initialization processing at the time of startup of the information processing device and fault processing control when a fault occurs. A diagnostic processor 390, monitors the operation state of the processor 100, configured with a console 600 which outputs the operation mode change request S2 for requesting a change of the operation mode according to the operating state of the processor 100 to the diagnostic processor 390.

  The function processing unit 200 completes the processing of the in-order prefix instruction when the instruction sequence S1 includes an in-order prefix instruction that performs predetermined processing and an in-order processing instruction that requires processing by the in-order prefix instruction. Issuance of the in-order processing instruction until it is issued, and issuance control unit 160 that outputs one of the issuance status notifications S5 indicating these states and that issues an issuance standby notification indicating that the issuance is stopped. The processor 100 that receives the instruction S11 and performs various arithmetic processes and the like, and when the operation mode change request S2 is output from the console 600, the instruction completion notification S3 is output and then the processor 100 is instructed to change the operation mode. An instruction management unit 170 and an operation mode register group 180 including an operation mode register 1800 corresponding to each operation mode. Constructed.

  This information processing apparatus has a plurality of operation modes that define the hardware operation state of the processor 100, and the optimum operation mode specified in the operation mode register group 180 by the operation mode change request S 2 from the console 600. The processor 100 and the like can perform various kinds of processing such as arithmetic processing.

  The mode state notification S4 is a notification indicating the state in the diagnostic processor 390 to the instruction management unit 170. This mode state notification S4 is a mode change notification indicating that the operation mode change request S2 is received from the console 600. , An instruction to change the operation mode of the processor 100 in response to a request from the console 600 or the like, and an operation mode change end notification indicating that this change instruction has been completed, and a mode change notification corresponding to the mode state notification S4 as necessary. Alternatively, an operation mode change end notification is output to the instruction management unit 170.

  The issuance status notification S5 is a notification indicating the status in the issuance control unit 160 to the instruction management unit 170. This notification is issued to the processor 100 and the like, an issuance waiting notification indicating that the in-order processing command issuance is stopped. It consists of a control command S11 and a command issue notification indicating that an in-order processing command has been issued, and a notification corresponding to the issue status notification S5 is output to the command management unit 170 as necessary.

  The processor 100 performs memory access control with the arithmetic processing unit 110 that performs arithmetic processing, the internal control command processing unit 120 that performs status control operation within the function processing unit 200, and the main storage unit 340, and the input / output I / O. An external control command processing unit 130 that performs / O (Input / Output) access control.

  The processor 100 is connected to an issue control unit 160, the issue control unit 160 is connected to an instruction management unit 170, the instruction management unit 170 is connected to an operation mode register group 180, and the operation mode register group 180 is The diagnosis processor 390 is connected to the console 600, the processor 100 is connected to the instruction management unit 170, the instruction management unit 170 is connected to the diagnosis processor 390, and the operation mode is connected to the diagnosis processor 390. The register group 180 is connected to the memory control unit 345, the memory control unit 345 is connected to the main storage unit 340, the main storage unit 340 is connected to the issue control unit 160, and the operation mode register group 180 is The processor 100 is connected to the input / output control unit 350 and the operation mode register group 1 It is connected to 0.

  In addition, the structure and connection which were demonstrated described the required part relevant to this invention, and description about the structure of a prior art etc. is abbreviate | omitted.

  The issuance control unit 160 is provided in the function processing unit 200. The issuance control unit 160 decodes the instruction sequence S1 output from the main storage unit 340, and executes various controls corresponding to the instruction sequence S1 and executed by the function processing unit 200 or the like. It has a function of issuing an instruction to be issued to each component such as the processor 100 as the instruction S11, and has an issue control function for controlling the issuance of the control instruction S11.

  The instruction management unit 170 manages the execution state of various control instructions S11 executed in the function processing unit 200, and sends an operation status S6 indicating the instruction execution state in the function processing unit 200 to the issuance control unit 160. Has a function to notify.

  The instruction management unit 170 receives, from the processor 100, an instruction completion notification S3 indicating that various arithmetic processes of the processor 100 according to the control instruction S11 are completed, and thereby executes the control instruction S11 being executed in the function processing unit 200. Monitor status.

  The instruction management unit 170 receives an issuance standby notification that is one of the issuance status notifications S5, and when receiving the instruction completion notification S3, the issuance control unit notifies the fact as a standby end notification that is one of the operation statuses S6. To 160.

  The operation mode register group 180 is a register that can be dynamically rewritten and changed under the control of the mode designation notification S7 from the diagnostic processor 390, and hardware in each function processing part such as the function processing unit 200 in the information processing apparatus. One arbitrary operation method is determined from among a plurality of operation modes (operation methods) that are implemented in an automatic manner.

  Therefore, the operation mode register group 180 can be rewritten by the diagnosis processor 390 by the operation mode change start instruction S9 issued from the instruction management unit 170 to the diagnosis processor 390 in response to the mode change notification, and corresponds to the operation mode. An operation mode register 1800 is provided.

  The operation mode register group 180 has a function of changing the operation mode to the processor 100, the memory control unit 345, the input / output control unit 350, and the like by a mode change instruction S8.

  The processor 100 receives the control command S11 to be executed output from the issue control unit 160, and performs processing for each of the arithmetic processing unit 110, the internal control command processing unit 120, and the external control command processing unit 130.

  The arithmetic processing unit 110 is an information processing unit represented by an arithmetic unit generally referred to as an ALU (Arithmetic and Logic Unit), and performs arithmetic operations such as four arithmetic operations such as addition / multiplication and logical operations. Has a function of performing general processing.

  In addition to the circuit that performs such operations, the arithmetic processing unit 110 stores accumulators that temporarily store the results of operations performed by the circuits, and status information such as the positive / negative and carry of the operation results. In many cases, a flag register or the like is provided.

  The internal control command processing unit 120 has a function of performing a status control operation in the function processing unit 200.

The external control command processing unit 130 has a function of performing memory access control with the main storage unit 340 and input / output I / O access control. The diagnostic processor 390 includes each component including the function processing unit 200. It has an interface with an LSI (Large Scale Integration), and has a function of controlling initialization processing at the time of hardware startup and failure processing when a failure occurs.

  The main storage unit 340 is a register that performs temporary storage and can be accessed at high speed according to a request, and has a function of specifying a position stored directly by the control instruction S11 and reading and writing.

  The memory control unit 345 has a function of performing control when reading stored contents stored in the main storage unit 340 and writing and storing them in the main storage unit 340.

  The input / output control unit 350 has a function of controlling input / output with various peripheral devices such as an input / output terminal (not shown), a display device, and a printing device connected to the information processing apparatus.

  Next, the operation of the information processing apparatus according to the present embodiment will be described in detail with reference to FIGS.

  The instruction sequence S1 stored in the main storage unit 340 and executed by the function processing unit 200 is output from the main storage unit 340 to the issue control unit 160 of the function processing unit 200 under the control of the memory control unit 345.

  The issuance control unit 160 that has received the instruction sequence S1 to be executed in the function processing unit 200 decodes each instruction of the received instruction sequence S1, and receives a control instruction S11 indicating the content of the instruction obtained as a result of the decoding. Issued to the processor 100 or the like, and simultaneously notifies the instruction management unit 170 that the control command S11 has been issued to the processor 100 or the like as an instruction issue notification.

  The arithmetic processing unit 110, the internal control command processing unit 120, and the external control command processing unit 130, which are components of the processor 100 that has received the control command S11 output from the issue control unit 160, operate based on the control command S11. Start processing according to the instructions.

  The arithmetic processing unit 110 performs various arithmetic processing such as four arithmetic operations such as addition and multiplication and logical operation in accordance with the received control command S11, and outputs the operation result.

  The internal control command processing unit 120 obtains the status in the function processing unit 200 and performs a status control operation in the function processing unit 200 according to the obtained status.

  The external control command processing unit 130 performs memory access control and I / O access control with the function processing unit 200 inside and outside.

  The arithmetic processing unit 110, the internal control command processing unit 120, and the external control command processing unit 130, which are constituent parts of the processor 100, complete the execution of each process according to the control command S11 received from the issue control unit 160.

  When the processing of the control command S11 is completed, the processor 100 notifies the command management unit 170 of the completion as a command completion notification S3.

  The instruction management unit 170 receives the instruction issuance notification notified from the issuance control unit 160 and the instruction completion notification S3 notified from the processor 100. The function processing unit responds to the correspondence between the instruction issuance notification and the instruction completion notification S3 In 200, it is monitored whether there is a control command S11 in progress.

  When it is determined whether or not there is a control command S11 in progress in the function processing unit 200, the command management unit 170 stores the control command S11 in a state register provided in the command management unit 170.

  When the issuance control unit 160 decodes an in-order processing instruction that needs to be processed after waiting for completion of the control instruction S11 that has been executed in advance, the issuance control unit 160 executes the in-order processing instruction in advance. The issuing of the subsequent control instruction S11 is stopped until the processing of the in-order pre-instruction is completed, and is issued to the instruction management unit 170 as an issuance wait notification indicating that the in-order pre-instruction is in progress and is in a state of waiting for the in-order processing instruction issuance. Notice.

  In this in-order processing instruction issuance waiting state, the processor 100 notifies the instruction management unit 170 as an instruction completion notification S3 that the processor 100 has finished processing the in-order pre-instruction and that the processor 100 is no longer in process. Then, it becomes possible to cancel the issuance wait.

  When receiving the instruction completion notification S3 from the processor 100, the instruction management unit 170 notifies the issuance control unit 160 that the waiting for subsequent instruction issuance can be canceled as a standby end notification which is one of the operation statuses S6.

  However, at this time, when there is a mode change notification that is one of the mode state notifications S4 from the diagnostic processor 390, after the processor 100 finishes the processing of the in-order pre-instruction, the operation mode register group according to the instruction from the diagnostic processor 390 After completing the change of 180, the instruction control unit 170 issues an issue control unit as a standby end notification that the instruction issue wait can be released based on the operation mode change end notification which is one of the mode state notifications S4 from the diagnostic processor 390. 160 may be notified.

  The diagnostic processor 390 controls the execution of fault processing when receiving an interrupt from each functional unit such as the processor 100, and also issues an operation mode change request S2 for requesting a change of the operation mode provided in hardware to the console 600. In response to this change request, it is transmitted to the instruction management unit 170 as a mode change notification which is one of the mode state notifications S4.

  Upon receiving the issuance waiting notification of the issuance state notification S5 and the mode change notification of the mode state notification S4, the instruction management unit 170 provides the state of the function processing unit 200 in the instruction management unit 170 according to these notifications. Store in the status register.

  A configuration example of the command management unit 170 is shown in FIG.

  As shown in the figure, the instruction management unit 170 includes a status register 171 that indicates a status of receiving the notification. This status register 171 corresponds to the reception of the command issue notification and the command completion notification S3. An E bit 172 indicating the presence / absence of S11 (see FIG. 1), an I bit 173 indicating whether or not the in-order processing instruction is waiting to be issued, and a mode change notification S4 from the diagnostic processor 390 are provided. The corresponding C bit 174 has a 3-bit status flag.

  The definitions of the logical values of the status flag E bit 172, I bit 173, and C bit 174 of the status register 171 are shown in FIG.

  As shown in the drawing, the column includes a column indicating the status flag type from the left, a logical value column for each status flag, a processor state (operation status) corresponding to the logical value, and a column indicating the presence / absence of notification.

  The E bit 172 is reset to the logical value “0” when the instruction issuance notification is received from the issuance control unit 160, and this logical value “0” is indicated, whereby the processor 100 controls the control instruction S11 (FIG. 1). (See) is in progress.

  The E bit 172 is set to a logical value “1” when the instruction completion notification S3 is received from the processor 100, and the processor 100 completes the execution of the control instruction S11 by indicating this logical value “1”. It means that there is no process in progress.

  The instruction management unit 170 monitors whether or not there is an in-process control instruction S11 by collating the instruction issuance notification from the issuance control unit 160 with the instruction completion notification S3 from the processor 100, and by this collation, the function processing unit When it is determined at 200 that there is a control command S11 in progress, the E bit 172 is reset to the logical value “0”, and when it is determined that there is no control command S11 in progress, the E bit 172 is set to the logical value “0”. It may be set to “1”.

  The I bit 173 is set to a logical value “1” when an issuance standby notification is received from the issuance control unit 160, and this logical value “1” indicates that the processor 100 is in the process of in-order pre-instruction. It represents that.

  The I bit 173 indicates that the issuance control unit 160 is in a state of waiting for issuance of an in-order processing instruction subsequent to the in-order pre-order instruction by indicating the logical value “1”. .

  The I bit 173 is reset to the logical value “0” when the instruction management unit 170 outputs a standby end notification that is one of the operation statuses S6 to the issue control unit 160, and is reset to the logical value “0”. Sometimes, there is no in-order pre-order in progress in the processor 100 or the execution of the in-order pre-order has been completed, indicating that the issuance control unit 160 is not waiting for the in-order processing instruction to be issued.

  Note that the processing of the in-order pre-instruction has been completed, but if for some reason the issuance of the subsequent in-order processing instruction is continued in the issuance control unit 160, the I bit 173 remains set to the logical value “1”. It becomes. Thereafter, when the issuance of the in-order processing instruction of the issuance control unit 160 is released, a standby end notification is output, and the I bit 173 is reset to the logical value “0”.

  When the in-order pre-instruction is in progress, since the processor 100 is executing the in-order pre-instruction, the status register 171 sets the I bit 173 to the logical value “1” as described above. In addition, the E bit 172 is also reset to the logical value “0” indicating that the in-order execution of the control instruction S11 is being executed because the in-order pre-instruction is being executed.

  Also at this time, the E bit 172 is set to the logical value “1” by the instruction completion notification S3 output from the processor 100.

  The C bit 174 is set to a logical value “1” when a mode change notification, which is one of the mode state notifications S4, is received from the diagnostic processor 390, and this logical value “1” is indicated. This indicates that the processor 390 has received the hardware operation mode change request S2 from the console 600. When the processor 390 is reset to the logical value “0”, the console 600 does not have the hardware operation mode change request S2. This indicates that the instruction management unit 170 has received the operation mode change end notification, which is one of the mode state notifications S4, after the operation mode change instruction has been completed.

  In this way, the issue control unit 160 decodes the instruction sequence S1 fetched from the main storage unit 340, and if the instruction sequence S1 recognizes that the in-order processing instruction is included in the instruction sequence S1, notifies the instruction management unit 170 of an issue standby notification. In response to this issuance standby notification, the instruction management unit 170 sets a logical value “1” in the I bit 173 of the status register 171 provided in the instruction management unit 170.

  When the diagnostic processor 390 receives the operation mode change request S2, the diagnostic processor 390 outputs a mode change notification, which is one of the mode state notifications S4, to the instruction management unit 170, and the instruction management unit 170 performs the mode change notification. When the notification is received, a logical value “1” is set in the C bit 174 of the status register 171 provided in the instruction management unit 170.

  The state of the function processing unit 200 and the presence / absence of notification can be indicated by the 3-bit status flag defined as described above.

  The instruction management unit 170 notifies the issuance control unit 160 of the set or reset state of the E bit, I bit, and C bit as the operation status S6 of instruction execution, if necessary, in addition to the standby end notification.

  Depending on the state indicated by the 3-bit status flag of the instruction management unit 170, the processor 100 has the following operation status.

  FIG. 4 shows a 3-bit status flag 171 and the operation status of the processor 100.

  As shown in the figure, in the first line, there are a C bit 174 column, an I bit 173 column, and an E bit 172 column from the left, and a column indicating the operation status of the processor 100 corresponding to the right side. is there.

  The logical value “0” of the C bit 174 in the second row in the figure indicates that there is no mode change notification that is one of the mode state notifications S4, and the logical value “0” of the I bit 173 indicates the in-order processing instruction. The logical value “0” of the E bit 172 indicates that there is no issue waiting, and that there is a control instruction S11 in progress in the processor 100, and the control instruction S11 is in progress from the column indicating the operation status of the processor 100. It can be seen that the status is being executed.

  Similarly, the logical value “0” of the C bit 174 in the third row in the figure indicates that there is no mode change notification, and the logical value “0” of the I bit 173 indicates that there is no waiting for issuing an in-order processing instruction. , The logical value “1” of the E bit 172 indicates that there is no control instruction S11 in progress in the processor 100, and it can be seen that the control instruction S11 has a no-in-progress status.

  The logical value “0” of the C bit 174 in the fourth row in the figure indicates that there is no mode change notification, the logical value “1” of the I bit 173 indicates that the in-order processing instruction is waiting to be issued, and E The logical value “0” of the bit 172 indicates that there is a control instruction S11 in progress in the processor 100, and it can be seen that this is a status of waiting for completion of the control instruction S11.

  The logical value “0” of the C bit 174 in the fifth row in the figure indicates that there is no mode change notification, the logical value “1” of the I bit 173 indicates that the in-order processing instruction is waiting to be issued, and E The logical value “1” of the bit 172 indicates that there is no control instruction S11 in progress in the processor 100, and it can be seen that this is the status of in-order processing instruction processing start.

  The logical value “1” of the C bit 174 in the sixth row in the figure indicates that there is a mode change notification, the logical value “0” of the I bit 173 indicates that there is no waiting for an in-order processing instruction, and E The logical value “0” of the bit 172 indicates that there is a control instruction S11 in progress in the processor 100, and it can be seen that this is a status of waiting for completion of the control instruction S11.

  Similarly, the logical value “1” of the C bit 174 in the seventh row in the figure indicates that there is a mode change notification, and the logical value “0” of the I bit 173 indicates that there is no waiting for an in-order processing instruction to be issued. , The logical value “1” of the E bit 172 indicates that there is no control instruction S11 in progress in the processor 100, and it can be seen that the operation mode change start status.

  The logical value “1” of the C bit 174 in the eighth row in the figure indicates that there is a mode change notification, the logical value “1” of the I bit 173 indicates that the in-order processing instruction is waiting to be issued, and E The logical value “0” of the bit 172 indicates that there is a control instruction S11 in progress in the processor 100, and it can be seen that this is a status of waiting for completion of the control instruction S11.

  The logical value “1” of the C bit 174 in the ninth line in the figure indicates that there is a mode change notification, the logical value “1” of the I bit 173 indicates that the in-order processing instruction is waiting to be issued, and E The logical value “1” of the bit 172 indicates that there is no control instruction S11 in progress in the processor 100, and it can be seen that the status is awaiting issuance of an in-order processing instruction.

  If there is no mode change notification that is one of the mode state notifications S4 in the initial state, the issue control unit 160 described above decodes each instruction according to the state indicated by the state register 171 described above, and obtains the result of decoding. When the processor 100 is processing according to the operation instruction based on these control instructions S11, the C bit is set to the logical value “0” and the I bit is set to the logical value “0”. The E bit is set to the logical value “0”.

  This state is a status during execution of the in-process control instruction S11 shown in the second line of FIG.

  Next, the issuance control unit 160 decodes the in-order processing instruction included in the instruction sequence S1 output from the main storage unit 340. After the decoding, the issuance control unit 160 waits for the completion of the control instruction S11 that is already being executed by the processor 100. The in-order processing instruction issuance waiting state.

  At this time, the issuance control unit 160 notifies the instruction management unit 170 that it is waiting to issue an in-order processing instruction to the instruction management unit 170 as an issuance waiting notification, and the instruction management unit 170 sets the I bit 173 to the logical value “1”. Set to "".

  As a result, this state is in the status of waiting for completion of the in-process control instruction shown in the fourth line of FIG.

  Next, the instruction management unit 170 turns on the E bit 172 when it is confirmed by the instruction completion notification S3 from the processor 100 that the execution of the control instruction S11 in progress in the processor 100 is completed and there is no control instruction S11 in progress. To set the logical value “1”.

  This state is the status of the in-order processing instruction start shown in the fifth line of FIG. 4 already described.

  At this time, when the C bit 174 is not lit and the logical value is “0”, the instruction management unit 170 outputs a standby end notification to the issuance control unit 160 to resume the issuance of the in-order processing instruction that has been paused. At the same time, the issuance control unit 160 is instructed, and at the same time, the I bit 173 and the E bit 172 of the status register 171 are reset to both logical values “0”.

  This state is a status during execution of the in-process control instruction S11 shown in the second line of FIG.

  Further, when receiving the operation mode change request S2 from the console 600 or the like, the diagnosis processor 390 notifies the instruction management unit 170 of a mode change notification. The instruction management unit 170 that has received the mode change notification from the diagnostic processor 390 sets the C bit 174 to the logical value “1” in response to the mode change notification from the diagnostic processor 390.

  This state is a status of waiting for completion of the in-process completion of the control instruction S11 shown in the sixth line of FIG.

  The instruction management unit 170 receives the mode change notification from the diagnostic processor 390, and when the C bit 174 is set, when the E bit 172 is set and the I bit 173 is reset, the instruction mode register group 180 is designated. The operation mode register 1809 is rewritten through the diagnostic processor 390 to instruct the processor 100 to change the operation mode.

  That is, when the instruction management unit 170 confirms that there is no control instruction S11 to be executed by receiving the instruction completion notification S3 from the processor 100, the E bit 172 is turned on (set to the logical value “1”), and the C bit 174 is set. When the logical value is set to “1”, a change start instruction S9 is notified to the diagnostic processor 390 in order to change the operation mode register group 180.

  This state is the operation mode change start status shown in the seventh line of FIG. 4 already described.

  When the diagnosis processor 390 receives the change start instruction S9 from the instruction management unit 170, the diagnosis processor 390 changes the specified operation mode register 1809 of the operation mode register group 180 in accordance with the mode specification notification S7 output from the diagnosis processor 390.

  As the operation mode register 1809 is changed, the state of the operation mode register 1809 is notified as a mode change instruction S8 to the processor 100, the memory control unit 345, the input / output control unit 350, and the like, and the processor 100, the memory control unit 345 In addition, the operation mode of the input / output control unit 350 or the like is dynamically changed.

  When the change of the operation mode register 1809 by the change start instruction S9 is completed, the diagnosis processor 390 transmits an operation mode change end notification, which is one of the mode state notifications S4, to the instruction management unit 170.

  When receiving the operation mode change end notification, which is one of the mode state notifications S4, from the diagnostic processor 390, the instruction management unit 170 resets the E bit 172, the I bit 173, and the C bit 174 to each logical value “0”. , The issue control unit 160 is notified of the start of issue of the subsequent control command S11.

  This state is a status during execution of the in-process control instruction S11 shown in the second line of FIG.

  When both the C bit 174 and the I bit 173 are lit with the logical value "1", that is, waiting for the completion of the control instruction S11 shown in the eighth line of FIG. 4 or waiting for the in-order processing instruction issuance shown in the ninth line of FIG. In the case of the status, the above-described operation mode change process is executed, and then the E bit 172, the I bit 173, and the C bit 174 are reset to the logical value “0” and decoded to the issuance control unit 160. A standby end notification instructing the start of issuing the control command S11 is output.

  This state is also the status during the in-process execution of the control instruction S11 shown in the second line of FIG.

  The operation mode register group 180 and the operation mode register 1800 as described above are provided not only in the function processing unit 200 but also in general components such as the memory control unit 345 and the input / output control unit 350. The operation mode register provided in the constituent part may be changed at the same time as the operation mode register 1800 of the function processing unit 200 is changed.

  As described above, the information processing apparatus can be used in each unit in the information processing apparatus such as a processor having a plurality of hardware operation modes without affecting the system operation while continuing the system operation of the information processing apparatus. The hardware operation mode can be dynamically changed.

As described above, the present invention has the following effects.
(1) Since this information processing apparatus can change the system operation mode by generating a static state in hardware during system operation, it can be dynamically changed at any time without stopping the system operation.
(2) Since the information processing apparatus does not depend on software and implements a change function with hardware, the operation mode can be changed with almost no performance degradation.
(3) Since this information processing apparatus is realized by extending the functions implemented by most general processors and function processing units, it can be realized with a minimum increase in hardware.
(4) The information processing apparatus can generate the timing for safely changing the hardware operation mode in hardware while executing any control instruction in the processor, and can change the hardware operation mode register group. To do. Therefore, the hardware operation mode can be dynamically changed without being aware of the operation status of the software even when the operation system or the user process is operating during the system operation of the information processing apparatus.

It is a block diagram which shows the structural example of the information processing apparatus of this embodiment. It is a block diagram which shows the structural example of the command management part of the information processing apparatus of this embodiment. It is explanatory drawing which showed the definition of the logical value of C bit, I bit, and E bit of an instruction management part. It is a figure which shows the setting state of the C bit of a command management part, I bit, and E bit, and the operation status of a processor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Processor 110 Arithmetic processor 120 Internal control command processing part 130 External control command processing part 160 Issue control part 170 Instruction management part 171 Status register 172 E bit 173 I bit 174 C bit 180 Operation mode register group 200 Function processing part 340 Main memory Unit 345 Memory control unit 350 Input / output control unit 390 Diagnostic processor 600 Console 1800 Operation mode register 1809 Specified operation mode register S1 Command sequence S2 Operation mode change request S3 Command completion notification S4 Mode status notification S5 Issuing status notification S6 Operation status S7 Mode designation notification S8 Mode change instruction S9 Change start instruction S11 Control command

Claims (7)

In an information processing apparatus having a processor that performs various arithmetic processing according to a given instruction sequence, having a plurality of operation modes that define the operation state of the processor, and having a console that monitors the operation state of the processor,
The console outputs an operation mode change request to change the operation mode according to the operation state of the processor;
The processor outputs an instruction completion notice when the arithmetic processing currently being processed is completed,
And an instruction management unit that instructs the processor to change the operation mode after the instruction completion notification is output from the processor when the operation mode change request is output from the console. apparatus. The information processing apparatus according to claim 1,
The in-order processing until the processing of the in-order pre-instruction is completed when the instruction sequence includes an in-order pre-instruction for performing predetermined processing and an in-order processing instruction requiring processing by the in-order pre-instruction. An issuance control unit for stopping the issuance of an instruction and outputting a notice to that effect to the instruction management unit;
The command management unit outputs a standby end notification to the issue control unit when the command completion notification is output after the issue standby notification is output,
The issuance control unit is an information processing apparatus that issues the in-order processing instruction when receiving the standby end notification. The information processing apparatus according to claim 1 or 2,
When the operation mode change request is output from the console, the diagnostic processor further outputs to the command management unit as a mode change notification in response to the operation mode change request,
The instruction management unit
The E bit that is set when the instruction completion notification is received from the processor, the I bit that is set when the issuance waiting notification is received from the issuance control unit, and the mode change notification are received from the diagnostic processor A status register consisting of a C bit set when
Reset the E bit when the instruction sequence is being executed by the processor;
Resetting the I bit when the instruction management unit outputs the standby end notification,
An information processing apparatus that resets the C bit when an instruction to change the operation mode to the processor is completed. The information processing apparatus according to claim 3.
The information processing apparatus, wherein the instruction management unit notifies the issue control unit of an operation status indicating an instruction execution state of the processor with respect to a set or reset state of each of the E bit, the I bit, and the C bit. The information processing apparatus according to claim 4,
According to the operation mode change start instruction issued from the instruction management unit to the diagnostic processor in response to the mode change notification, rewriting by the diagnostic processor is possible, and further includes an operation mode register corresponding to the operation mode,
When the C bit is set in response to the mode change notification, the instruction management unit sets the operation mode register to the diagnostic processor when the E bit is set and the I bit is reset. An information processing apparatus that instructs to change the operation mode by rewriting through the network. A processor that performs various types of arithmetic processing according to a given instruction sequence; an instruction management unit that defines one of a plurality of operation modes according to an output of the processor; and the operation state of the processor. In a method for controlling an information processing apparatus including a console to be monitored,
Outputting an operation mode change request for changing the operation mode according to the operation state of the processor, performed at the console;
A step of outputting an instruction completion notification when the arithmetic processing performed by the processor is being performed;
Instructing the processor to change the operation mode when the instruction completion notification is output from the processor after the operation mode change request from the console, which is performed in the instruction management unit. A method for controlling an information processing apparatus. A processor that performs various types of arithmetic processing according to a given instruction sequence; an instruction management unit that defines one of a plurality of operation modes according to an output of the processor; and the operation state of the processor. In a control method of an information processing device including a console to be monitored,
Outputting an operation mode change request for changing the operation mode according to the operation state of the processor, performed at the console;
A step of outputting an instruction completion notice when the arithmetic processing performed by the processor is being performed;
Instructing the processor to change the operation mode when the instruction completion notification is output from the processor after the operation mode change request from the console, which is performed in the instruction management unit;
When the instruction sequence performed by the issue control unit includes an in-order prefix instruction for performing a predetermined process and an in-order processing instruction that requires processing by the in-order prefix instruction, the in-order prefix instruction Performing a control to stop issuing the in-order processing instruction until the process is completed, and outputting the fact to the instruction management unit as an issue standby notification;
Outputting the standby end notification to the issuance control unit when the instruction completion notification is output after the issuance standby notification is output, which is performed in the instruction management unit;
And a step of issuing the in-order processing command after receiving the standby end notification, which is performed by the issuance control unit.

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