JP2007158319A - Semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package which can keep a stable electrical connection between the power supply terminal of each stacked semiconductor device and the power supply terminal of a wiring board with a simple internal structure, and can obtain high reliability as a product. <P>SOLUTION: Even in a package structure in which a first semiconductor device 1, a conductive layer 4, and a second semiconductor device 2 are stacked in this order on a wiring board 3, the power supply terminal of the second semiconductor device 2 bonded on the conductive layer 4 and the power supply terminal of the wiring board 3 are electrically connected to each other via the conductive layer 4, so that a gold wire 25 for electrical connection is shortened as compared with the case where the second semiconductor device 2 and the wiring board 3 are directly connected to each other. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor package in which a plurality of semiconductor elements are stacked on a wiring board and sealed with resin.

  Conventionally, semiconductor packages have been mounted on many electronic devices widely used in the market. Recently, system LSIs have been advanced, and there is a tendency to mount more functions on one semiconductor package.

  In particular, due to the progress of mobile phones and mobile devices, semiconductor packages are required to be mounted with higher density than ever before, and SIP (System In Package) for stacking and packaging semiconductor elements and the like is popular. It has been adopted.

The structure of the conventional semiconductor package as described above will be described below with reference to the drawings.
FIG. 9 is a cross-sectional view showing a configuration example of a conventional semiconductor package. This semiconductor package is a type of semiconductor package using an organic substrate as a wiring substrate. In FIG. 9, in the semiconductor package, a first semiconductor element 1 constituting an electronic circuit for processing an electrical signal is bonded to a wiring substrate 3 that electrically connects the first semiconductor element 1 by a paste or the like. Is done.

  The second semiconductor element 2 is bonded onto the first semiconductor element 1, and the power supply terminal and the signal terminal on each of the semiconductor elements 1 and 2 are joined using gold wires 15 and 25 such as wire bonding. It is electrically connected to the power supply terminal and signal terminal of the wiring board 3 by technology. A predetermined wiring pattern is formed on the wiring substrate 3 by etching a copper foil (not shown).

Thereafter, the structure is sealed with a low thermal expansion sealing resin by a transfer mold or the like.
As a package structure using a conductive layer (see, for example, Patent Document 1), there is a method in which the conductive layer and a power supply terminal on the circuit configuration surface of the semiconductor element are connected by a bump.
JP 2004-221216 A

  However, in the conventional semiconductor package as described above, the power supply terminal of the second semiconductor element 2 stacked on the first semiconductor element 1 and the power supply terminal of the wiring board 3 are electrically connected on the wiring board 3. In such a case, the length of the gold wire 25 for the connection becomes considerably long, and there is a risk that the gold wire 25 may fall down when the resin is sealed for packaging. It was.

  Further, when the number of terminals of the first semiconductor element 1 stacked on the wiring board 3 is increased, particularly when the terminals arranged on the outer periphery are in a staggered arrangement, the first semiconductor element 1 The gold wire 15 and the gold wire 25 from the second semiconductor element 2 stacked on the gold wire 15 overlap each other in the vertical direction. There was also a problem of high possibility of contact.

  The present invention solves the above-mentioned conventional problems, and in the packaging of a semiconductor element, with a simple internal structure, for the electrical connection between the power supply terminal of each stacked semiconductor element and the power supply terminal of the wiring board. Provided is a semiconductor package which can maintain a stable connection state by eliminating problems such as unnecessary contact between connection wirings and breakage of the connection wiring, and can obtain high reliability as a product.

  In order to solve the above-described problems, a semiconductor package according to claim 1 of the present invention includes a first semiconductor element and a second semiconductor element that perform electrical signal processing with terminals arranged on an outer peripheral portion of a circuit configuration surface. A semiconductor element, a wiring substrate that is electrically connected to the first semiconductor element and the second semiconductor element, and a conductive layer that can be electrically connected are stacked, and these are sealed with resin to package A semiconductor package to be formed, wherein the first semiconductor element is disposed on an upper layer of the wiring substrate, the conductive layer is disposed on an upper layer of the first semiconductor element, and the second semiconductor layer is disposed on an upper layer of the conductive layer. A semiconductor element is disposed, and the power supply terminal of the second semiconductor element and the power supply terminal of the wiring board are connected via the conductive layer.

  According to a second aspect of the present invention, there is provided a semiconductor package according to a second aspect of the present invention, wherein the first semiconductor element and the second semiconductor element that perform electrical signal processing with terminals disposed on the outer periphery of the circuit configuration surface, A semiconductor package in which a semiconductor substrate and a wiring board electrically connected to the second semiconductor element and a conductive layer capable of electrical connection are stacked and sealed with resin to form a package. The conductive layer is formed in a state in which a central portion is punched, the first semiconductor element is disposed on an upper layer of the wiring substrate, the conductive layer is disposed on an upper layer of the first semiconductor element, and the first The second semiconductor element is disposed so as to be surrounded by the conductive layer in a central portion of the conductive layer, which is an upper layer of one semiconductor element, and a power supply terminal of the second semiconductor element and a power supply terminal of the wiring board Are connected via the conductive layer. The features.

  According to a third aspect of the present invention, there is provided a semiconductor package according to the second aspect, wherein the power supply terminal is provided in the punched region of the conductive layer on the circuit configuration surface of the first semiconductor element. The power supply terminal of the wiring board is connected via the conductive layer.

  A semiconductor package according to claim 4 of the present invention is the semiconductor package according to claim 2 or claim 3, wherein the conductive layer is divided into a plurality of regions in the upper layer of the first semiconductor element. It is characterized by having arranged by.

  Moreover, the semiconductor package of Claim 5 of this invention is a semiconductor package in any one of Claims 1-4, Comprising: The said electroconductive layer is said non-conductive adhesive and said 1st It is characterized by being bonded to a semiconductor element.

  A semiconductor package according to a sixth aspect of the present invention is the semiconductor package according to any one of the first to fifth aspects, wherein the wiring substrate is formed of an organic substrate.

  A semiconductor package according to a seventh aspect of the present invention is the semiconductor package according to any one of the first to fifth aspects, wherein the wiring board has a lead frame structure.

  A semiconductor package according to an eighth aspect of the present invention is the semiconductor package according to any one of the first to fifth aspects, wherein the wiring substrate is a ceramic substrate.

  As described above, according to the present invention, when the power supply terminal of the second semiconductor element disposed in the upper layer than the first semiconductor element on the wiring board and the power supply terminal of the wiring board are electrically connected, By connecting via a conductive layer arranged on the semiconductor element, the length of the wiring for electrical connection is shortened compared to the case of directly connecting the second semiconductor element and the wiring board, and these are made of resin. When sealing with, between the first semiconductor element and the second semiconductor element, the wiring from the first semiconductor element and the power supply terminal of the wiring board electrically connected to each of the first semiconductor element and the second semiconductor element Contact with the wiring can be prevented.

  Therefore, in the packaging of semiconductor elements, unnecessary contact between connection wirings and breakage of connection wiring with respect to the electrical connection between the power supply terminals of the stacked semiconductor elements and the power supply terminals of the wiring board with a simple internal structure. Thus, it is possible to maintain a stable connection state by eliminating problems such as the above, and to obtain high reliability as a product.

Hereinafter, a semiconductor package showing an embodiment of the present invention will be specifically described with reference to the drawings.
FIG. 1 is a structural perspective view showing one structural example of the semiconductor package of the present embodiment, and FIG. 2 is a cross-sectional view of the semiconductor package. Here, components corresponding to the components described in FIG. 9 showing the conventional example and having substantially the same function are denoted by the same reference numerals. The following embodiments are examples embodying the present invention, and do not limit the technical scope of the present invention.

  1 and 2, a semiconductor package includes a first semiconductor element 1 and a second semiconductor element 2 that have terminals arranged on an outer peripheral portion of a circuit configuration surface and perform electrical signal processing, and these semiconductor elements. The first semiconductor element 1 is arranged on the wiring board 3, which is composed of the wiring board 3 that is electrically connected to each other by the gold wires 15, 25, and 45 and the conductive layer 4 that can be electrically connected. The conductive layer 4 is disposed on the first semiconductor element 1, and the second semiconductor element 2 is bonded to the upper layer of the conductive layer 4. The power supply terminal of the second semiconductor element 2 and the power supply terminal of the wiring substrate 3 Are connected by gold wires 25 and 45 through the conductive layer 4.

Hereinafter, an example of a configuration in which an organic substrate is used as the wiring substrate 3 will be described in order with respect to the method for manufacturing the semiconductor package of the present embodiment.
The first semiconductor element 1 is bonded to a predetermined position provided on the wiring board 3 using a paste material or the like in advance, and then a non-conductive adhesive is used on the first semiconductor element 1. The conductive layer 4 is adhered. Thereafter, the second semiconductor element 2 is bonded onto the conductive layer 4.

  Thus, after the bonding of the semiconductor elements 1 and 2 and the conductive layer 4 on the wiring board 3 is completed, the gap between the semiconductor elements 1 and 2 and the wiring board 3 is, for example, gold wires 15, 25, 45 Are electrically connected by wire bonding. At the time of this electrical connection, the power supply terminal of the second semiconductor element 2 and the power supply terminal of the wiring board 3 are connected by the gold wires 25 and 45 through the conductive layer 4 disposed on the first semiconductor element 1. Is done.

  In the present embodiment, an organic substrate is employed as the wiring board 3, and the wiring board 3 on which the first semiconductor element 1 is mounted is arranged in a matrix in a frame having a predetermined size. The wiring board 3 is formed with a pattern (not shown) by etching a copper foil or the like, and the surface of the joint portion on the pattern is gold-plated so that electrical connection is possible. Yes. In addition, the surface of the wiring board 3 is protected by a solder resist except for the joints.

  After the electrical connection between the respective semiconductor elements 1 and 2 and the wiring board 3 by the gold wires 15, 25, 45 was completed, sealing was performed by transfer molding using a low thermal expansion sealing resin. Finally, a plurality of semiconductor packages are completed by cutting into individual pieces.

  Through such a manufacturing process, the lengths of the gold wires 25 and 45 connecting the power supply terminal of the second semiconductor element 2 and the power supply terminal of the wiring board 3 are set to the second semiconductor element 2 as in the prior art. Compared with the case where the wiring board 3 is directly connected to the wiring board 3, the semiconductor package can be made shorter and a highly reliable semiconductor package can be provided.

  The above description of the process is for the case where the second semiconductor element 2 to be mounted is bonded onto the conductive layer 4, but the second semiconductor element as in the other embodiments shown in FIGS. There is no problem even if 2 is mounted on the first semiconductor element 1. That is, the conductive layer 4 is formed in a state in which the central region is punched out, is disposed so as to surround the second semiconductor element 2, and the second semiconductor element 2 is disposed in the first semiconductor element 1. The power terminal of the second semiconductor element 2 and the power terminal of the wiring board 3 may be connected to each other by the gold wires 25 and 45 through the conductive layer 4. By adopting this configuration, the thickness of the semiconductor package can be suppressed as compared with the case of FIG.

  Further, as in the configuration example of the embodiment shown in FIG. 5, the central portion of the conductive layer 4 is formed by punching in the same manner as in FIG. 3, and the first semiconductor element 1 is electrically conductive on the circuit configuration surface. A power supply terminal provided in the punched region of the layer 4 and the power supply terminal of the wiring board 3 may be connected by the gold wires 45 and 46 through the conductive layer 4. By adopting this configuration, it is possible to easily prevent a power supply voltage drop phenomenon, that is, an IR drop, in the first semiconductor element 1.

  In another embodiment shown in FIG. 6, first, the first semiconductor element 1 is bonded onto the wiring substrate 3, and then the conductive layer 4 is divided into a plurality of regions on the first semiconductor element 1. The arrangement is as follows. Thereby, even if there are a plurality of types of power to be supplied to the second semiconductor element 2, the effect of the present embodiment can be similarly expected.

The embodiment shown in FIG. 7 is a cross-sectional view of a semiconductor package when a lead frame is adopted as the wiring board 3.
First, the first semiconductor element 1 is bonded in advance to a predetermined position provided on the wiring board 3 constituting the lead frame together with the external connection lead terminal RT1 by using a paste material or the like. A conductive layer 4 is bonded onto the element 1 using a non-conductive adhesive. Thereafter, the second semiconductor element 2 is bonded onto the conductive layer 4.

  Thus, after the bonding of the semiconductor elements 1 and 2 and the conductive layer 4 on the wiring board 3 is completed, the gap between the semiconductor elements 1 and 2 and the wiring board 3 is, for example, gold wires 15, 25, 45 Are electrically connected by wire bonding. At the time of this electrical connection, the power supply terminal of the second semiconductor element 2 and the power supply terminal of the wiring board 3 are connected by the gold wires 25 and 45 through the conductive layer 4 disposed on the first semiconductor element 1. Is done. A pattern is formed on the lead frame by etching or the like (not shown), and a predetermined plating is applied to the surface of the joint portion on the pattern so that electrical connection is possible.

  After the electrical connection between the respective semiconductor elements 1 and 2 and the wiring board 3 by the gold wires 15, 25, 45 was completed, sealing was performed by transfer molding using a low thermal expansion sealing resin. Finally, a plurality of semiconductor packages are completed by cutting into individual pieces.

  Thus, even in a semiconductor package having a configuration using a lead frame as the wiring board 3, the lengths of the gold wires 25 and 45 that connect the power supply terminal of the second semiconductor element 2 and the power supply terminal of the wiring board 3 are set. Compared to the case where the second semiconductor element 2 is directly connected to the wiring substrate 3 as in the prior art, the length can be made shorter and the same effect can be obtained.

The embodiment shown in FIG. 8 is a cross-sectional view of a semiconductor package when a ceramic substrate is adopted as the wiring board 3.
First, in the first semiconductor element 1, gold bumps 16 are formed on the main surface on which the semiconductor element is mounted. Next, an insulating sheet-like thermosetting resin (thermosetting resin sheet) J1 is attached to the main surface of the wiring board 3 so that the first semiconductor element 1 can be bonded. A pattern for connecting to the gold bumps 16 on the first semiconductor element 1 is formed on the wiring substrate 3 (not shown), and the surface of the joint portion on the pattern is gold plated, Connection is possible.

  Next, the gold bumps 16 on the first semiconductor element 1 and the pattern on the wiring substrate 3 are aligned and pressed and connected while being heated. After the connection, the conductive layer 4 is bonded to the back surface of the first semiconductor element 1 using a non-conductive adhesive, and then the second semiconductor element 2 is bonded onto the conductive layer 4.

  Thus, after the connection of the first semiconductor element 1 on the wiring substrate 3 and the adhesion of the second semiconductor element 2 and the conductive layer 4 are completed, the connection between the second semiconductor element 2 and the wiring substrate 3 is completed. Are electrically connected by wire bonding with gold wires 25 and 45, for example. At the time of this electrical connection, the power terminals of the second semiconductor element 2 and the wiring board 3 are connected to the gold wires 25 and 45 via the conductive layer 4 disposed on the back surface of the first semiconductor element 1. Connected by

  After the electrical connection between each of the semiconductor elements 1 and 2 and the wiring board 3 was completed, a low thermal expansion sealing resin was used and sealed by transfer molding. Finally, a plurality of semiconductor packages are completed by cutting into individual pieces.

  Thus, even in a semiconductor package having a configuration using a ceramic substrate as the wiring substrate 3, the lengths of the gold wires 25 and 45 that connect the power supply terminal of the second semiconductor element 2 and the power supply terminal of the wiring substrate 3 are set. Compared to the case where the second semiconductor element 2 is directly connected to the wiring substrate 3 as in the prior art, the length can be made shorter and the same effect can be obtained.

As described above, the present invention can be implemented regardless of the form of the semiconductor package.
Although the above description has been described with respect to the embodiments of the first semiconductor element 1 and the second semiconductor element 2, there is no problem even if it is applied to a semiconductor package composed of three or more semiconductor elements.

  The semiconductor package of the present invention has a simple structure, can obtain high reliability with respect to the connection between the power supply terminals of the stacked semiconductor elements and the power supply terminals of the wiring board, and can be wired to the stacked semiconductor elements. Can be stably performed, and is useful for a semiconductor package or the like used as a mounting part of a mobile phone or a mobile device with a structure in which semiconductor elements are stacked.

Structural perspective view which shows the 1st structural example of the semiconductor package of embodiment of this invention Sectional drawing which shows the 1st structural example of the semiconductor package of the embodiment Structural perspective view showing a second configuration example of the semiconductor package of the same embodiment Sectional drawing which shows the 2nd structural example of the semiconductor package of the embodiment Structural perspective view showing a third configuration example of the semiconductor package of the same embodiment Structural perspective view showing a fourth configuration example of the semiconductor package of the same embodiment Sectional drawing which shows the 5th structural example of the semiconductor package of the embodiment Sectional drawing which shows the 6th structural example of the semiconductor package of the embodiment Sectional drawing which shows the structural example of the conventional semiconductor package

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st semiconductor element 2 2nd semiconductor element 3 Wiring board 4, 4a, 4b Conductive layer 15, 25, 45, 46 Gold wire (for electrical connection) 16 Gold bump (for electrical connection) J1 Thermosetting Resin (thermosetting resin sheet)
RT1 Lead terminal

Claims (8)

A first semiconductor element and a second semiconductor element that perform electrical signal processing with terminals arranged on the outer periphery of the circuit configuration surface;
A wiring board electrically connected to the first semiconductor element and the second semiconductor element;
Laminating a conductive layer that can be electrically connected,
A semiconductor package in which these are sealed with a resin and packaged,
Placing the first semiconductor element on the upper layer of the wiring board;
Placing the conductive layer on top of the first semiconductor element;
Disposing the second semiconductor element on the conductive layer;
A semiconductor package, wherein a power supply terminal of the second semiconductor element and a power supply terminal of the wiring board are connected via the conductive layer. A first semiconductor element and a second semiconductor element that perform electrical signal processing with terminals arranged on the outer periphery of the circuit configuration surface;
A wiring board electrically connected to the first semiconductor element and the second semiconductor element;
Laminating a conductive layer that can be electrically connected,
A semiconductor package in which these are sealed with a resin and packaged,
The conductive layer is formed in a state in which a central portion is punched,
Placing the first semiconductor element on the upper layer of the wiring board;
Placing the conductive layer on top of the first semiconductor element;
The second semiconductor element is disposed so as to be surrounded by the conductive layer at the center of the conductive layer, which is an upper layer of the first semiconductor element.
A semiconductor package, wherein a power supply terminal of the second semiconductor element and a power supply terminal of the wiring board are connected via the conductive layer. A semiconductor package according to claim 2, wherein
A semiconductor package comprising: a power supply terminal provided in a punching region of the conductive layer on a circuit configuration surface of the first semiconductor element; and a power supply terminal of the wiring board connected via the conductive layer. A semiconductor package according to claim 2 or claim 3, wherein
The semiconductor package according to claim 1, wherein the conductive layer is arranged in a state of being divided into a plurality of regions above the first semiconductor element. A semiconductor package according to any one of claims 1 to 4,
The semiconductor package, wherein the conductive layer is bonded to the first semiconductor element with a non-conductive adhesive. A semiconductor package according to any one of claims 1 to 5,
The semiconductor package, wherein the wiring board is formed of an organic substrate. A semiconductor package according to any one of claims 1 to 5,
A semiconductor package, wherein the wiring board has a lead frame structure. A semiconductor package according to any one of claims 1 to 5,
The semiconductor package, wherein the wiring substrate is a ceramic substrate.

Images