JP2007158130A - Group iii nitride-based compound semiconductor optical element and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve yiled and light extracting efficiency in separating a wafer into individual light-emitting elements. <P>SOLUTION: From a wafer 1000w (2. A), a sapphire substrate used for epitaxial growth is removed by a laser lift-off method. The wafer has a front surface where a conductive multilayer film fm, group III nitride-based compound semiconductor layers 11, 12, and an n electrode 130 are formed on an n-type silicon substrate 200; and a rear surface where a conductive multilayer film 230 is formed. A cut surface fd having a taper is formed from the semiconductor layers 11, 12, and the semiconductor layers 11, 12 are separated for each individual element (2. B). A cut surface bd is formed from the rear surface side at the depth of 1/3 of the thickness of the n-type silicon substrate 200 (2. C). Subsequently, the cutting surfaces fd and bd of the front and rear surfaces of the wafer 1000w are seamed by a known breaking process to acquire individual light-emitting elements 1000 (2. D). The cut surface fd may be made into a tapered shape of the same angle (2. E) or a tapered shape of a changing angle (2. F). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a group III nitride compound semiconductor optical device and a method for manufacturing the same. In this specification, the term “semiconductor optical element” refers to a light-emitting element, a light-receiving element, a conversion element from one to the other of light energy and electric energy, and other semiconductor elements having an arbitrary optical function.

  As a light emitting element that emits green, blue or ultraviolet light, it has been a long time since a group III nitride compound semiconductor light emitting element appeared, but it is still mainstream to epitaxially grow the light emitting element on a dissimilar and insulating substrate such as a sapphire substrate. It is. Even when different types of conductive substrates are used, so-called dislocations during epitaxial growth cannot be sufficiently reduced, and cracks in the group III nitride compound semiconductor layer due to differences in thermal expansion coefficients after returning to room temperature after epitaxial growth. It is still a problem that generation | occurrence | production of this cannot fully be suppressed.

By the way, a substrate for epitaxial growth and a support substrate when used as an element are different, that is, a technique for transferring a group III nitride compound semiconductor layer or a group III nitride compound semiconductor element to another substrate after epitaxial growth. (Patent Documents 1 to 4, Non-Patent Document 1).
Patent 3418150 Special table 2001-501778 Special table 2005-522873 USP 6071795 Kelly et al., “Optical process for liftoff of group III-nitride films”, Physica Status Solidi (a) vol. 159, 1997, R3-R4

  As a method for applying the above technique to a group III nitride compound semiconductor optical device, the present inventors used a support substrate as a conductive substrate, and applied a highly reflective metal to the electrode structure on the p-layer side in contact with the support substrate. It is under consideration to form the electrode on the opposite side, that is, the exposed n layer side in a window frame shape. Thereby, for example, as a group III nitride compound semiconductor light emitting device, it is considered that light extraction can be efficiently performed from a region (window) in which the window frame-shaped electrode on the n layer side is not formed.

   As a method for separating a wafer composed of a conductive support substrate and a semiconductor layer having a plurality of semiconductor elements into individual elements, for example, from the side where the semiconductor layer is not formed (back surface) to the conductive support substrate. A means of performing a half cut with a dicing blade and then braking can be considered. However, since the multilayer metal film is formed when the semiconductor layer is transferred from the epitaxial growth substrate to the conductive substrate by the above method, the crack is not directly connected to the semiconductor layer from the half-cut on the back surface, and the semiconductor layer is desired. It was found that it was difficult to cut at the position. In addition, full cutting with a dicing blade from the back or front surface is also possible because the hardness of each layer of the conductive support substrate, the epitaxial growth layer, and the multilayer metal film formed between them is different. could not. These mean a decrease in yield at the time of element isolation.

  Accordingly, an object of the present invention is to improve the yield in separating a wafer on which a group III nitride compound semiconductor optical device is formed into individual devices. Furthermore, it is to improve the light extraction efficiency or light extraction efficiency of the individual elements formed thereby.

  The invention according to claim 1 is a method of manufacturing a group III nitride compound semiconductor optical device that is separated into individual devices by a dicing blade, wherein the group III nitride compound semiconductor optical device is formed on a first substrate. Forming an electrode on the uppermost layer of the group III nitride compound semiconductor optical device; forming an electrode directly with a conductive second substrate or via a conductive film or a conductive multilayer film; A step of bonding the first substrate on which the group III nitride compound semiconductor device is formed, a step of removing the first substrate, and a newly revealed layer of the group III nitride compound semiconductor device And forming a group III nitride compound semiconductor layer for each element by a dicing blade from the side of the conductive second substrate on which the group III nitride compound semiconductor optical element is formed. Of isolated elements A first dicing step of dicing the surrounding portion so that at least the entire circumference of the outer periphery in the vicinity of the light emitting region or the light receiving region is tapered, and the group III nitride compound semi-light guide of the conductive second substrate And a second dicing step of dicing from the side opposite to the side on which the element is formed. Here, the “light emitting region or light receiving region” means that the light emitting region includes all of the pn junction interface, single or multiple quantum well structure and other light emitting layers, and the same applies to the light receiving region.

  The invention according to claim 2 is a group III nitride compound semiconductor optical device, wherein the conductive substrate is joined to the conductive substrate directly or via a conductive film or a conductive multilayer film. Group III nitride compound semiconductor optical device in which at least one electrode, a first conductive type layer joined to the first electrode, and a second conductive type layer different from the conductive type are stacked And a second electrode formed on the surface side opposite to the first electrode of the group III nitride compound semiconductor optical device layer, and the device outer peripheral portion, and a group III nitride It has a taper portion formed over the entire circumference of the light emitting region or the light receiving region formed between the two conductive layers of the physical compound semiconductor optical element layer.

  Since the entire circumference of the light emitting region or the light receiving region in the vicinity of the light emitting region, which is an area sandwiched between the p layer and the n layer on the side surface around the element, which is exposed when half cutting with a dicing blade is performed, is, for example, In the light-emitting element, light that has repeatedly reflected within the group III nitride compound semiconductor layer and reaches the tapered side surface is extracted from the tapered side surface to the outside. This is because, for example, in a flat rectangular parallelepiped, there is an optical path that exceeds the critical angle on both surfaces due to reflection, and finally in the group III nitride compound semiconductor layer without light being extracted outside. If it has a tapered portion formed over the entire circumference of the outer periphery near the light emitting region or the light receiving region, such an optical path is cut at the tapered portion, and light is emitted to the outside. by. Further, if dicing is performed also from the back surface where the semiconductor layer is not formed, at least the semiconductor layer is separated, so that the yield in the separation process into individual elements is improved. The present invention is particularly effective for a manufacturing method in which dicing is performed after the epitaxial growth substrate is formed and then transferred to another supporting substrate (claim 1).

  In addition, the element having such a configuration can improve the light extraction efficiency and improve the yield at the time of chip formation.

  The dicing blade used in the present invention has, for example, a tip that is at least tapered in the vicinity of the light emitting region or the light receiving region when the thickness of the group III nitride compound semiconductor layer formed on the target wafer is cut. As long as it is formed. That is, an extremely wide range of dicing blades can be used unless a completely vertical cutting surface is formed. The taper to be formed in the group III nitride compound semiconductor layer may have a normal line of 10 to 80 degrees, preferably 20 to 70 degrees, with respect to the thickness direction of the epitaxial layer on any surface. More preferably, it is 30 to 60 degrees.

  Dicing from the group III nitride compound semiconductor layer side requires at least a depth to reach the light emitting region or the light receiving region of the group III nitride compound semiconductor layer, and preferably the group III nitride compound semiconductor layer. The depth is to be separated for each element to be obtained. In the case of being placed on the conductive substrate through the multilayer metal film, the depth of cutting the multilayer metal film, or the depth of cutting the conductive substrate may be used. If the depth is such that the group nitride compound semiconductor layer is separated for each element to be obtained, the object of the present invention can be achieved.

  On the other hand, dicing from the side where the group III nitride compound semiconductor layer is not formed on the substrate is preferably performed with a depth sufficient to cleave the substrate in a subsequent braking step. The “width” of dicing can be set as desired by the design in which elements are arranged on the wafer.

  The present invention can be applied to any group III nitride compound semiconductor optical device, and in particular to a light emitting device having a light extraction region and a light receiving device having a light extraction region. In an element having a support substrate, an electrode such as a window frame is preferably formed directly or via a translucent electrode on the group III nitride compound semiconductor layer on the side not in contact with the substrate. Since positive and negative electrodes are located above and below the light emitting region, it is desirable to use a conductive substrate as the support substrate.

  For example, when the thin film portion of GaN is melted and decomposed by laser irradiation to be separated from the epitaxial growth substrate, a laser with a wavelength shorter than 365 nm is suitable, a YAG laser with a wavelength of 365 nm, 266 nm, a XeCl laser with a wavelength of 308 nm, a wavelength of 155 nm An ArF laser and KrF having a wavelength of 248 nm are preferably used. For example, if the chips are arranged on the wafer every 500 μm, 4 × 4 2 mm square laser irradiations or 6 × 6 3 mm square laser irradiations are used. Then, it is preferable that the boundary between “laser irradiated” and “unirradiated” does not cross each chip.

  The group III nitride compound semiconductor multilayer structure is desirably formed by epitaxial growth. However, the buffer layer formed prior to the epitaxial growth may be formed by, for example, sputtering or other methods without depending on the epitaxial growth. The details of the epitaxial growth method, the epitaxial growth substrate, the structure of each layer, the structure of the functional layer such as the light emitting layer, the other structure method, and the handling method after dividing the element may not be described at all in the following embodiments. Use of any known configuration at the time of filing, or a combination of a plurality of technical configurations to form a desired optical element means that the present invention can be included.

  Group III nitride compounds, in a narrow sense, include quaternary semiconductors including arbitrary and binary AlGaInN compositions, and donor or acceptor impurities for imparting conductivity to them. In general, however, semiconductors using other groups III and V in addition or in part, or semiconductors added with any element to give other functions are excluded. It is not a thing.

  An arbitrary conductive material can be used for the electrode directly bonded to the group III nitride compound layer and the single-layer or multi-layer electrode connected to the electrode. As the highly reflective metal, iridium (Ir), platinum (Pt), rhodium (Rh), silver (Ag), and aluminum (Al) are suitable for direct bonding to the group III nitride compound layer. A light-transmitting electrode can also be formed, and indium tin oxide, indium titanium oxide, or other oxide electrodes can be used. Solder can be suitably used to join the epitaxially grown wafer and the support substrate, and a multilayer metal film may be formed on the joining side surface of the support substrate or epitaxially grown wafer as needed depending on the solder component. In addition, when a dielectric layer is formed between two layers, for example, an oxide layer and a metal layer so as not to be in direct contact with each other, an arbitrary dielectric material is used, and a hole is provided in the dielectric layer so as to be electrically connected. For example, there is a method of filling the connecting member.

  The present invention is characterized by the electrode configuration, and as described repeatedly, any other known configuration and combination of known techniques can be used for other configurations.

  FIG. A to FIG. K is a process diagram (cross-sectional view) showing a method for manufacturing a group III nitride compound semiconductor light emitting device 1000 according to a specific example of the present invention. In addition, FIG. K shows a diagram substantially corresponding to a one-chip group III nitride compound semiconductor light-emitting device 1000. FIG. A to FIG. J also shows a drawing corresponding to a cross-sectional view of one chip. However, FIG. A to FIG. J is an enlarged representation of a “part” of a single wafer, etc. FIG. K also means an enlarged cross-sectional view of a “part” of one wafer or the like that is in a state before dicing into chips.

First, a sapphire substrate 100 is prepared, and a group III nitride compound semiconductor layer is formed by normal epitaxial growth (FIG. 1.A). FIG. In A, a group III nitride compound semiconductor layer stacked as an n-type layer 11, a p-type layer 12, and a light emitting region L is shown in a simplified manner. FIG. A to FIG. In K, the n-type layer 11 and the p-type layer 12 are described as two layers that are in contact with each other in the light emitting region L indicated by a broken line, but these are not described in detail of the laminated structure. Actually, even if the sapphire substrate 100 includes, for example, a buffer layer, a high concentration n ⁺ layer made of GaN doped with silicon, a low concentration n layer made of GaN, and an n-AlGaN cladding layer, FIG. A to FIG. In K, the n-type layer 11 is represented. Similarly, even if a p-AlGaN cladding layer doped with magnesium, a low-concentration p layer made of GaN, and a high-concentration p ⁺ layer made of GaN are formed, FIG. A to FIG. In K, the p-type layer 12 is represented. The light emitting region L is represented by a broken line representing both the junction surface in the case of a pn junction and a light emitting layer having a multiple quantum well structure (usually, the well layer is an undoped layer). It does not mean the “interface between the mold layer 11 and the p-type layer 12”. However, the “plane of the light emitting region” is a plane existing in the vicinity of the broken line indicated by the light emitting region L. Note that the p-type layer 12 is “a layer containing a p-type impurity but not reduced in resistance” before the “heat treatment under nitrogen (N ₂ ) atmosphere” described below, and the “nitrogen ( After the “N ₂ ) heat treatment under atmosphere”, it is a p-type layer with a low resistance in the usual sense.

Next, a translucent electrode 121-t made of indium tin oxide (ITO) having a thickness of 300 nm is formed on the entire surface of the p-type layer 12 by electron beam evaporation. Thereafter, heat treatment is performed at 700 ° C. for 5 minutes in an N ₂ atmosphere to reduce the resistance of the p-type layer 12 and to reduce the contact resistance between the p-type layer 12 and the ITO electrode 121-t. Next, a dielectric layer 150 made of silicon nitride (SiN _x ) having a thickness of 100 nm is formed on the entire surface of the ITO electrode 121-t (FIG. 1.B).

Next, a hole H is formed in the dielectric layer 150 made of SiN _x by dry etching by photolithography using a resist film (not shown). As will be described later, the shape and position of the hole H, that is, the shape and position of the connecting portion 121-c made of nickel (Ni) are related to the shape and position of the n-electrode 130 made of a multilayer metal film to be formed later. In FIG. 5, the orthogonal projections of the two projected on the “plane of the light emitting region L” are not overlapped. In the present example, the hole H was formed in a stripe shape having a width of about 20 μm and an interval of the hole H of 80 to 100 μm with respect to the square group III nitride compound semiconductor light emitting device 1000 having a side of 400 to 500 μm. Thereafter, the resist film is removed (FIG. 1.C).

Next, in order to form the connection part 121-c made of nickel (Ni) in the hole H, a resist film (not shown) is formed. In this resist film, a hole larger than the hole is formed above the hole H of the dielectric layer 150 made of SiN _x . Thus, nickel (Ni) is formed by resistance heating vapor deposition in the hole H of the dielectric layer 150 made of SiN _x and the hole of the resist film formed thereon. At this time, nickel (Ni) was deposited until the hole H of the dielectric layer 150 made of SiN _x was filled, and a 20 nm thick hook-like portion was formed on the dielectric layer 150. In this way, the resist film was removed, and a connection portion 121-c made of nickel (Ni) filling the hole H of the dielectric layer 150 made of SiN _x was formed (FIG. 1.D).

Next, the highly reflective metal layer 121-r made of aluminum (Al) having a thickness of 300 nm is formed on the dielectric layer 150 made of SiN _x having the connection part 121-c made of nickel (Ni) in the hole H. Is formed by vapor deposition (FIG. 1.E). Thus, the group III nitride compound semiconductor layer is formed by the translucent electrode 121-t made of ITO, the connection part 121-c made of nickel (Ni), and the highly reflective metal layer 121-r made of aluminum (Al). A multiple p-electrode is formed that has high adhesion to the surface and does not absorb light and highly reflects light. Note that the role of the dielectric layer 150 made of SiN _x having the connection part 121-c made of nickel (Ni) in the hole H is that aluminum (Al) and ITO are not in direct contact with each other, thereby oxidizing the aluminum (Al). It is to prevent deterioration of the electrode characteristics due to.

  Next, a multilayer metal film is formed by vapor deposition in the following order. A titanium (Ti) layer 122 having a thickness of 50 nm, a nickel (Ni) layer 123 having a thickness of 500 nm, and a gold (Au) layer 124 having a thickness of 50 nm. Thus, FIG. The layer structure is F. The functions of the titanium (Ti) layer 122, the nickel (Ni) layer 123, and the gold (Au) layer 124 are as follows. In providing the gold tin solder (Au-20Sn) 51 of 20% tin, a gold (Au) layer 124 is formed as an alloying layer with the gold tin solder (Au-20Sn) 51, and aluminum (Al) of tin (Sn). The nickel (Ni) layer 123 is used as a layer for preventing diffusion to the highly reflective metal layer 121-r made of, and the adhesion between the nickel (Ni) layer 123 and the highly reflective metal layer 121-r made of aluminum (Al) In order to improve the above, a titanium (Ti) layer 122 is provided.

  Next, a gold tin solder (Au-20Sn) 51 of 20% tin is formed on the gold (Au) layer 124 to a thickness of 1500 nm (1.G).

Next, an n-type silicon substrate 200 is prepared, and a conductive multilayer film is formed on both surfaces by vapor deposition or the like in the following order. The front side layers are denoted by reference numerals 221 to 224, and the back side layers are denoted by reference numerals 231 to 244. Titanium nitride (TiN) layers 221 and 231 having a thickness of 30 nm, titanium (Ti) layers 222 and 232 having a thickness of 50 nm, nickel (Ni) layers 223 and 233 having a thickness of 500 nm, and gold (Au) layer 224 having a thickness of 50 nm And 234. The titanium nitride (TiN) layers 221 and 231 are selected from the viewpoint of low contact resistance with the n-type silicon substrate 200. The titanium (Ti) layers 222 and 232, nickel (Ni) layers 223 and 233, gold The functions of the (Au) layers 224 and 234 are exactly the same as the functions of the titanium (Ti) layer 122, the nickel (Ni) layer 123, and the gold (Au) layer 124 described above. On the gold (Au) layer 224 that is the uppermost layer of the conductive multilayer film on the surface side formed on the n-type silicon substrate 200, a 20% tin gold tin solder (Au-20Sn) 52 is formed to a thickness of 1500 nm, FIG. A group III nitride compound semiconductor light emitting device wafer in which a gold tin solder (Au-20Sn) 51 of 20% tin of G is formed to a thickness of 1500 nm is bonded to the surfaces on which the gold tin solder (Au-20Sn) is formed ( Figure 1.H). Thus, the two wafers are united by hot pressing at 300 ° C. and 30 kg weight / cm ² (2.94 MPa). Hereinafter, gold tin solder (Au-20Sn) is shown as an integrated layer 50 (FIG. 1.I).

The integrated wafer is irradiated with a 248 nm KrF high-power pulse laser from the sapphire substrate 100 side. The irradiation conditions are 0.7 J / cm ² or more, a pulse width of 25 ns (nanoseconds), an irradiation area of 2 mm square or 3 mm square, and for each irradiation, the outer periphery of the laser irradiation area should not cross “one chip”. good. By this laser irradiation, the interface 11f of the n-type layer 11 (GaN layer) closest to the sapphire substrate 100 is melted into a thin film and decomposed into gallium (Ga) droplets and nitrogen (N ₂ ). After that, the sapphire substrate 100 is removed from the integrated wafer by lift-off (FIG. 1.J). Thereafter, the exposed surface of the n-type layer 11 is washed with diluted hydrochloric acid to remove gallium (Ga) droplets adhering to the surface.

  Next, a resist film (not shown) is formed, and an n-electrode 130 made of a multilayer metal film is formed by vapor deposition in the following order in the hole of the resist film. As will be described later, the hole portion of the resist film was formed in a “window frame shape” so that the shape of the connection portion 121-c made of nickel (Ni) and the orthogonal projection do not overlap each other. Next, on the n-type layer 11 (hole portion of the resist film), a vanadium (V) layer having a thickness of 15 nm, an aluminum (Al) layer having a thickness of 150 nm, a titanium (Ti) layer having a thickness of 30 nm, and a thickness. A 500 nm nickel (Ni) layer and a 500 nm thick gold (Au) layer. Thereafter, the resist is lifted off and removed, whereby the n-electrode 130 made of the multilayer metal film in the hole of the resist film remains, and the metal film in the other region is removed together with the resist. Thus, the n-type silicon substrate 200 having the conductive multilayer film formed on both sides is used as a support substrate, the p-side transparent electrode 121-t made of ITO, the connection part 121-c made of nickel (Ni), aluminum (Al And a highly reflective metal layer 121-r, and is electrically connected to the n-type silicon substrate 200 with a gold-tin solder (Au-20Sn) 50 via a multilayer metal film. A compound semiconductor light emitting device 1000 was formed (FIG. 1.K). The group III nitride compound semiconductor light emitting device 1000 is a light emitting device in which a region where the n-electrode 130 made of a multilayer metal film formed in a “window frame shape” is not formed is a light extraction region.

  Next, dicing which is the main part of the present invention will be described with reference to FIG. FIG. A to FIG. FIG. 2D is a cross-sectional view showing a separation process from the wafer obtained as described above into individual elements, and FIG. E and FIG. F is an enlarged view centering around the outer periphery of the light emitting region L of the outer periphery of the obtained group III nitride compound semiconductor light emitting device 1000. FIG.

  FIG. A to FIG. In F, for simplicity, a titanium nitride (TiN) layer 231, a titanium (Ti) layer 232, a nickel (Ni) layer 233, and a gold (Au) layer 234 are formed on the back surface 200B of the n-type silicon substrate 200. The conductive multilayer film made of simply 230, a titanium nitride (TiN) layer 221 formed between the surface 200F of the n-type silicon substrate 200 and the group III nitride compound semiconductor p-type layer 12, titanium (Ti ) Layer 222, nickel (Ni) layer 223, gold (Au) layer 224, gold tin solder (Au-20Sn) layer 50, gold (Au) layer 124, nickel (Ni) layer 123, titanium (Ti) layer 122, The conductive multilayer film including the aluminum (Al) layer 121-r, the connection part 121-c made of nickel (Ni), and the translucent electrode 121-t made of ITO is simply indicated by fm. In addition, FIG. A to FIG. In D, the group III nitride compound semiconductor layer is shown as one layer, and the code is shown as “11, 12”. Further, for simplification, the number of n electrodes is shown in FIG. 2 so as to be two per one element.

  First, a wafer 1000w from which the sapphire substrate 100 is removed by the laser lift-off method is shown in FIG. Shown in A. This is illustrated in FIG. This is a state before separation of the group III nitride compound semiconductor light emitting device 1000 indicated by K. A dicing blade is operated from the group III nitride compound semiconductor layers 11 and 12 side to form a cutting surface fd, and the group III nitride compound semiconductor layers 11 and 12 are separated into individual elements. At this time, the cutting surface fd was not perpendicular to the surface of the n-type silicon substrate 200, but had a taper (FIG. 2.B).

  Next, a dicing blade was operated from the back side of the conductive multilayer film 230 side to form a cutting surface bd. The cutting surface bd was set to a depth until the thickness 1/3 of the n-type silicon substrate 200 was cut (FIG. 2.C). Next, each group III nitride compound semiconductor light emitting device 1000 can be obtained by a known braking process so that the cut surfaces fd and bd on the front and back sides of the wafer 1000w are connected (FIG. 2.D).

  An enlarged view of an example of the state of the group III nitride compound semiconductor light emitting device 1000 near the cutting surface fd is shown in FIG. E and FIG. Shown in F. The cutting surface fd is shown in FIG. As shown in FIG. 2E, the entire group III nitride compound semiconductor layers 11 and 12 may be tapered at the same angle (45 degrees in FIG. 2.E). Like F, it is good also as a taper shape (an elliptic cylinder surface or other curved column surface shape) from which the angle changes from the p-type layer 12 of the group III nitride compound semiconductor layer to the n-type layer 11.

  FIG. 2 shows an example in which the cutting surface fd is formed over the entire device outer peripheral portion of the group III nitride compound semiconductor layers 11 and 12, but the present invention is tapered at least in the vicinity of the light emitting region or the light receiving region. As long as the is formed. Further, even if the cutting surface fd reaches the group III nitride compound semiconductor layers 11 and 12 and the conductive multilayer film fm and further reaches the surface of the underlying n-type silicon substrate 200, n-type silicon is further provided. A part of the substrate 200 may be cut.

[About the planar shape of the hole H of the dielectric layer 150 filled with the n electrode 130 and the connection part 121-c]
It is desirable that the orthogonal projections of the n-electrode 130 and the planar shape of the hole H of the dielectric layer 150 filled with the connection portion 121-c, that is, the plane of the light emitting region L do not overlap, and the orthogonal projection is It is preferable not to be less than a certain distance at any position. In this case, the “certain distance” is preferably set to a distance of about the total film thickness of the n-type layer 11 and the p-type layer 12, or a multiple of the distance. For example, if the total film thickness of the n-type layer 11 and the p-type layer 12 is 5 μm, the two orthogonal projections are preferably separated by 5 μm or more at any position, more preferably 10 μm or more, More preferably, the distance is 20 μm or more.

  In the above embodiment, the n-electrode 130 may not be formed directly on the n-type layer 11, but a window frame-shaped n-electrode may be further formed after forming a translucent electrode, for example.

  The p-electrode side is not composed of the translucent electrode 121-t made of ITO, the connection part 121-c made of nickel (Ni), and the highly reflective metal layer 121-r made of aluminum (Al), and is made of high A single-layer electrode made of a reflective metal, for example, a single-layer electrode made of rhodium (Rh) may be used.

FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. A to FIG. D is a cross-sectional view showing an element isolation step, FIG. E and FIG. F is an enlarged view of the vicinity of the light emitting region L in the outer periphery of the element.

Explanation of symbols

1000: Group III nitride compound semiconductor light emitting device 100: Sapphire substrate (epitaxial growth substrate)
11: n-type group III nitride compound semiconductor layer 12: p-type group III nitride compound semiconductor layer L: Light emitting region 121-t: Translucent electrode made of ITO 121-c: Connection portion 121- made of Ni r: highly reflective metal layer made of Al 200: silicon substrate (support substrate)
221, 231: TiN layer 122, 222, 232: Ti layer 123, 223, 233: Ni layer 124, 224, 234: Au layer 130: n-electrode made of multilayer metal film 50, 51, 52: Au-20Sn solder layer 150: Dielectric layer made of SiN _x H: Hole of dielectric layer

Claims (2)

A method of manufacturing a group III nitride compound semiconductor optical device that is separated into individual devices by a dicing blade,
Forming a group III nitride compound semiconductor optical device on a first substrate;
Forming an electrode on the uppermost layer of the group III nitride compound semiconductor optical device;
A conductive second substrate is bonded directly to the first substrate on which the group III nitride compound semiconductor element is formed from the side on which the electrode is formed through a conductive film or a conductive multilayer film. Combining the steps,
Removing the first substrate;
Forming an electrode on the newly revealed layer of the group III nitride compound semiconductor device;
A group III nitride compound semiconductor layer is separated for each element by a dicing blade from the side of the conductive second substrate on which the group III nitride compound semiconductor optical element is formed. A first dicing step of dicing so that at least the entire circumference of the outer periphery in the vicinity of the light emitting region or the light receiving region is tapered with respect to the surrounding portion;
A group III nitride having a second dicing step of dicing from the side of the conductive second substrate opposite to the side on which the group III nitride compound semi-light guide element is formed For manufacturing a semiconductor compound semiconductor device. Group III nitride compound semiconductor optical device,
A conductive substrate;
A first electrode bonded directly or via a conductive film or a conductive multilayer film to the conductive substrate;
A group III nitride compound semiconductor optical element layer in which at least a first conductivity type layer bonded to the first electrode and a second conductivity type layer different from the first conductivity type are stacked;
A second electrode formed on the surface side opposite to the first electrode of the group III nitride compound semiconductor optical element layer;
A taper formed on the outer periphery of the element and formed over the entire outer periphery of the light emitting region or the light receiving region formed between the two conductive layers of the group III nitride compound semiconductor optical device layer. A group III nitride compound semiconductor optical device having a portion.

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