JP2007157974A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
JP2007157974A
JP2007157974A JP2005350390A JP2005350390A JP2007157974A JP 2007157974 A JP2007157974 A JP 2007157974A JP 2005350390 A JP2005350390 A JP 2005350390A JP 2005350390 A JP2005350390 A JP 2005350390A JP 2007157974 A JP2007157974 A JP 2007157974A
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resin sealing
sealing body
semiconductor
semiconductor device
sealed
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Inventor
Haruhiko Yamaguchi
山口　　晴彦
Kimihiko Kono
公彦 河野
Makoto Kishimoto
真 岸本
Kenichi Miki
研一 三木
Akihiko Yoshida
昭彦 吉田
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Toshiba Corp
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Toshiba Corp
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Priority to JP2005350390A priority Critical patent/JP2007157974A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device which suppresses the occurrence of surface chip and the semiconductor device formed by this method. <P>SOLUTION: The semiconductor manufacturing method comprises a process wherein a plurality of semiconductor elements (semiconductor chips) are arranged in a mold with a distance between each other so as to have the shape of lattice to effect resin sealing, and to form an integrated resin sealing body 10', in which the plurality of semiconductor chips are sealed; a process for effecting half cuts 16 in transversal and lateral directions on a main surface provided with an indication mark 13 of the integrated resin sealing body 10', in which the plurality of semiconductor chips are sealed; and a process for effecting full cut by a dicing blade 15 from a rear surface provided with external electrodes 11, 12 along the half cut groove type lines 16, to divide and form a plurality of pieces of resin sealing bodies 10' individually, in which the single body of semiconductor chip is sealed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、裏面に外部電極などの電極が形成された樹脂封止体を有する半導体装置の製造方法及び半導体装置に関するものである。   The present invention relates to a method for manufacturing a semiconductor device having a resin sealing body in which an electrode such as an external electrode is formed on the back surface, and the semiconductor device.

小信号の半導体装置は、小型化が進んでおり、例えば、各辺のサイズが１ｍｍ以下の半導体装置まで製造されている。このサイズでは個別には封止せず、複数の半導体素子（半導体チップ）を金型内で行列に配列して一括して樹脂封止し、この一括樹脂封止体を半導体チップ毎にダイシングして樹脂封止体に包まれた１つの半導体チップに分割することにより製造されている。このような半導体チップを包み込む樹脂封止体（パッケージ）は、形状が直方形であるためハンドリング時の衝撃などにより角部の欠けが発生し易いという問題があった。これは、樹脂の効率や封止の際の金型のずれによる寸法精度の悪化を抑えるためにこのような形成方法を採用しているためである。この様にして得られた半導体装置の外囲器は角部がすべて直角になっており、ハンドリング時に欠けを発生する可能性が高い。
従来、樹脂封止体（パッケージ）の欠け対策としてはその角部の面取りを行うことが多いが、チップサイズのパッケージ単体での面取りの実施は困難を伴うものであった。 Small signal semiconductor devices have been miniaturized. For example, semiconductor devices having a side size of 1 mm or less have been manufactured. This size is not individually sealed, but a plurality of semiconductor elements (semiconductor chips) are arranged in a matrix in the mold and collectively sealed with resin, and this batch resin sealed body is diced for each semiconductor chip. It is manufactured by dividing it into one semiconductor chip wrapped in a resin sealing body. Such a resin encapsulant (package) that wraps around a semiconductor chip has a rectangular shape, and therefore has a problem that corners are easily chipped due to an impact during handling. This is because such a forming method is employed in order to suppress deterioration of dimensional accuracy due to resin efficiency and die shift at the time of sealing. The envelope of the semiconductor device obtained in this way has all the right corners, and there is a high possibility that chipping will occur during handling.
Conventionally, as countermeasures against chipping of a resin-encapsulated body (package), corners are often chamfered, but chamfering with a chip-size package alone has been difficult.

特許文献１には外囲器の１つの面に電極を形成し、その周囲をブレードでダイシングする半導体装置において、２回のダイシング工程により樹脂封止体をダイシングして樹脂封止体に封止された半導体チップを形成することが開示されている。また、特許文献２には、電極面からダイシングしてから、その反対面からレーザダイシングすることが開示されている。
特開２００５−１３６２２６号公報 特開２００４−２４１６２６号公報 In Patent Document 1, in a semiconductor device in which an electrode is formed on one surface of an envelope and the periphery thereof is diced with a blade, the resin sealing body is diced and sealed in the resin sealing body by two dicing processes. Forming an integrated semiconductor chip is disclosed. Patent Document 2 discloses that dicing is performed from the electrode surface and then laser dicing is performed from the opposite surface.
JP 2005-136226 A JP 2004-241626 A

本発明は、表面の欠けの発生を抑制する半導体装置の製造方法及び半導体装置を提供する。   The present invention provides a method for manufacturing a semiconductor device and a semiconductor device that suppress the occurrence of chipping on the surface.

本発明の半導体装置の製造方法の一態様は、複数の半導体素子を金型内に格子状に間隔を置いて配置し、樹脂封止を行って、前記格子状に間隔をおいて配置された複数の半導体素子が封止された一括樹脂封止体を形成する工程と、前記複数の半導体素子が封止された一括樹脂封止体の主面に前記半導体素子が個別又は複数個毎に分離されるように縦方向及び横方向のハーフカットを行う工程と、前記ハーフカットのラインに沿って前記一括樹脂封止体を裏面からフルカットして、前記複数の半導体素子が樹脂封止された樹脂封止体を複数個分割形成することを特徴としている。   According to one aspect of a method for manufacturing a semiconductor device of the present invention, a plurality of semiconductor elements are arranged in a grid at intervals in a lattice shape, resin-sealed, and arranged in the lattice shape at intervals. A step of forming a collective resin sealing body in which a plurality of semiconductor elements are sealed; and the semiconductor elements are separated individually or in plurals on a main surface of the collective resin sealing body in which the plurality of semiconductor elements are sealed And performing the half cut in the vertical direction and the horizontal direction, the full resin sealing body is fully cut from the back surface along the half cut line, and the plurality of semiconductor elements are resin-sealed. The resin sealing body is divided into a plurality of parts.

本発明によれば、表面の欠けの発生を抑制する半導体装置の製造方法を得ることができる。   According to the present invention, it is possible to obtain a method for manufacturing a semiconductor device that suppresses occurrence of chipping on the surface.

以下、実施例を参照して発明の実施の形態を説明する。   Hereinafter, embodiments of the invention will be described with reference to examples.

図１乃至図６を参照して実施例１を説明する。図１は、半導体装置の斜視図、図２乃至図４は、半導体装置の製造工程を説明する斜視図及びこの斜視図のＡ−Ａ′線に沿う部分の断面図、図５は、パッケージ保持テープに収容された樹脂封止体が収容されたパッケージ保持テープの断面図、図６は、樹脂封止体で封止された半導体装置の断面図である。この実施例では半導体装置として、例えば、ダイオードを用いて説明する。   The first embodiment will be described with reference to FIGS. FIG. 1 is a perspective view of a semiconductor device, FIGS. 2 to 4 are perspective views for explaining a manufacturing process of the semiconductor device, and a sectional view of a portion along the AA ′ line of this perspective view. FIG. FIG. 6 is a cross-sectional view of a package holding tape containing a resin sealing body housed in a tape, and FIG. 6 is a cross-sectional view of a semiconductor device sealed with the resin sealing body. In this embodiment, a semiconductor device will be described using a diode, for example.

図１は、半導体チップが封止されているパッケージ（樹脂封止体）の電極が形成されている面（裏面）を上にした斜視図（図１（ａ））及び極性などのマークが表示された面（主面）を上にした斜視図（図１（ｂ））から構成されている。半導体チップを封止した樹脂封止体１０の裏面には外部接続端子となるアノード、カソードなどの電極１１、１２が形成されている。樹脂封止体１０主面には極性を示すマーク１３が形成されている。極性マーク１３が形成されている主面の四周には、所定のＲを持った面取り部１４が施されている。極性マーク１３は、印刷もしくはレーザなどによる焼付けにより樹脂封止体１０に形成される。また、この実施例では、面取り部１４は、ダイシング時のハーフカットにより形成される。半導体装置のパッケージサイズ（樹脂封止体のサイズ）は、各辺が１ｍｍ以下である。   FIG. 1 shows a perspective view (FIG. 1A) with the surface (back surface) on which an electrode of a package (resin sealing body) in which a semiconductor chip is sealed is formed, and marks such as polarity. It is comprised from the perspective view (FIG.1 (b)) which made the surface (main surface) made up. Electrodes 11 and 12 such as an anode and a cathode serving as external connection terminals are formed on the back surface of the resin sealing body 10 in which the semiconductor chip is sealed. A mark 13 indicating polarity is formed on the main surface of the resin sealing body 10. A chamfered portion 14 having a predetermined R is provided on the four circumferences of the main surface on which the polar mark 13 is formed. The polar mark 13 is formed on the resin sealing body 10 by printing or baking with a laser or the like. In this embodiment, the chamfered portion 14 is formed by half-cutting during dicing. The package size of the semiconductor device (the size of the resin sealing body) is 1 mm or less on each side.

次に、図２乃至図５を参照してこの半導体装置の製造方法を説明する。複数の半導体チップが金型（図示しない）内において行列状に配置される。そして、複数の半導体チップは、エポキシ樹脂などからなる一括樹脂封止体１０′に封止される。一括樹脂封止体１０′の主面には極性マーク１３が一括樹脂封止体１０′内の半導体チップに対応して行列状に配列形成されている（図２（ａ））。一括樹脂封止体１０′の裏面には各半導体チップの電極１１、１２が露出している（図では電極１１が表示されている）（図２（ｂ））。   Next, a method for manufacturing this semiconductor device will be described with reference to FIGS. A plurality of semiconductor chips are arranged in a matrix in a mold (not shown). The plurality of semiconductor chips are sealed in a collective resin sealing body 10 'made of epoxy resin or the like. Polarity marks 13 are arranged in a matrix on the main surface of the collective resin sealing body 10 'so as to correspond to the semiconductor chips in the collective resin sealing body 10' (FIG. 2A). The electrodes 11 and 12 of each semiconductor chip are exposed on the back surface of the collective resin sealing body 10 '(the electrodes 11 are displayed in the figure) (FIG. 2B).

次に、この一括樹脂封止体１０′をダイシングして、図１に示すように、１つの半導体チップが封止された樹脂封止体１０に分割形成され、これがこの実施例の半導体装置を構成する。一括樹脂封止体１０′から複数の樹脂封止体１０に分割するには、まず、一括樹脂封止体１０′の極性マーク１３が形成された主面に各半導体チップ毎に区画されるようにブレードによりハーフカットする。これにより主面にはハーフカット溝あるいはハーフカットライン１６が形成される。この実施例では、ハーフカットライン幅２ｄは、次のフルカットに用いられるブレード（ダイシングブレード）１５（図４参照）の幅より大きくすることが必要である（図３）。なぜなら、ハーフカットライン１６は、樹脂封止体１０の面取り部１４となるからである。図６に示すように、ｄは、面取り幅に相当し、例えば、この実施例では０．１ｍｍである。このハーフカットにより一括樹脂封止体１０′から切り出される樹脂封止体１０は、主面の極性マーク面は、面取り部１４を有するようになり、電極１１、１２が形成された裏面より面積が狭い。   Next, the collective resin sealing body 10 ′ is diced and divided into resin sealing bodies 10 in which one semiconductor chip is sealed, as shown in FIG. Constitute. In order to divide the collective resin sealing body 10 ′ into a plurality of resin sealing bodies 10, first, each semiconductor chip is partitioned on the main surface on which the polarity mark 13 of the collective resin sealing body 10 ′ is formed. Half cut with a blade. Thereby, a half cut groove or a half cut line 16 is formed on the main surface. In this embodiment, the half cut line width 2d needs to be larger than the width of the blade (dicing blade) 15 (see FIG. 4) used for the next full cut (FIG. 3). This is because the half cut line 16 becomes the chamfered portion 14 of the resin sealing body 10. As shown in FIG. 6, d corresponds to the chamfer width, and is 0.1 mm in this embodiment, for example. The resin sealing body 10 cut out from the collective resin sealing body 10 ′ by this half cut has a chamfered portion 14 on the main surface of the polar mark surface, and the area is smaller than the back surface on which the electrodes 11 and 12 are formed. narrow.

次に、一括樹脂封止体１０′を裏面側からダイシング（フルカット）する。ハーフカットを行ったブレードのブレード幅２ｄより幅の狭いダイシングブレード１５を用い、ハーフカットライン１６の溝中心にダイシングブレード１５がくるようにして一括樹脂封止体１０′をダイシングする。この様にして、ハーフカットによって極性マーク面（主面）が面取りされ、半導体チップが封止された樹脂封止体１０（図１参照）が複数個切り出される。この樹脂封止体１０は、ハーフカット用ダイシングブレード先端のＲに沿った面取りを容易に行うことができた。一括樹脂封止体１０′から切り出された樹脂封止体１０は、約１０００ｐ作製され、各個片毎にパッケージ保持テープ１７の凹部１７′に収納されて保護テープ１８により密閉される（図５）。   Next, the collective resin sealing body 10 ′ is diced (full cut) from the back side. The dicing blade 15 having a width smaller than the blade width 2d of the half-cut blade is used, and the collective resin sealing body 10 ′ is diced so that the dicing blade 15 comes to the center of the groove of the half-cut line 16. In this way, the polarity mark surface (main surface) is chamfered by half cutting, and a plurality of resin sealing bodies 10 (see FIG. 1) in which the semiconductor chip is sealed are cut out. This resin sealing body 10 could easily be chamfered along R at the tip of the half-cut dicing blade. The resin sealing body 10 cut out from the collective resin sealing body 10 'is manufactured to about 1000p, and is stored in the recess 17' of the package holding tape 17 for each individual piece and sealed with the protective tape 18 (FIG. 5). .

図６は、図１に示す半導体チップが樹脂封止体（パッケージ）に封止された構成の半導体装置の内部を説明する断面図である。半導体チップを封止した樹脂封止体１０の裏面に電極１１、１２、主面に極性を示すマーク１３、主面の四周に所定のＲを持った面取り部１４が形成されていることは図１の説明時に説明したとおりである。ダイオードが形成された半導体チップ１は、裏面に形成されたアノードもしくはカソードと主面に形成されたカソードもしくはアノードを有している。半導体チップ１は、外部電極１１の上に接合されており、外部電極１２は間隔をおいて外部電極１１に対向して配置されている。外部電極１２は、ボンディングワイヤ２により半導体チップ１主面のカソードもしくはアノードに電気的に接続されている。レーザなどにより焼付け形成された極性マーク１３は、外部電極１１の上方に対向するように配置されている。ハーフカットにより形成された面取り部１４は、例えば、幅ｄが０．１μｍ程度である。半導体チップ１、外部電極１１、１２、ボンディングワイヤ２は、エポキシ樹脂などを材料とする樹脂封止体１０に封止され、外部電極１１、１２の下面は、樹脂封止体１０から露出している。   FIG. 6 is a cross-sectional view illustrating the inside of a semiconductor device having a configuration in which the semiconductor chip shown in FIG. 1 is sealed in a resin sealing body (package). The electrodes 11 and 12 are formed on the back surface of the resin sealing body 10 encapsulating the semiconductor chip, the polar mark 13 is formed on the main surface, and the chamfered portion 14 having a predetermined R is formed around the main surface. This is as described in the description of 1. The semiconductor chip 1 on which the diode is formed has an anode or cathode formed on the back surface and a cathode or anode formed on the main surface. The semiconductor chip 1 is bonded onto the external electrode 11, and the external electrode 12 is disposed to face the external electrode 11 with a gap. The external electrode 12 is electrically connected to the cathode or anode of the main surface of the semiconductor chip 1 by the bonding wire 2. The polarity mark 13 baked and formed by a laser or the like is disposed so as to face the upper side of the external electrode 11. The chamfered portion 14 formed by the half cut has a width d of about 0.1 μm, for example. The semiconductor chip 1, the external electrodes 11 and 12, and the bonding wire 2 are sealed with a resin sealing body 10 made of an epoxy resin or the like, and the lower surfaces of the external electrodes 11 and 12 are exposed from the resin sealing body 10. Yes.

このように樹脂封止体のテープ詰めを行なった後に樹脂封止体の角部の欠けを確認したが目立つ欠けは発見できなかった。また外形認識による実装装置で認識精度を確認したが特に問題はなかった。即ち、外形認識を行なった場合の認識の精度を落すことなく欠けを低減させることができた。パッケージ（樹脂封止体）の実装を行なう際の認識方法として電極で認識を行なう場合と外形で認識を行なう場合があり、後者の場合面取りにより認識される寸法が異なると実装不良を起こす可能性があるが、面取りを極性マーク面のみとすることにより電極面から外形を見た場合の形状を変えないようにできる。
面取りを極性マーク面のみとしない従来の方法で作製したパッケージを有する半導体装置を約１０００ｐ作製し、樹脂封止体（パッケージ）の角部の欠けを確認したところ欠けが７ｐ発見された。またこの従来例では外形認識による実装装置の認識精度を確認したが特に問題はなかった。 Thus, after the resin sealing body was taped, chipping of the corner of the resin sealing body was confirmed, but no conspicuous chipping was found. Although the recognition accuracy was confirmed with a mounting device based on outline recognition, there was no particular problem. That is, the chipping can be reduced without degrading the recognition accuracy when the outer shape recognition is performed. When recognizing a package (resin-sealed body), there are cases where the electrode is recognized and the outline is recognized. In the latter case, mounting defects may occur if the dimensions recognized by chamfering are different. However, it is possible to keep the shape when the outer shape is viewed from the electrode surface by changing the chamfering only to the polar mark surface.
About 1000 p of a semiconductor device having a package manufactured by a conventional method in which chamfering is not limited to the polar mark surface was manufactured, and when a chipped corner of a resin sealing body (package) was confirmed, 7 p of chipping was found. In this conventional example, the recognition accuracy of the mounting apparatus was confirmed by outline recognition, but there was no particular problem.

次に、図７乃至図９を参照して実施例２を説明する。図７は、樹脂封止体により被覆された半導体装置の断面図、図８及び図９は、半導体装置の製造工程を説明する斜視図及びこの斜視図のＡ−Ａ′線に沿う部分の断面図である。この実施例ではハーフカットの方法に特徴がある。
図７は、半導体装置の樹脂封止体２０の断面を示しており、主面に極性マーク２３が形成され、裏面に外部接続端子となる電極２２が形成されている。極性マーク２３が形成されている主面は、所定のＲを持って面取り２４されている。極性マーク２３は、印刷もしくはレーザによる焼付けにより樹脂封止体２０に形成される。また、面取り２４は、ダイシング時のハーフカットにより形成される。半導体装置のパッケージサイズ（樹脂封止体のサイズ）は、各辺が１ｍｍ以下である。 Next, Embodiment 2 will be described with reference to FIGS. 7 is a cross-sectional view of a semiconductor device covered with a resin sealing body, FIGS. 8 and 9 are perspective views for explaining a manufacturing process of the semiconductor device, and a cross-section of a portion along the line AA ′ in this perspective view. FIG. This embodiment is characterized by a half-cut method.
FIG. 7 shows a cross section of the resin sealing body 20 of the semiconductor device, in which a polarity mark 23 is formed on the main surface, and an electrode 22 serving as an external connection terminal is formed on the back surface. The main surface on which the polar mark 23 is formed is chamfered 24 with a predetermined R. The polarity mark 23 is formed on the resin sealing body 20 by printing or laser baking. Further, the chamfer 24 is formed by a half cut at the time of dicing. The package size of the semiconductor device (the size of the resin sealing body) is 1 mm or less on each side.

次に、図８及び図９を参照してこの半導体装置の製造方法を説明する。複数の半導体チップが金型（図示しない）内において行列状に配置される。そして、複数の半導体チップは、エポキシ樹脂などからなる一括樹脂封止体２０′に封止される。一括樹脂封止体２０′の主面には極性マーク２３が一括樹脂封止体２０′内の半導体チップに対応して行列状に配列形成されている（図８（ａ））。一括樹脂封止体２０′の裏面には各半導体チップの電極２２が露出している（図２（ｂ））。   Next, a method for manufacturing this semiconductor device will be described with reference to FIGS. A plurality of semiconductor chips are arranged in a matrix in a mold (not shown). The plurality of semiconductor chips are sealed in a collective resin sealing body 20 ′ made of epoxy resin or the like. Polarity marks 23 are arrayed in a matrix on the main surface of the collective resin sealing body 20 'corresponding to the semiconductor chips in the collective resin sealing body 20' (FIG. 8A). The electrode 22 of each semiconductor chip is exposed on the back surface of the collective resin sealing body 20 ′ (FIG. 2B).

次に、この一括樹脂封止体２０′をダイシングして、図７に示す、１つの半導体チップが封止された樹脂封止体２０に分割形成され、これがこの実施例の半導体装置を構成する。まず、一括樹脂封止体２０′の極性マーク２３が形成された主面に各半導体チップ毎に区画されるようにレーザ装置２７によりハーフカットする。主面には溝状のハーフカットライン２６が形成される。この実施例においてもハーフカットライン幅２Ｄは、次のフルカットに用いられるブレード（ダイシングブレード）２５の幅より大きくなっている（図９）。図７に示すように、Ｄは、例えば、８０μｍ程度である。このハーフカットにより一括樹脂封止体２０′から切り出される樹脂封止体２０は、主面の極性マーク面には、面取り部２４が形成され、電極２２が形成された裏面より面積が狭い。   Next, the collective resin sealing body 20 'is diced and divided into resin sealing bodies 20 in which one semiconductor chip is sealed as shown in FIG. 7, which constitutes the semiconductor device of this embodiment. . First, a half cut is performed by the laser device 27 so that each semiconductor chip is partitioned on the main surface on which the polarity mark 23 of the collective resin sealing body 20 ′ is formed. A groove-shaped half cut line 26 is formed on the main surface. Also in this embodiment, the half cut line width 2D is larger than the width of the blade (dicing blade) 25 used for the next full cut (FIG. 9). As shown in FIG. 7, D is, for example, about 80 μm. The resin sealing body 20 cut out from the collective resin sealing body 20 ′ by this half cut has a chamfered portion 24 formed on the polar mark surface of the main surface, and has a smaller area than the back surface on which the electrode 22 is formed.

次に、一括樹脂封止体２０′をダイシング（フルカット）する。ハーフカットを行ったレーザ装置２７のハーフカットライン幅２Ｄより幅の狭いブレード２５を用い、ハーフカットライン２６に沿って一括樹脂封止体２０′をダイシングする。この様にして、ハーフカットによって極性マーク面（主面）が面取りされ、半導体チップが封止された樹脂封止体２０が複数個切り出される。この樹脂封止体は、ハーフカット用レーザビームのＲに沿った面取りを容易に行うことができた。一括樹脂封止体２０′から切り出された樹脂封止体２０は、約１０００ｐ作製され、各個片毎に保持テープの凹部に収納されて保護テープにより密閉される（図５参照）。   Next, the collective resin sealing body 20 ′ is diced (full cut). The collective resin sealing body 20 ′ is diced along the half-cut line 26 using a blade 25 having a width smaller than the half-cut line width 2D of the laser device 27 that has been half-cut. In this way, the polarity mark surface (main surface) is chamfered by half cutting, and a plurality of resin sealing bodies 20 in which the semiconductor chip is sealed are cut out. This resin-sealed body could easily be chamfered along the half-cut laser beam R. The resin sealing body 20 cut out from the collective resin sealing body 20 ′ is manufactured to about 1000 p, and is stored in the concave portion of the holding tape for each individual piece and sealed with a protective tape (see FIG. 5).

図７は、半導体チップが樹脂封止体（パッケージ）に封止された構成の半導体装置の内部を説明する断面図である。半導体チップを封止した樹脂封止体２０の裏面に電極２１、２２、主面に極性を示すマーク２３、主面の四周に所定のＲを持った面取り部１４が形成されていることは上述の通りである。ダイオードが形成された半導体チップ２８は、裏面に形成されたアノードもしくはカソードと主面に形成されたカソードもしくはアノードを有している。半導体チップ２８は、外部電極２１の上に接合されており、外部電極２２は間隔をおいて外部電極２１に対向して配置されている。外部電極２２は、ボンディングワイヤ２９により半導体チップ２８主面のカソードもしくはアノードに電気的に接続されている。レーザなどにより焼付け形成された極性マーク２３は、外部電極２１の上方に対向するように配置されている。半導体チップ２８、外部電極２１、２２、ボンディングワイヤ２９は、エポキシ樹脂などを材料とする樹脂封止体２０に封止され、外部電極２１、２２の下面は、樹脂封止体２０から露出している。   FIG. 7 is a cross-sectional view illustrating the inside of a semiconductor device having a configuration in which a semiconductor chip is sealed in a resin sealing body (package). As described above, the electrodes 21 and 22 are formed on the back surface of the resin sealing body 20 encapsulating the semiconductor chip, the polarity mark 23 is formed on the main surface, and the chamfered portion 14 having a predetermined R is formed on the four circumferences of the main surface. It is as follows. The semiconductor chip 28 on which the diode is formed has an anode or cathode formed on the back surface and a cathode or anode formed on the main surface. The semiconductor chip 28 is bonded onto the external electrode 21, and the external electrode 22 is disposed to face the external electrode 21 with a gap. The external electrode 22 is electrically connected to the cathode or anode of the main surface of the semiconductor chip 28 by a bonding wire 29. The polarity mark 23 baked and formed by a laser or the like is disposed so as to face the upper side of the external electrode 21. The semiconductor chip 28, the external electrodes 21 and 22, and the bonding wires 29 are sealed in a resin sealing body 20 made of an epoxy resin or the like, and the lower surfaces of the external electrodes 21 and 22 are exposed from the resin sealing body 20. Yes.

樹脂封止体のテープ詰めを行なった後に樹脂封止体の角部の欠けを確認したが目立つ欠けは発見できなかった。また外形認識による実装装置で認識精度を確認したが特に問題はなかった。即ち、外形認識を行なった場合の認識の精度を落すことなく欠けを低減させることができた。面取りを極性マーク面のみとすることにより電極面から外形を見た場合の形状を変えないようにできる。また、ハーフカットをレーザビームにより行うことにより、面取り幅を小さくすることができる。
以上、実施例ではダイオードなどの電極が２つの半導体装置について説明したが、本発明においては、トランジスタなどの電極が３つの場合にも適用することができる。また実施例では１つの半導体装置中に１つの半導体チップが入る構造について説明したが、本発明は、１つの半導体装置の中に２つの半導体チップが入る構造や３つ以上の半導体チップが入る構造にも適用することができる。 After the resin sealing body was taped, chipping of the corners of the resin sealing body was confirmed, but no noticeable chipping was found. Although the recognition accuracy was confirmed with a mounting device based on outline recognition, there was no particular problem. That is, the chipping can be reduced without degrading the recognition accuracy when the outer shape recognition is performed. By only chamfering the polar mark surface, it is possible to prevent the shape when the outer shape is viewed from the electrode surface from being changed. Further, the chamfering width can be reduced by performing the half-cut with a laser beam.
As described above, the semiconductor device having two electrodes such as a diode has been described in the embodiments. However, the present invention can also be applied to the case where there are three electrodes such as a transistor. In the embodiment, the structure in which one semiconductor chip is inserted in one semiconductor device has been described. However, the present invention is a structure in which two semiconductor chips are inserted in one semiconductor device or a structure in which three or more semiconductor chips are inserted. It can also be applied to.

本発明の一実施例である実施例１の主面（マーク面）を下に配した状態と裏面（電極面）を下に配した半導体装置の斜視図。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a semiconductor device in which a main surface (mark surface) of Example 1 which is an embodiment of the present invention is disposed below and a back surface (electrode surface) is disposed below. 図１の半導体装置の製造工程を説明する斜視図。FIG. 3 is a perspective view illustrating a manufacturing process of the semiconductor device of FIG. 1. 図１の半導体装置の製造工程を説明する斜視図及びこの斜視図のＡ−Ａ′線に沿う部分の断面図。FIG. 2 is a perspective view for explaining a manufacturing process of the semiconductor device of FIG. 図１の半導体装置の製造工程を説明する斜視図及びこの斜視図のＡ−Ａ′線に沿う部分の断面図。FIG. 2 is a perspective view for explaining a manufacturing process of the semiconductor device of FIG. 図１の半導体チップを含む樹脂封止体が収容されたパッケージ保持テープの断面図。Sectional drawing of the package holding tape in which the resin sealing body containing the semiconductor chip of FIG. 1 was accommodated. 図１の樹脂封止体により半導体チップが封止された半導体装置の断面図。Sectional drawing of the semiconductor device by which the semiconductor chip was sealed with the resin sealing body of FIG. 本発明の一実施例である実施例２の樹脂封止体により被覆された半導体装置の断面図。Sectional drawing of the semiconductor device coat | covered with the resin sealing body of Example 2 which is one Example of this invention. 図７の半導体装置の製造工程を説明する斜視図及びこの斜視図のＡ−Ａ′線に沿う部分の断面図。FIG. 8 is a perspective view illustrating a manufacturing process of the semiconductor device of FIG. 7 and a cross-sectional view of a portion along the line AA ′ of the perspective view. 図７の半導体装置の製造工程を説明する斜視図及びこの斜視図のＡ−Ａ′線に沿う部分の断面図。FIG. 8 is a perspective view illustrating a manufacturing process of the semiconductor device of FIG. 7 and a cross-sectional view of a portion along the line AA ′ of the perspective view.

符号の説明Explanation of symbols

１、２８・・・半導体チップ
２、２９・・・ボンディングワイヤ
１０、２０・・・樹脂封止体（パッケージ）
１０′、２０′・・・一括樹脂封止体
１１、１２、２１、２２・・・電極
１３、２３・・・マーク
１４、２４・・・面取り部
１５、２５・・・ダイシングブレード
１６、２６・・・ハーフカットライン（溝）
１７・・・パッケージ保持テープ
１７′・・・パッケージ保持テープの凹部
１８・・・保護テープ
２７・・・レーザ照射装置

DESCRIPTION OF SYMBOLS 1,28 ... Semiconductor chip 2, 29 ... Bonding wire 10, 20 ... Resin sealing body (package)
10 ', 20' ... collective resin sealing body 11, 12, 21, 22 ... electrode 13, 23 ... mark 14, 24 ... chamfered portion 15, 25 ... dicing blade 16, 26 ... Half cut lines (grooves)
DESCRIPTION OF SYMBOLS 17 ... Package holding tape 17 '... Recessed part of package holding tape 18 ... Protective tape 27 ... Laser irradiation device

Claims (5)

複数の半導体素子を金型内に格子状に間隔を置いて配置し、樹脂封止を行って、前記格子状に間隔をおいて配置された複数の半導体素子が封止された一括樹脂封止体を形成する工程と、
前記複数の半導体素子が封止された一括樹脂封止体の主面に前記半導体素子が個別又は複数個毎に分離されるように縦方向及び横方向のハーフカットを行う工程と、
前記ハーフカットのラインに沿って前記一括樹脂封止体を裏面からフルカットして、前記複数の半導体素子が樹脂封止された樹脂封止体を個別に複数個分割形成することを特徴とする半導体装置の製造方法。 Collective resin sealing in which a plurality of semiconductor elements arranged at intervals in a lattice form are arranged in a mold in a mold, and resin sealing is performed, and the plurality of semiconductor elements arranged at intervals in the lattice form are sealed Forming a body;
A step of half-cutting in the vertical direction and the horizontal direction so that the semiconductor elements are separated individually or plurally on the main surface of the collective resin sealing body in which the plurality of semiconductor elements are sealed;
The collective resin sealing body is fully cut from the back surface along the half-cut line, and a plurality of resin sealing bodies in which the plurality of semiconductor elements are resin-sealed are individually divided and formed. A method for manufacturing a semiconductor device. 前記ハーフカットのライン径は、前記フルカットのライン径よりも大きいことを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the half-cut line diameter is larger than the full-cut line diameter. 前記ハーフカットされる主面には表示マークが形成され、裏面には電極が形成されていることを特徴とする請求項１又は請求項２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein display marks are formed on the main surface to be half-cut and electrodes are formed on the back surface. 前記ハーフカットにはブレードもしくはレーザを用いることを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein a blade or a laser is used for the half-cut. 半導体素子と、
前記半導体素子が封止され、上面には表示マークが形成され、下面には露出して電極が形成された樹脂封止体とを備え、
前記上面の四周は面取りされており、且つ前記上面の面積は、前記下面の面積より小さいことを特徴とする半導体装置。



A semiconductor element;
The semiconductor element is sealed, a display mark is formed on the upper surface, and a resin sealing body in which an electrode is formed exposed on the lower surface,
4. The semiconductor device according to claim 1, wherein the upper surface has four chamfers, and the area of the upper surface is smaller than that of the lower surface.



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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009170476A (en) * 2008-01-11 2009-07-30 Panasonic Corp Semiconductor device and method of manufacturing the same
JP2009275108A (en) * 2008-05-14 2009-11-26 Nitto Denko Corp Semiconductor-sealing resin composition, method for producing the same and semiconductor device using the same
US9029199B2 (en) 2012-06-22 2015-05-12 Ps4 Luxco S.A.R.L. Method for manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009170476A (en) * 2008-01-11 2009-07-30 Panasonic Corp Semiconductor device and method of manufacturing the same
JP2009275108A (en) * 2008-05-14 2009-11-26 Nitto Denko Corp Semiconductor-sealing resin composition, method for producing the same and semiconductor device using the same
US9029199B2 (en) 2012-06-22 2015-05-12 Ps4 Luxco S.A.R.L. Method for manufacturing semiconductor device

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