JP2007157322A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory device provided with a floating body transistor capacitor-less memory cell and its operating method. <P>SOLUTION: The semiconductor memory device includes a memory cell array which includes a plurality of unit memory cells, where each of the unit memory cells comprises complementary first and second floating body transistor capacitor-less memory cells. A logical value used in and read from each unit memory cell is defined by a difference in threshold voltage states of the first and second floating body transistor capacitor-less memory cells. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a floating body type capacitorless memory cell and an operation method thereof.

  Generally, a memory cell of a dynamic access memory device includes a capacitor for storing electric charge and a transistor for accessing the capacitor. The logic value of the memory cell is determined by the voltage of the capacitor. However, in order to increase the degree of integration of the semiconductor memory device, a DRAM memory cell composed of a single transistor has been proposed. Here, such a single transistor type memory cell is referred to as a “floating body transistor type capacitorless memory cell” or simply as a “transistor cell”.

  In the write mode, in the floating body transistor type capacitorless memory cell, the threshold voltage of the cell is changed by changing the channel body potential, and in the read mode, the logic state is distinguished by the magnitude of the current passing through the cell. . This will be described in more detail with reference to FIG.

  FIG. 1 is a cross-sectional view of an example of a floating body transistor type capacitorless memory cell. As shown, the floating body transistor type capacitorless memory cell of this example includes a silicon substrate 100 and a buried oxide layer 101. A floating channel body region 102 disposed between the source 103 and the drain region 104 is disposed on the buried oxide layer 101. The gate dielectric 105 and the gate electrode 106 are disposed on the floating channel body region 102 so that the insulating layer 107 (eg, SiO 2 layer) isolates the floating body transistor capacitorless memory cell from other devices on the substrate 100. Formed.

  The logic “1” and logic “0” states depend on the threshold voltage Vth of the floating body transistor capacitorless memory cell, and examples of write and read voltages applied to the floating body transistor capacitorless memory cell are shown in the table below. It is shown in 1.

  When the write data is “1”, the voltage bias conditions are set to Vgs> Vth and Vgd <Vth. This allows the transistor to operate in saturation. In this state, impact ionization occurs from the junction of the drain region 104 and the floating channel body region 102. As a result, holes are injected into the floating channel body region 102, which increases the potential of the floating channel body region 102 and decreases the threshold voltage Vth of the floating body transistor capacitorless memory cell.

  When the write data is “0”, the drain voltage Vd drops to a negative voltage in order to create a forward bias state at the junction between the floating channel body region 102 and the drain region 104. The forward bias moves the hole group included in the floating channel body region 102 to the drain region 104. This decreases the potential of the floating channel body region 102 and increases the threshold voltage Vth.

  In the read operation, the voltage bias conditions are set to Vgs> Vth and Vgd> Vth, and the transistor cell operates in the fan-shaped region. The drain current is compared with the reference cell current to determine whether the floating body transistor capacitorless memory cell is in a high (logic “0”) or low (logic “1”) voltage threshold Vth state. More specifically, when the measured drain current is less than the reference current, a logic “0” state is read, and when the measured drain current is greater than the reference current, a logic “1” state is read.

  In general, the reference cell current is generated using a reference (or dummy) transistor cell programmed to the “0” and “1” states, respectively. Further, the reference voltage generation circuit and other circuits are used to generate a reference current having a value between the drain current value of the “0” reference transistor cell and the drain current value of the “1” reference transistor cell. It is done.

  Here, the technique described in Patent Document 1 will be examined. The read operation of the floating body transistor type capacitorless memory cell tends to induce many errors. An example of such an error will be described with reference to FIGS. 2A to 2C.

  2A and 2B show drain current distributions 201 and 202 in a “0” or “1” state of a plurality of floating body transistor capacitorless cells and a current distribution 203 of a reference cell related to a plurality of read operations.

  2A shows a portion 210 where the reference cell current distribution 203 and the drain current distribution 201 in the “0” state overlap, and FIG. 2B shows a portion where the reference cell current distribution 203 and the drain current distribution 202 in the “1” state overlap. 211 is shown. In either case, a read error occurs. 2A and 2B can occur based on a number of factors such as process changes, temperature changes, and the like.

  FIG. 2C shows that the drain current distributions 201 and 202 in the “0” state and “1” state of the transistor cell overlap in another portion 212. This is manifested by the volatility of the floating body transistor capacitorless memory cell. That is, leakage from the floating channel body region causes the threshold voltage Vth of the cell transistor to fluctuate. Therefore, it is necessary to periodically refresh the floating body transistor type capacitorless memory cell in the same manner as refreshing a conventional capacitor type DRAM cell.

As described above, in addition to the tendency to read errors, a DRAM device having a memory cell without a conventional floating body transistor capacitor has a reference current generator, a reference memory cell, and other circuits for generating a reference current. Has the disadvantage of requiring This is an obstacle to increasing the degree of integration of the memory device. In addition, a longer time is required in the refresh operation for refreshing the reference memory cell.
US Pat. No. 6,567,330 US Pat. No. 6,882,008 US Pat. No. 6,781,875

  An object of the present invention is to provide a memory device having a floating body transistor type capacitorless memory cell that can reduce data read errors and solve the problems of the prior art as described above.

  Another object of the present invention is to provide a method of operating a memory device to achieve the above object.

  A semiconductor memory device according to an embodiment of the present invention includes a memory cell array including a plurality of unit memory cells, and each unit memory cell includes complementary first and second floating body transistor type capacitorless memory cells.

  According to another aspect of the present invention, a semiconductor memory device includes a memory cell array having a plurality of unit memory cells arranged in rows and columns, each unit memory cell having complementary first and second floating bodies. A transistor type capacitorless memory cell is provided. The memory device further includes a plurality of odd-numbered pairs of bit lines connected to the odd-numbered rows in each of the unit memory cells, each of the odd-numbered bit lines being a first floating body in the odd-numbered rows. A first odd-numbered bit line connected to the transistor-type capacitorless memory cell and a second odd-numbered bit line connected to the second floating body transistor-type capacitorless memory cell in each odd-numbered row. The memory device further includes a plurality of pairs of even-numbered bit lines connected to the even-numbered rows of the unit cells, respectively, wherein each even-numbered pair of bit lines includes a first floating body transistor type capacitorless capacitor line. A first even-numbered bit line connected to the memory cell and a second even-numbered bit line connected to the second floating body transistor type capacitorless memory cell in the even-numbered row. The memory device is selected from odd-numbered and even-numbered sensing circuits, a pair of odd-numbered and even-numbered sense bit lines operatively paired with odd-numbered and even-numbered circuits, respectively, and a plurality of pairs of odd-numbered bit lines. An odd bit line selector for selectively connecting the odd pair of bit lines to the odd pair of sense bit lines, and an even pair of bit lines selected from a plurality of pairs of even bit lines. An even bit line selector selectively connected to the even-numbered pair of sense bit lines is further provided.

  According to another aspect of the present invention, a semiconductor memory device includes a memory cell array including a plurality of unit cells, each of the unit memory cells being a first floating body transistor type capacitorless memory cell located in a first memory block array, And a complementary second floating body transistor type capacitorless memory cell located in the second memory block array. The memory device is located in the first memory block array and operatively coupled to the corresponding first floating body transistor type capacitorless memory cell and the second bit located in and corresponding to the plurality of first bit lines and the second memory block array. The floating body transistor type capacitorless memory cell further includes a plurality of second bit lines operatively coupled. A memory device is a sensing circuit operatively positioned between a first memory block array and a second memory block array, and selects a first bit line of a plurality of first bit lines as one of a pair of sense bit lines And a second bit line selector that selectively connects a second bit line of the plurality of second bit lines to the other one of the pair of sense bit lines. To do.

  According to another aspect of the present invention, there is provided a method for writing data to a semiconductor memory device including a floating body transistor type capacitorless memory cell. The method includes setting a threshold voltage of the first floating body transistor type capacitorless memory cell to a first threshold voltage and setting a threshold voltage of the second floating body transistor type capacitorless memory cell to a second threshold voltage. . The first and second floating body transistor type capacitorless memory cells constitute a unit memory cell, and the logical value used for each unit cell is the first and second floating body transistor type capacitorless memory cells. It is defined by the difference between the two threshold voltages.

  According to yet another aspect of the present invention, there is provided a method for reading data of a semiconductor memory device including a floating body transistor type capacitorless memory cell. The method includes determining a threshold voltage state of the first floating body transistor type capacitorless memory cell and determining a threshold voltage of the second floating body transistor type capacitorless memory cell. The first and second floating body transistor capacitorless memory cells constitute a unit memory cell, and the method further includes the first and second threshold voltage states of the first and second floating body transistor capacitorless memory cells. The method further includes determining a logical value of each unit memory cell according to the difference.

  Since the semiconductor memory device of the present invention does not have a reference memory cell array block, no separate control is required for the reference memory cell array block, and data is read by reading data without using the reference memory cell array block. An error does not occur.

  Hereinafter, a memory device having a floating body transistor type capacitorless memory cell of the present invention and an operation method of the device will be described with reference to the drawings.

FIG. 3 is a block diagram of a memory device including a floating body transistor capacitorless memory cell according to an embodiment of the present invention. A floating body transistor type capacitorless memory cell is a memory cell that includes a floating body transistor but does not include a capacitor (excluding a parasitic capacitor).
3 includes a plurality of subarray blocks SBLK <1: m>, a plurality of even and odd bit line BL selectors 21-1 <1: m>, 20-2 <1: m>, and a plurality of sense blocks. 22-1 <1: m>, 22-2 <1: m>, memory cell array block including row decoder 24, column decoder 26, bit line selection signal generator 28, control signal generator 30, and instruction decoder 32 BLK1 is provided.

  Each subarray block SBLK of each memory cell array block BLK1 includes a plurality of floating body transistor capacitorless memory cells MC. Although only a single memory cell array block BLK1 is shown in FIG. 3, the memory device includes a plurality of blocks BLK having the same configuration.

  Each memory cell array block BLK (BLK1) includes a plurality of subarray blocks SBLK <1: m>. The subarray blocks SBLK <1: m> share the same word line WL. In FIG. 3, only one word line WL1 is shown for simplicity.

  The sub-array block SBLK includes a plurality of bit lines BL <1: k> and a plurality of inverted bit lines BLB <1: k>. Bit lines BL <1: k> and inverted bit lines BLB are arranged in FIG. Each bit line BL <1: k> and the inverted bit line BLB are also referred to herein as a “pair of bit lines” BL / BLB. In the example of this embodiment, there are K pairs of bit lines BL / BLB for each subarray block SBLK.

  In the present embodiment, the “unit memory cell” includes a first floating body transistor capacitorless memory cell connected between the bit line BL and a reference potential (for example, ground), a unit potential of the inverted bit line BLB, And a second floating body transistor type capacitorless memory cell connected between the two. The unit memory cell holds a logical value indicated by a complementary threshold voltage of the first and second floating body transistor type capacitorless memory cells. That is, each unit memory cell includes complementary first and second floating body transistor type capacitorless memory cells having opposite threshold voltage states. In the example of this embodiment, the floating body transistor capacitorless memory cell is an NMOS transistor.

  Complementary first and second floating body transistor type capacitorless memory cells of each unit memory cell are connected to the same word line WL.

  The even bit line selector 20-1 <1: m> and the odd bit line selector 20-2 <1: m> are located on opposite sides of the respective subarray blocks SBLK <1: m>. Each even bit line selector 20-1 is connected to a bit line BL having k / 2 even numbers and an inverted bit line BLB having k / 2 even numbers in the corresponding sub-array block SBLK. . Similarly, each odd bit line selector 20-2 is connected to the bit line having k / 2 odd numbers and the inverted bit line BLB having k / 2 odd numbers of the corresponding sub-array block SBLK. Is done.

  Referring to FIG. 3, the sense block 22-1 <1: m> is connected to the even bit line selector 20-1 <1: m>, and the sense block 22-2 <1: m> Odd bit line selector 20-2 <1: m>. In particular, the complementary sense bit lines SBL1 <1: m> and SBL1B <1: m> correspond to the corresponding odd bit line selector 20-2 <1: m> and the corresponding sense block 22-2 <1. : M> are connected to each other. Similarly, the complementary sense bit lines SBL2 <1: m> and SBL2B <1: m> are connected to the corresponding even bit line selector 20-1 <1: m> and the corresponding sense block 22-. 1 <1: m> is arranged to be connected.

  Examples of even and odd bit line selectors 20-1, 20-2 are described in detail below.

  The instruction decoder 32 generates an active instruction ACT, a read instruction RD, and a write instruction WD in response to the instruction signal COM.

  In response to the active command ACT, the row decoder 24 decodes the first row address RA1 and activates the corresponding one in the word line WL.

  The bit line selection signal generator 28 decodes the second row address RA2 in response to the active command ACT, and activates one of the bit line signals BS <1: k / 2>. Here, as described above, the number of the pair of bit lines BL / BLB for each sub-array block SBLK is “K”. As shown in FIG. 3, the bit line selection signals BS <1: k / 2> are provided to the even and odd bit line selectors 20-1 <1: m> and 20-2 <1: m>.

  In response to the read command RD and the write command WR, the column decoder 26 decodes the column address CA and activates one or more corresponding column selection signals CSL <1: m>. As shown in FIG. 3, the column selection signal CSL <1: m> is provided to each sense block 22-1 <1: m> and each sense block 22-2 <1: m>.

  The control signal generator 30 selectively activates the sense amplification enable signal SEN and the write back signal WB in response to the active signal ACT. Specifically, the write back signal WB is activated for a predetermined time after the sense amplification enable signal SEN is activated. As shown in FIG. 3, this signal is provided to sense blocks 22-1 <1: m>, 22-2 <1-m>.

  Also, as shown in FIG. 3, there are first complementary data lines D1, D1B and second complementary data lines D2, D2B. The first complementary data lines D1 and D1B are connected to the sense block 22-2 <1: m>, and the second complementary data lines D2 and D2B are connected to the sense block 22-1 <1: m>. Is done.

  Those skilled in the art will be able to understand the configurations of the row decoder 24, the column decoder 26, the bit line selection circuit 28, the control signal generator 30, and the instruction decoder 32. Therefore, the description about the detailed circuit structural example of such a component is abbreviate | omitted.

  Examples of the even bit line selector 20-1 and the odd bit line selector 20-2 of FIG. 3 will be described below with reference to FIGS. 4A and 4B. In particular, FIG. 4A is a circuit diagram showing an example of an even bit line selector 20-1, and FIG. 4B is a circuit diagram showing an example of an odd bit line selector 20-2.

  As shown in FIG. 4A, the even bit line selector in such an example includes sense bit lines complementary to a pair of bit lines BL2 / BLB2, BL4 / BLB4,..., BLk / BLBk, each having an even number. A pair of NMOS transistors N18-2, N18-4,..., N18-k having even numbers connected between SBL2 / SBL2B are included. As already described, the complementary sense bit lines SBL2 / SBL2B are connected to the corresponding sense block 22-1. The gates of a pair of NMOS transistors N18-2, N18-4,..., N18-k having even numbers are connected to bit line selection signals BS <1: k / 2>, respectively. As described above, the bit line selection signal BS <1: k / 2> is generated by the bit line selection signal generator 28. The even bit line selector of FIG. 4A responds to the bit line selection signal BS <1: k / 2> with a pair of bit lines BL2 / BLB2, BL4 / BLB4,..., BLk / BLBk having even numbers. A pair of them are selectively connected to complementary sense bit lines SBL2 / SBL2B.

  4B includes a pair of bit lines BL1 / BLB1, BL3 / BLB3,..., BLk−1 / BLBk−1 each having an odd number and sense bit lines SBL1 / SBL1B complementary to each other. , N18-k-1 having a pair of odd-numbered NMOS transistors N18-1, N18-3,. As described above, the complementary sense bit lines SBL1 / SBL1B are connected to the corresponding sense block 22-2. The gates of a pair of NMOS transistors N18-1, N18-3,..., N18- (k-1) having odd numbers are respectively connected to the bit line selection signal BS <1 generated by the bit line selection signal generator 28. : K / 2>. The odd-numbered bit line selector of FIG. 4B responds to the bit line selection signal BS <1: k / 2> with a pair of bit lines BL1 / BLB1, BL3 / BLB3,..., BLk− having odd numbers. A pair in 1 / BLBk-1 is selectively connected to complementary sense bit lines SBL1 / SBL1B.

  FIG. 5 is a circuit diagram showing one example in the sense block 22-1 <1: m> of FIG. The sense block 22-2 <1: m> in FIG. 3 has the same configuration.

  As shown in FIG. 5, the sense block 22-1 is connected between complementary sense bits SBL2 / SBL2B (see FIG. 3 and FIG. 4), and includes level limiters LM1, LM2, sense amplifier SA, write back. A gate WBG, a latch LA, and a column selection gate CSG are provided.

  The level limiter LM1 includes a comparator COM2 that compares the voltage of the sense bit line SBL2 with the limit voltage VBLR so that the voltage of the sense bit line SBL2 does not exceed the limit voltage VBLR in response to the output of the comparator COM2. A limiting NMOS transistor N10 is provided. Similarly, the level limiter LM2 prevents the voltage of the sense bit line SBL2B from exceeding the limit voltage VBLR in response to the outputs of the comparator COM3 and the comparator COM3 that compare the voltage of the sense bit line SBL2B and the limit voltage VBLR. A limiting NMOS transistor N11 is provided.

  The sense amplifier SA is enabled by the sense enable signal SEN and generates voltages corresponding to the currents Ic and Icb from the sense bit lines SBL2 and SBL2B, respectively. These voltages are compared, and the result of the comparison is output as a logical value to the node “a” in FIG. For example, the floating body transistor capacitorless memory cell MC connected to the sense bit line SBL2 has a logical value “1”, and the complementary transistor cell MCB connected to the sense bit line SBL2B has a logical value “0”. Considering the case of having the current, the current Ic is larger than the current Icb. This is because the threshold voltage of the transistor cell MC is smaller than that of the complementary transistor cell MC. In this case, a voltage having a logical value corresponding to “0” is output to the node “a”.

  The latch circuit LA includes inverters I3 and I4 driven by supply voltages V1 and V2, and drives the latch node “b” to a logic level opposite to that of the latch node “a”. The supply voltage V1 is a positive voltage used to write data “1” in one of the complementary transistor cells MC and MCB, and the supply voltage V2 is the complementary transistor cell MC. , A negative voltage used to perform an operation of writing data “0” to the other one in the MCB. For example, the drain voltage Vd values for writing “1” and writing “0” are illustrated in Table 1 above. In this example, the supply voltage V1 is about 1.5V and the supply voltage V2 is about -1.5V.

  Write back gate WBG includes an NMOS transistor N12 connected between node “a” and sense bit line SBL2B, and an NMOS transistor N13 connected between node “b” and sense bit line SBL2. The write back gate WBG is enabled in a write operation by a write back signal WB (provided from the control circuit generator 30 of FIG. 3), and the data from the nodes “a” and “b” is applied to the sense bit lines SBL2B, SBL2. Transmit each.

  Column select gate CSG includes an NMOS transistor N14 connected between node "a" and data line D2B, and an NMOS transistor N15 connected between data line D2 and node "b". The column selection gate WBG is enabled in a read operation and a write operation by a column selection signal CSL (provided from the column decoder of FIG. 3), and transmits data of nodes “a” and “b” to the data lines D2B and D2, respectively. To do.

  FIG. 6 is a circuit diagram showing an example of the sense amplifier SA of FIG. As shown, the sense amplifier SA includes voltage converters CV1, CV2 and a comparator COM4. The node “b1” of the voltage converter CV1 is connected to the level limiter LM1 of FIG. 5, and the node “b2” of the voltage converter CV2 is connected to the level limiter LM2 of FIG.

  The voltage converters CV1 and CV2 each include a PMOS transistor P1 that operates as a current source enabled by a sense enable signal SEN, PMOS transistors P2 and P3 that operate as a current mirror, and an NMOS transistor N16 that operates as a diode. The sense bit line currents Ic and Icb are reflected as voltages on the respective inputs Sn and SnB of the comparator COM4. The comparator COM4 outputs the comparison result (logic “1” or “0”) to the node “a” in FIG.

  The operation of the memory device will be described with reference to FIGS. First, it will be described that the word line WL is activated and the bit sense lines SBL1 and SBL2 are selected in the “active” operation. The active operation is executed first before the write or read operation is performed. The writing and reading operations will be described in order.

  In the active operation, the row decoder 24 activates one of the word lines WL in an active (high state) state in response to the active command ACT and the first row address signal RA1. The bit line selection signal generator 28 activates one of the bit line selection signals BS <1: k / 2> in response to the active command ACT and the second row address RA2. In response to this, the even bit line selector 20-1 connects a pair of the plurality of bit lines BL / BLB having even numbers to the sense bit lines SBL2, SBL2B, and the odd bit line selector 20-1. Connects a pair of bit lines BL / BLB having odd numbers to the sense bit lines SBL1, SBL1B. The control signal generator 30 activates the sense enable signal SEN and the write back signal WB. In response to the activated sense enable signal SEN, the sense amplifiers SA are enabled from the respective sense blocks 22-1 and 22-2, and a current difference between the pair of sense bit lines SBL / SBLB selected thereby is obtained. Amplified and complementary voltages appear at nodes “a” and “b” of latch circuit LA. In response to the activated write-back signal WB, the sense blocks 22-1 and 22-2 return these complementary voltages to the selected pair of sense bit lines SBL / SBLB. The refresh operation is executed by such a method.

  In the write operation, the instruction decoder 32 decodes the write instruction WR, and the column decoder 26 activates one of the column selection lines CSL <1: m> in response to the write instruction WR and the column address CA. . As a result, the corresponding column selection gate CSG is opened, and the complementary write data on the data lines D1 / D1B and D2 / D2B are sense blocks 22-1, 22 connected to the activated selection line CSL. -2 latch LA is transmitted to the “a” and “b” nodes. The write back signal WB is transmitted to a pair of sense bit lines SBL / SBLB in which complementary write data from the “a” and “b” nodes of the latches LA of the sense blocks 22-1 and 22-2 are selected. Enabled.

  For example, when data “1” is written to a selected unit memory cell connected to a pair of bit lines BL / BLB having odd numbers, a “high” level voltage is applied to the data line D1, and a “low” level is applied. A voltage is applied to the data line D1B. Thus, a “high” level voltage is applied to node “b” of the corresponding latch LA, and a “low” level voltage is applied to node “a” of the corresponding latch LA. A supply voltage V1 having a value larger than the “high” level voltage is applied to the sense bit line SBL1, and a supply voltage V2 having a value smaller than the “low” level voltage is applied to the sense bit line SBL1B. In this manner, the floating body transistor type capacitorless memory cell MC is connected to the sense bit line SBL1 and holds data “1”, and the floating body transistor type capacitorless memory cell MC is connected to the sense bit line SBL1B. Data “0” is held. In the example of this embodiment, the complementary data indicates data “1” in the unit memory cell.

  In the read operation, the instruction decoder 32 decodes the read instruction RD, and the column decoder 26 activates one of the column selection lines CSL <1: m> in response to the read instruction RD and the column address CA. As a result, the corresponding column selection gate CSG is opened and the nodes “a” and “a” of the latch LA of the sense blocks 22-1 and 22-2 connected to the selection line CSL in which complementary read data is activated. b "to the data lines D1 / D1B and D2 / D2B.

  In the above embodiment, complementary floating body transistor capacitorless memory cells are used to define each unit memory cell. Thus, this embodiment provides the advantages of a highly integrated capacitorless memory cell structure, and at the same time, a reference (or dummy) cell for reading the logic value of the transistor cell, a reference current generator, and other Depends on conventional circuits. Also, since no reference cell is required, no time is required for refreshing the reference cell.

  In the embodiment illustrated in FIGS. 3-6, the data lines DL1 / DLB1, DL2 / DLB2 are used to write data to and read data from complementary floating body transistor capacitorless memory cells, respectively. Used for. Other embodiments provide separate read data lines and write data lines, as illustrated in FIGS.

  FIG. 7 is a block diagram of a memory device according to still another embodiment of the present invention. In the embodiment illustrated in FIG. 7, the plurality of memory blocks BLK <1: i> and circuits connected thereto are the same as those illustrated in FIG. 3, but the data line structure, read data line RD <b> 1 are the same. / RD1B, RD2 / RD2B and write data lines WD1, WD2 are different from the configuration illustrated in FIG. The column selector 26 'of FIG. 7 is the same as FIG. 3 except that it includes a separate read column select line RCSL <1: m> and write column select line WCSL <1: m>.

  Except for the following detailed description, the embodiment of FIG. 7 is similar to the embodiment of FIG. The same elements are denoted by the same numerals in the two drawings, and detailed description of common parts between the two embodiments is omitted to avoid duplication.

  Referring to FIG. 7, the memory device includes sense blocks 22-1 <1: located on opposite sides of each memory block BLK <1: i> so as to sandwich each memory block BLK <1: i>. m> and sense block 22-2 ′ <1: m>. According to the embodiment of FIG. 3, the sense block 22-1 ′ <1: m> ′ is connected to the corresponding even bit line selector 20-1 <1: m> and the sense block 22-2 <1: m>. > 'Is connected to the corresponding odd bit line selector 20-2 <1: m>. Further, unlike the embodiment of FIG. 3, the sense block 22-1 <1: m> ′ is connected to the read data line RD2 / RD2B and the write data line WD2, and the sense block 22-2 <1: m>. 'Is connected to the read data line RD1 / RD1B and the write data line WD1.

  FIG. 8 is a circuit diagram showing an example of the sense block 22-11 'shown in FIG. The remaining sense blocks 22-1 <2: m> ′ and 22-2 <1: m> ′ in the respective memory blocks BLK are similarly configured.

  Referring to FIG. 8, the sense block 22-11 'includes level limiters LM1 and LM2, a sense amplifier SA, a latch circuit LA, and a write back gate WBG. Such elements are similar to the identically numbered elements already described in FIG.

  Further, the sense block 22-11 'includes a read column selection gate RCSG and a write column selection gate WCSG.

  The read column selection gate RCSG includes NMOS transistors N19 and N20 connected between the read data line RD2 and a reference potential (for example, ground), and an NMOS transistor N21 connected between the read data line RD2B and the reference potential. , N22. The NMOS transistors N19 and N21 are connected to the read column selection signal RCSL. The NMOS transistor N20 is connected to the node “b” of the latch circuit LA, and the NMOS transistor N22 is connected to the node “a” of the latch circuit LA.

  Write column select gate WCSG includes an NMOS transistor N23 connected between write data line WD2 and node “b” of latch circuit LA. The NMOS transistor N3 is connected to the write column selection line WCSL.

  Next, the operation of the memory device of FIGS. 7 and 8 will be described. During the active operation, the row decoder 24 activates (high state) one of the word lines WL in response to the active command ACT and the first row address signal RA1. The bit line selection signal generator 28 activates one of the bit line selection signals BS <1: k / 2> in response to the active command ACT and the second row address RA2. As a result, the even bit line selector 20-1 connects a pair of the plurality of bit lines BL / BLB having even numbers to the sense bit lines SBL2, SBL2B, and the odd bit line selector 20-2 One pair of a plurality of pairs of bit lines BL / BLB having odd numbers is connected to the sense bit lines SBL1 and SBL1B. The control signal generator 30 activates the sense enable signal SEN and the write back signal WB. In response to the activated sense enable signal SEN, the sense amplifiers SA arranged in the respective sense blocks 22-1 <1: m> ′ and 22-2 <1: m> ′ are enabled, thereby The current difference between the selected pair of sense bit lines SBL / SBLS is amplified and appears as a complementary voltage at the nodes “a” and “b” of the latch circuit LA. In response to the activated write-back signal WB, the sense blocks 22-1 <1: m> ′ and 22-2 <1: m> ′ have a pair of sense bit lines SBL selected with complementary voltages. Return to / SBLB. The refresh operation is executed by such a method.

  In the write operation, the instruction decoder 32 decodes the write instruction WR, and the column decoder 26 activates one of the write column selection lines WCSL <1: m> in response to the write instruction WR and the column address CA. As a result, the corresponding write column selection gate WCSG is opened, and the write data in the write data lines WD1 and WD2 is transmitted to the node “b” of the latch circuit LA of the sense block 22-1 <1: m> ′. At this time, complementary data automatically appears at the node “a” by the operation of the latch circuit LA. Further, the write-back signal WB is a pair of sense bits selected from the nodes “a” and “b” of the latch circuit LA of the sense blocks 22-1 <1: m> ′ and 22-2 <1: m> ′. It is activated to transmit write data complementary to the line SBL / SBLB.

  During the read operation, the instruction decoder 32 decodes the read instruction RD, and the column decoder 26 activates one of the read column selection lines RCSL <1: m> in response to the read instruction RD and the column address CA. . As a result, the corresponding read column selection gate RCSG is opened, and the sense blocks 22-1 <1: m> ′ and 22-2 <1 connected to the read column selection line RCSL in which complementary read data is activated. Is transmitted from the “a” and the node “b” of the latch circuit LA of m> ′ to the read data lines RD1 / RD1B and RD2 / RD2B.

  In the above-described embodiment, the complementary floating body transistor type capacitorless memory cells MC constitute a unit memory cell and are mutually arranged on the complementary bit lines BL / BLB in each memory block. FIG. 9 shows an “open bit line”, in which complementary floating body transistor capacitorless memory cells are arranged in other memory blocks.

  FIG. 9 is a block diagram of a floating body transistor capacitorless memory cell memory device according to an embodiment of the present invention.

  9 includes a memory cell array block BLK2 having a plurality of subarray blocks SBLK1 <1: m> and a plurality of subarray blocks SBLK2 <1: m> therein, a plurality of bit lines and an inverted bit line BL selector 20. -1 <1: m> ', 20-2 <1: m>', multiple sense blocks 22-2 <1: m>, row decoder 24, column decoder 26, bit line selection signal generator 28 ', control A memory cell array block BLK1 including a signal generator 30 and an instruction decoder 32 is provided.

  The memory cell array blocks BLK1 and BLK2 together constitute a single block of memory. Although only a single memory block is shown in FIG. 9 for simplicity, the memory device includes a plurality of memory blocks having the same configuration.

  The sub-array block SBLK of each memory cell array block BLK1 includes a plurality of “true” floating body transistor type capacitorless memory cells MC, while the sub-array block SBLK of each memory cell array block BLK2 corresponds to each sub-array block SBLK. A plurality of “complementary” floating body transistor type capacitorless memory cells MC are provided. Here, unlike the previous embodiment, the positive or complementary floating body transistor type capacitorless memory cell MC defines each unit memory cell and is located in the other memory cell blocks BLK1 and BLK2.

  The sub-array blocks SBLK <1: m> of the memory cell array block BLK1 share the same positive word line WL1. Here, the sub-array blocks SBLK <1: m> of the memory cell array block BLK2 share the same complementary word line WL2.

  Each subarray block SBLK of the memory cell array block BLK1 includes a plurality of positive bit lines BL <1: k>, and each subarray block SBLK of the memory cell array block BLK2 includes a plurality of complementary bitlines BLB <1: k>. It has. Each pair of bit line BL and inverted bit line BLB is referred to as a pair of bit lines. Thus, in the example of this embodiment, there are “k” pairs of bit lines for each pair of subarray blocks SBLK.

  As in the previous embodiment, a “unit memory cell” is defined by a first floating body transistor capacitorless memory cell connected between a bit line BL and a reference potential (eg, ground). The unit memory cell holds a logical value indicated by a complementary threshold voltage state of the first and second floating body transistor type capacitorless memory cells. That is, in each of the unit memory cells, the complementary first and second floating body transistor type capacitorless memory cells have opposite threshold voltage states. In the example of this embodiment, the floating body transistor capacitorless memory cell is an NMOS transistor.

  The complementary first and second floating body transistor type capacitorless memory cells of each unit memory cell are connected to the positive word line WL1 and the complementary word line WL2.

  The positive bit line selector 20-1 <1: m> ′ and the inverted bit line selector 20-2 <1: m> ′ have a memory block BLK1 so as to sandwich the corresponding sense block 22-1 <1: m>. , BLK2. Each bit line selector 20-1 'is connected to the positive bit line BL, and each inverted odd bit line selector 20-2 is connected to the inverted bit line BLB.

  Referring to FIG. 3, the sense blocks 22-1 <1: m> are respectively connected to the positive bit line and inverted bit line selectors 20-1 <1: m> ′ and 20-1 <1: m> ′. It is connected. In particular, the inverted sense bit lines SBL1 <1: m> and SBL1B <1: m> have their respective positive bit line and inverted bit line selectors 20-2 <1: m> ′, 20-1 <1: m>. And the corresponding sense block 22-1 <1: m>.

  Examples of the positive and inverted bit line selectors 20-1 'and 20-2' and the sense blocks 22-1 and 22-2 will be described in detail later.

  The instruction decoder 32 generates an active instruction ACT, a read instruction RD, and a write instruction WD in response to the instruction signal COM.

  In response to the active command ACT, the row decoder 24 decodes the first row address RA1 and activates the corresponding one in the word line WL.

  In response to the active command ACT, the bit line selection signal generator 28 'decodes the second row address RA2 and activates one of the bit line selection signals BS <1: k>. As shown in FIG. 9, the bit line selection signals BS <1: k> are applied to the bit line and inverted bit line selectors 20-1 <1: m> 'and 20-2 <1: m>'.

  The column decoder 26 decodes the column address CA in response to the read command RD and the write command WR, and activates one or more of the corresponding column selection signals CSL <1: m>. The column selection signal CSL <1: m> is applied to each sense block 22-1 <1: m> as shown in FIG.

  The control signal generator 32 selectively activates the sense amplification enable signal SEN and the write back signal WB in response to the active signal ACT. In particular, the write back signal WB is activated for a predetermined time after the sense amplification enable signal SEN is activated. As shown in FIG. 9, this signal is applied to the sense block 22-1 <1: m>.

  Further, as shown in FIG. 9, the complementary data lines D1 and D1B are connected to the sense block 22-2 <1: m>.

  Examples of the positive and inverted bit line selectors 20-1 'and 20-2' of FIG. 9 will be described later in connection with FIGS. 10A and 10B. In particular, FIG. 10A is a circuit diagram illustrating an example of a positive bit line selector 20-1 ', and FIG. 10B is a circuit diagram illustrating an example of an inverted bit line selector 20-2'.

  As shown in FIG. 10A, the bit line selector 20-1 of this example includes NMOS transistors N19- <1: k connected between a pair of bit lines BL <1: k> and a sense bit line SBL, respectively. >. The NMOS transistors N19- <1: k> are connected to the bit line selection signals BS <1: k> generated by the bit line selection signal generator 28 ', respectively. The positive bit line selector 20-1 selectively connects one of the bit line selection signals BS <1: k> to the cent bit line SBL.

  The inverted bit line selector 20-2 in this example includes NMOS transistors N19- <1: k> connected between each pair of inverted bit lines BLB <1: k> and the inverted sense bit line SBLB. . The NMOS transistors N19- <1: k> are connected to the bit line selection signals BS <1: k> generated by the bit line selection signal generator 28 ', respectively. The inverted bit line selector 20-21 selectively connects one of the inverted bit lines BLB <1: k> to the inverted sense bit line SBLB in response to the bit line selection signal BS <1: k>.

  The sense block 22-1 <1: m> is configured in the same manner as in FIGS.

  The operation of the memory device of FIGS. 9, 10A, and 10B will be further described.

  In the active operation, the row decoder 24 activates (in a high state) one of the word lines WL in response to the active command ACT and the first row address signal RA1. The bit line selection signal generator 28 activates one of the bit line selection signals BS <1: k> in response to the active command ACT and the second row address RA2. As a result, the bit line selector 20-1 connects one of the bit lines BL to the sense bit line SBL, and the inverted bit line selector 20-2 selects one of the inverted bit lines BLB as an inverted sense bit. Connect to line SBL. The control signal generator 30 activates the sense enable signal SEN and the write back signal WB. In response to the activated sense enable signal SEN, the sense amplifiers SA in the respective sense blocks 22-1 are enabled, thereby amplifying the current difference between the selected pair of sense bit lines SBL / SBLB. , Appear as complementary voltages at nodes “a” and “b” of the latch circuit LA (see FIG. 5). In response to the activated write-back signal WB, the sense block 22-1 returns a complementary voltage to the selected pair of sense bit lines SBL / SBLB. The refresh operation is executed by such a method.

  In the write operation, the instruction decoder 32 decodes the write instruction WR, and the column decoder 26 activates one of the column selection lines CSL <1: m> in response to the write instruction WR and the column address CA. As a result, the corresponding column selection gate CSG is opened (see FIG. 5), and the sense block 22-1 connected to the selection line CSL in which complementary write data on the data line D1 / D1B is activated. Are transmitted to the nodes “a” and “b” of the latch LA. The write-back signal WB is enabled to transmit complementary write data from the nodes “a” and “b” of the latch LA of the sense block 22-1 to the selected pair of sense bit lines SBL / SBLB. .

  In the read operation, the instruction decoder 32 decodes the read instruction RD, and the column decoder 26 activates one of the column selection lines CSL <1: m> in response to the read instruction RD and the column address CA. As a result, the corresponding column selection gate CSG is opened, and the nodes from the nodes “a” and “b” of the latch LA of the sense block 22-1 connected to the selection line CSL in which the inverted read data is activated. It is transmitted to the data line D1 / D1B.

  Still another embodiment of the present invention will be described with reference to the circuit diagram of FIG. The embodiment of FIG. 11 is a modification of the embodiment of FIG. 9 while the embodiment of FIG. 7 is a modification of the embodiment of FIG.

  11 shows (a) FIG. 11 shows a plurality of pairs of memory blocks BLK <1: i> and circuits related thereto, and (b) FIG. 11 shows another data line structure (ie, read). (C) read column selection line RCSL <1: m> and write column selection line WCSL <1: separated by the column selector 26 'of FIG. Equivalent to FIG. 9 except that m>.

  Except as described below, the embodiment of FIG. 11 is similar to the embodiment of FIG. In the two drawings, the same elements are denoted by the same numbers, and detailed description of common parts between the two embodiments is omitted to avoid duplication.

  Referring to FIG. 11, the memory device includes a sense block 22-2 positioned between a corresponding bit line and inverted bit line selector 20-1 <1: m> ′, 20-2 <1: m> ′. <1: m> ′. As in the embodiment of FIG. 9, the sense blocks 22-2 <1: m> ′ are connected to the corresponding sense bit lines SBL and inverted sense bit lines SBLB. Also, unlike the embodiment of FIG. 9, the sense block 22-2 <1: m> ′ is connected to the read data lines RD1, RD1B and the write data line WD1.

  The sense block 22-2 <1: m> in FIG. 11 is configured in the manner already described in connection with FIG.

  Next, the operation of the memory device of FIG. 11 will be described. During the active operation, the row decoder 24 activates (sets as a high value) one of the word lines WL in response to the active command ACT and the first row address signal RA1. The bit line selection signal generator 28 'activates one of the bit line selection signals BS <1: k> in response to the active command ACT and the second row address RA2. As a result, the positive bit line selector 20-1 ′ connects one of the bit lines BL to the sense bit line SBL, and the inverted bit line selector 20-2 ′ selects one of the corresponding inverted bit lines BLB. Are connected to the inverted sense bit line SBL. The control signal generator 30 activates the sense enable signal SEN and the write back signal WB. In response to the activated sense enable signal SEN, the sense amplifiers SA in the respective sense blocks 22-2 are enabled, thereby amplifying the current difference between the selected pair of sense bit lines SBL / SBLB. , Complementary voltages appear at nodes “a” and “b” of the latch circuit LA (see FIG. 5). In response to the activated write back signal WB, the sense block 22-2 returns these complementary voltages to the selected pair of sense bit lines SBL / SBLB. The refresh operation is executed by such a method.

  In the write operation, the instruction decoder 32 decodes the write instruction WR, and the column decoder 26 activates one of the write column selection lines WCSL <1: m> in response to the write instruction WR and the column address CA. Let As a result, the corresponding write column selection gate WCSG is opened (see FIG. 8), and the write data on the write data line WD1 is activated in the sense block 22-2 connected to the write column selection line CSL. It is transmitted to the node “b” of the latch circuit LA. The inverted write data is automatically applied to the node “a” by the operation of the latch circuit LA. The write-back signal WB activates transmission of complementary write data from the nodes “a” and “b” of the latch LA of the sense block 22-2 to the selected pair of sense bit lines SBL / SBLB. Let

  In the read operation, the instruction decoder 32 decodes the read instruction RD, and the column decoder 26 activates one of the read column selection lines RCSL <1: m> in response to the read instruction RD and the column address CA. Let As a result, the corresponding read column selection gate CSG is opened (see FIG. 8), and the node of the latch circuit LA of the sense block 22-2 connected to the read column selection signal RCSL in which complementary read data is activated. The data is transmitted from “a” and “b” to the read data lines RD1 / RD1B.

  The above-described embodiments are partially specified by the use of complementary floating body transistor type capacitorless memory cells to define each unit memory cell of a memory device such as a DRAM device. Thus, the embodiments provide the advantages of highly integrated capacitorless memory cell structures and also read the logic values of reference (or dummy) cells, reference current generators, and other conventional transistor cells. The circuit for this is made unnecessary. Further, since the reference cell is not required, the reference cell refresh time is not required.

  Although the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will recognize that the invention is within the scope and spirit of the invention as defined by the appended claims. Can be modified and changed in various ways.

It is sectional drawing of the conventional floating body transistor type capacitor-less memory cell. It is a graph which shows cell current distribution of the conventional floating body transistor type | mold capacitorless memory cell. It is a graph which shows cell current distribution of the conventional floating body transistor type | mold capacitorless memory cell. It is a graph which shows cell current distribution of the conventional floating body transistor type | mold capacitorless memory cell. 1 is a block diagram of a memory device including a floating body transistor capacitorless memory cell according to an embodiment of the present invention. FIG. 5 is a circuit diagram of an even bit line selector according to an embodiment of the present invention. FIG. 4 is a circuit diagram of an odd bit line selector according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a sense block according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a sense amplifier according to an embodiment of the present invention. FIG. 6 is a block diagram of a floating body transistor type capacitorless memory cell memory device according to another embodiment of the present invention. FIG. 6 is a circuit diagram of a sense block according to still another embodiment of the present invention. 1 is a block diagram of a floating body transistor capacitorless memory cell memory device according to an embodiment of the present invention; FIG. FIG. 5 is a circuit diagram of a bit line selector according to still another embodiment of the present invention. FIG. 6 is a circuit diagram of an inverting bit line selector according to still another embodiment of the present invention. 1 is a block diagram of a floating body transistor capacitorless memory cell memory device according to an embodiment of the present invention; FIG.

Explanation of symbols

21-1, 20-2 Even and odd bit line BL selector 22-1, 22-2 Sense block 24 Row decoder 26 Column decoder 28 Bit line selection signal generator 30 Control signal generator 32 Instruction decoder ACT Active instruction BL bit Line BLB Inverted bit line BLK1 Memory cell array block COM Command signal D1, D1B First complementary data line D2, D2B Second complementary data line MC Memory cell RD Read command SBL2, SBL2B Inverted sense bit line SBLK Subarray block WD Write Command WL1 Word line

Claims (34)

Comprising a memory cell array having a plurality of unit memory cells;
2. A semiconductor memory device according to claim 1, wherein each of the unit memory cells includes a first and a second floating body transistor type capacitorless memory cell which are complementary. The semiconductor memory device includes:
2. The semiconductor memory according to claim 1, further comprising a plurality of pairs of complementary bit lines connected to the complementary first and second floating body transistor type capacitorless memory cells of the unit memory cell. apparatus. The semiconductor memory device includes:
At least one data line;
A sensing circuit operatively connected to the at least one data line;
A bit line selector for selectively connecting a pair of bit lines selected from the plurality of pairs of bit lines to the sensing circuit;
The semiconductor memory device according to claim 2, further comprising:   4. The semiconductor memory device according to claim 3, wherein the at least one data line is a first and a second complementary data line. The sensing circuit is
A latch circuit comprising a first latch node operatively connected to the first complementary data line and a second latch node operatively connected to the second complementary data line;
A sense amplifier having first and second inputs operatively connected to the selected pair of bit lines and an output operatively connected to one at the first and second latch nodes of the latch circuit. When,
5. The semiconductor memory device according to claim 4, further comprising: The semiconductor memory device includes:
First and second data read lines complementary to the data write lines;
A sensing circuit operatively connected to the data write line and the complementary first and second data read lines;
A bit line selector for selectively connecting a pair of bit lines selected from the plurality of pairs of bit lines to the sensing circuit;
The semiconductor memory device according to claim 2, further comprising: The sensing circuit is
A latch circuit comprising a first latch node operatively connected to the first data read line, a second latch node operatively connected to the second data read line and the data write line;
First and second inputs operatively connected to the selected pair of bit lines, respectively, and operatively connected to one of the first latch node and the second latch node of the first latch circuit. A sense amplifier including an output,
The semiconductor memory device according to claim 6, further comprising:   2. The semiconductor memory device according to claim 1, wherein the complementary first and second floating body transistor type capacitorless memory cells of the unit memory cell are alternately arranged in the same memory block.   2. The semiconductor memory device according to claim 1, wherein the complementary first and second floating body transistor type capacitorless memory cells of the unit memory cell are disposed in another memory block.   2. The semiconductor memory device according to claim 1, wherein the logical value of each unit memory cell is defined by a difference in threshold voltage between the complementary first and second floating body transistor type capacitorless memory cells. A plurality of unit memory cells arranged in rows and columns, each of the unit memory cells including a first and second floating body transistor type capacitorless memory cells complementary;
A first odd-numbered bit connected to each odd-numbered row of the unit memory cells, and each odd-numbered pair of bit lines connected to the first floating body transistor type capacitorless memory cell in each odd-numbered row A plurality of odd-numbered pairs of bit lines including a second odd-numbered bit line connected to the second floating body transistor capacitorless memory cell in each odd-numbered row;
A first even-numbered bit connected to each even-numbered row of the unit memory cells, and each even-numbered pair of bit lines connected to the first floating body transistor type capacitorless memory cell in each even-numbered row A plurality of even-numbered bit lines including a second even-numbered bit line connected to the second floating body transistor capacitorless memory cell in each even-numbered row;
Odd-numbered and even-numbered sensing circuits;
A pair of odd and even sense bits line operatively connected to each of the odd and even sensing circuits;
An odd-numbered bit line selector that selectively connects an odd-numbered pair of bit lines selected from the plurality of odd-numbered pairs of bit lines to the odd-numbered pair of sense bit lines;
An even-numbered bit line selector that selectively connects an even-numbered bit line selected from the plurality of even-numbered bit lines to the even-numbered pair of sense bit lines;
A semiconductor memory device comprising: The semiconductor memory device includes:
The method further comprises a first complementary data line operatively connected to the odd-numbered sensing circuit and a second complementary data line operatively connected to the even-numbered sensing circuit. The semiconductor memory device according to claim 11. The odd-numbered sensing circuit is
A first latch node operatively connected to one of the first complementary data lines and a second latch node operatively connected to the other one of the first complementary data lines; A first latch circuit;
First and second inputs operatively connected to each of the odd pair of bit lines and an output operatively connected to one of the first and second latch nodes of the first latch circuit. A first sense amplifier,
The even-numbered sensing circuit is
A first latch node operatively connected to one of the second complementary data lines and a second latch node operatively connected to the other one of the second complementary data lines; A second latch circuit;
First and second inputs operatively connected to each of the even pair of sense bit lines and an output operatively connected to one of the first and second latch nodes of the second latch circuit. 13. The semiconductor memory device according to claim 12, further comprising a second sense amplifier. The semiconductor memory device includes:
14. The semiconductor memory device as claimed in claim 13, further comprising a column decoder for generating a column selection signal in response to the column address. The odd-numbered sensing circuit is
A first transmission gate controlled by the column selection signal and connected between the first and second latch nodes of the first latch circuit and each of the odd pair of bit lines;
The even-numbered sensing circuit is
And a second transmission gate controlled by the column selection signal and connected between the first and second latch nodes of the second latch circuit and each of the even-numbered sense bit lines. The semiconductor memory device according to claim 14. The semiconductor memory device includes:
A first data write line and a first complementary data read line operatively connected to each of the first sensing circuits, and a second data write line and a second operatively connected to each of the second sensing circuits. The semiconductor memory device according to claim 11, further comprising a complementary data read line. The odd-numbered sensing circuit is
A first latch node operatively connected to one of the first complementary data lines, and operatively connected to the other one of the first complementary data read lines and the first data write line. A first latch circuit comprising a second latch node connected;
First and second inputs operatively connected to each of the odd pair of sense bit lines and an output operatively connected to one of the first and second latch nodes of the first latch circuit. A first sense amplifier comprising:
The even-numbered sensing circuit is
A first latch node operatively connected to one of the second complementary data read lines and another one of the second complementary data read line and operably connected to the data write line. A second latch circuit comprising a second latch node;
First and second inputs operatively connected to each of the even pair of sense bit lines and an output operatively connected to one of the first and second latch nodes of the second latch circuit. 17. The semiconductor memory device according to claim 16, further comprising a second sense amplifier. The semiconductor memory device includes:
18. The semiconductor memory device of claim 17, further comprising a column decoder that generates a read column selection signal and a write column selection signal in response to a column address and a read / write command. The odd-numbered sensing circuit is
A first transmission gate controlled by the read column selection signal and operatively connected between the first and second latch nodes of the first latch circuit and each of the odd pair of sense bit lines; Equipped,
The even-numbered sensing circuit is
A second transmission gate controlled by the read column selection signal and operatively connected between the first and second latch nodes of the second latch circuit and each of the even-numbered pair of sense bit lines; 19. The semiconductor memory device according to claim 18, further comprising: The odd-numbered sensing circuit is
A first transmission gate controlled by the write column selection gate and operatively connected between the second latch node of the first latch circuit and the first data write line;
The even-numbered sensing circuit is
And a second transmission gate controlled by the write column selection signal and operatively connected between the second latch node of the second latch circuit and the second write data line. The semiconductor memory device according to claim 18. The logical value of each unit memory cell is
12. The semiconductor memory device of claim 11, wherein the semiconductor memory device is defined by a difference in threshold voltage between the complementary first and second floating body transistor type capacitorless memory cells. A plurality of unit memory cells, each of the unit memory cells being a first floating body transistor type capacitorless memory cell located in the first memory block array and a complementary second floating body transistor located in the second memory block array A memory cell array comprising a type capacitorless memory cell;
A plurality of first bit lines located in the first memory block array and operatively connected to corresponding first floating body transistor type capacitorless memory cells;
A plurality of second bit lines located in the first memory block array and operatively connected to a corresponding second floating body transistor capacitorless memory cell;
A sensing circuit operatively located between the first and second memory block arrays;
A pair of sense bit lines operatively connected to the sensing circuit;
A first bit line selector that selectively connects a first bit line of the plurality of first bit lines to one of the pair of sense bit lines;
A first bit line selector that selectively connects a second bit line of the plurality of second bit lines to the other one of the pair of sense bit lines;
A semiconductor memory device comprising: The semiconductor memory device includes:
23. The semiconductor memory device of claim 22, further comprising a complementary data line operatively connected to the sensing circuit. The sensing circuit is
A latch circuit comprising a first latch node operatively connected to one of the complementary data lines and a second latch node operatively connected to the other one of the complementary data lines;
A sense amplifier having first and second inputs operatively connected to each of the pair of sense bit lines and an output operatively connected to one of the first and second latch nodes of the latch circuit; ,
24. The semiconductor memory device according to claim 23, comprising: The semiconductor memory device includes:
25. The semiconductor memory device of claim 24, further comprising a column decoder for generating a column selection signal in response to the column address. The sensing circuit is
26. The semiconductor device according to claim 25, further comprising a transmission gate controlled by the column selection signal and connected between the first and second latch nodes of the latch circuit and the pair of sense bit lines. Memory device. The semiconductor memory device includes:
23. The semiconductor memory device of claim 22, further comprising a data read line complementary to a data write line operatively connected to the sensing circuit. The sensing circuit is
A first latch node operatively connected to one of the complementary data read lines; a second latch node operatively connected to the other one of the complementary data read lines and the data write line; A latch circuit comprising:
A sense amplifier having first and second inputs operatively connected to each of the pair of sense bit lines and an output connected to one of the first and second latch nodes of the latch circuit;
28. The semiconductor memory device according to claim 27, comprising: The semiconductor memory device includes:
29. The semiconductor memory device of claim 28, further comprising a column decoder for generating a read column selection signal and a write column selection signal in response to a column address and a read / write command. The sensing circuit is
And a transmission gate controlled by the read column selection signal and operatively connected between the first and second latch nodes of the latch circuit and the pair of sense bit lines. Item 30. The semiconductor memory device according to Item 29. The sensing circuit is
30. The semiconductor device according to claim 29, further comprising a transmission gate controlled by the write column selection signal and operatively connected between the second latch node of the latch circuit and the data write line. Memory device. The logical value of each unit memory cell is
23. The semiconductor memory device of claim 22, wherein the semiconductor memory device is defined by a difference in threshold voltage between the complementary first and second floating body transistor type capacitorless memory cells. Setting the threshold voltage state of the first floating body transistor type capacitorless memory cell as the first threshold voltage state;
Setting a threshold voltage state of the second floating body transistor type capacitorless memory cell as a second threshold voltage state different from the first threshold voltage state;
The first and second floating body transistor type capacitorless memory cells constitute a unit memory cell, and a logical value used for each unit memory cell is the first and second floating body transistor type capacitorless memory cells. And a method of writing data in a semiconductor memory device comprising a floating body transistor type capacitorless memory cell, wherein the method is defined by a second threshold voltage state. Determining a threshold voltage state of the first floating body transistor capacitorless memory cell;
Determining a threshold voltage state of the second floating body transistor capacitorless memory cell;
The first and second floating body transistor type capacitorless memory cells constitute a unit memory cell, and each of the first and second floating body transistor type capacitorless memory cells has a difference between the first and second threshold voltage states of the first and second floating body transistor type capacitorless memory cells. A data write method in a semiconductor memory device having a floating body transistor type capacitorless memory cell, wherein a logical value of a unit memory cell is determined.

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