JP2003297074A - Ferroelectric memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory device in which area of a sense amplifier circuit region can be reduced without increasing the number of metal wiring layers. <P>SOLUTION: A sense amplifier circuit 3 is arranged between two cell arrays 1, 2 in which ferroelectric memory cells are arranged, and two cell arrays 1, 2 share the sense amplifier circuit 3. Column gates 6, 7 and column decoders 8, 9 are arranged at both end parts on an opposite side to the sense amplifier circuit 3 of the cell arrays 1, 2. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device for storing data in a nonvolatile manner using a ferroelectric capacitor.

[0002]

2. Description of the Related Art A ferroelectric memory stores binary data in a nonvolatile manner according to the magnitude of remanent polarization of a ferroelectric capacitor. A memory cell of a conventional ferroelectric memory is generally D
Like a RAM, it is configured by connecting a ferroelectric capacitor and a transistor in series. However, unlike the DRAM, the ferroelectric memory retains data by the amount of remanent polarization, so that it is necessary to drive the plate line to read the signal charge to the bit line. Therefore, in the conventional ferroelectric memory, the plate line driving circuit requires a large area.

On the other hand, Takashima et al. Have proposed a cell array system of a ferroelectric memory capable of reducing the area of the plate line driving circuit. This is a ferroelectric capacitor (C) at the source and drain of the cell transistor (T).
Both ends of each are connected to form a unit cell, and a plurality of these unit cells are connected in series to form a cell block (D. Takashima et al., "High-density c
hain feroelectric random memory (CFRAM) "in Proc.
VSLI Symp. June 1997, pp.83-84). In this TC parallel unit serial connection type ferroelectric memory, since the plate line drive circuit can be shared by, for example, eight unit cells, the cell array can be highly integrated.

In the data of the ferroelectric memory, for example, the positive remanent polarization state is data "1" and the negative remanent polarization state is data "0". At this time, the principle of data reading is
It looks like this: The reading of "1" data is a destructive reading in which a voltage is applied from the plate line to the ferroelectric capacitor to invert the polarization. When the plate line is returned to the low level after reading "1" data, a reverse voltage is applied to the ferroelectric capacitor by the voltage amplified by the sense amplifier, and polarization is inverted again to rewrite "1" data. The “0” data read is a non-destructive read without polarization inversion, and no voltage is applied to the ferroelectric capacitor even after the read, and “0” is rewritten as it is.

[0005]

DISCLOSURE OF THE INVENTION In a ferroelectric memory,
As the sense amplifier, for example, a flip-flop type sense amplifier similar to DRAM is used. However, in the case of a DRAM, the sense amplifier activation transistor is arranged outside the cell array and shared by a plurality of sense amplifiers, whereas in the case of a ferroelectric memory, an activation transistor is provided for each sense amplifier. The arrangement method is adopted. this is,
This is because a higher drivability in the DRAM is required for writing to the ferroelectric capacitor. Further, depending on the cell array system, a reference voltage generating circuit for applying a reference voltage to one of the bit line pairs is required, which must also be arranged in the sense amplifier circuit area. Therefore, the area of the sense amplifier circuit area is larger than that of a normal DRAM.

On the other hand, it is preferable to effectively use the chip area that the two cell arrays share the sense amplifier circuit. However, even if the shared sense amplifier system is used, another problem remains. When the column decoder is arranged on one end side of the array of the plurality of cell arrays, it is necessary to arrange the column selection line across the plurality of cell array regions, and for example, metal wiring of three layers or more must be formed. However, if the interlayer insulating film deposition and the metal wiring formation are repeated a large number of times after forming the ferroelectric capacitor, the ferroelectric capacitor suffers large thermal damage and cannot obtain sufficient residual polarization. From the viewpoint of reliability, it is desirable to reduce the number of layers of such metal wiring as much as possible.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a ferroelectric memory device capable of reducing the area of the sense amplifier circuit region without increasing the number of metal wiring layers. .

[0008]

In a ferroelectric memory device according to the present invention, a word line and a bit line are arranged so as to intersect with each other, and a transistor driven by the word line and this transistor are provided at the intersection. A first and a second cell array in which memory cells made of a ferroelectric capacitor, one end of which is connected to the bit line and the other end of which are connected to the plate line, are arranged, and between the first and second cell arrays. A sense amplifier circuit which is shared by the first and second cell arrays and detects and amplifies data of a selected memory cell;
Column decoders for selecting bit lines respectively arranged at ends of the first and second cell arrays opposite to the sense amplifier circuit.

According to the present invention, the sense amplifier circuit is shared by the two cell arrays, and the column decoder is arranged on the side opposite to the sense amplifier circuit of each of these cell arrays, whereby the column selection line is arranged across the cell array. Without doing so, the area of the sense amplifier circuit can be reduced.

In a preferred memory cell array to which the present invention is applied, memory cells are formed by connecting both ends of a ferroelectric capacitor to the source and drain of a transistor, and memory cells driven by a plurality of word lines are connected in series. Form a cell block. Then, one ends of two cell blocks adjacent to each other in the word line direction are connected to different plate lines, and the other ends are connected to a pair of bit lines via block selection transistors.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a cell array configuration of a ferroelectric memory to which the present invention is applied. In this embodiment, the two cell arrays 1 and 2 share the sense amplifier circuit 3 arranged between them. Bit lines BL, BBL (BL0, BL0,
BBL0, BL1, BBL1, ...) have a folded bit line structure and are connected to the sense node of the sense amplifier circuit 3 through the select gates 4 and 5, respectively. The selection gates 4 and 5 are controlled by the selection signals PT0 and PT2, and the sense amplifier circuit 3 is connected to only one of the cell arrays 1 and 2.

In the case of this embodiment, the cell arrays 1 and 2 are constructed as shown in FIG. A unit cell (memory cell) MC is composed of a ferroelectric capacitor C and a cell transistor T connected in parallel. In the example of the figure, eight such unit cells MC are connected in series to form a cell block MCB (MCB0, MCB1). , ...) are configured. Such a cell array configuration is called a TC parallel unit series connection type.

One end N1 of the cell block MCB is connected to the bit lines BL and BBL via block selection transistors Q10 and Q11, respectively, and the other end N2 is connected to the plate lines PL and BPL, respectively. The gate of the cell transistor of each cell block MCB is the word line WL.
(WL0 to WL7).

Bit lines BL and BB of each cell array 1 and 2
An end portion of L opposite to the sense amplifier circuit 3 is provided with data lines DQ and BDQ (DQ0, BDQ0, DQ1, BD) arranged in parallel with the word line WL via the column gates 6 and 7.
Q1, ...). And the data lines DQ, B
Column decoders (CD) 8 and 9 for selectively driving the column gates 6 and 7 are arranged outside the DQ.
Therefore, the column select line CSL (CSL00, CSL01, ..., CSL1) for driving the gates of the column gates 6 and 7 is used.
0, CSL11, ...) Are arranged outside the regions of the cell arrays 1 and 2.

FIG. 3 shows a specific structure of the sense amplifier circuit 3. In the sense amplifier body 31, the drains are connected to the sense nodes BLSA and BBLSA, respectively, and the gates are respectively connected to the sense nodes BBLSA and BLS.
A flip-flop composed of PMOS transistors QP1 and QP2 connected to A, and a flip-flop composed of NMOS transistors QN1 and QN2 whose drains are respectively connected to sense nodes BLSA and BBLSA and whose gates are connected to sense nodes BBLSA and BLSA, respectively. It is composed of The common source of the PMOS transistors QP1 and QP2 is the activation PMO.
Connected to the power supply Vaa via the S transistor QP3,
The common source of the NMOS transistors QN1 and QN2 is
It is connected to the ground potential Vss through the activation NMOS transistor QN3.

A bit line equalize circuit 32 is also formed between the sense nodes BLSA and BBLSA. The equalize circuit 32 includes sense nodes BLSA, B
NMOS transistors QN4 and QN5 for connecting BLSA to Vss and sense nodes BLSA and BBLS
It has an NMOS transistor QN6 for shorting A. The gates of these transistors are controlled by the equalize control line EQL, and the sense nodes BLSA and BSA are controlled.
BLSA and therefore these sense nodes BLSA, BB
The bit lines BL and BBL connected to LSA are precharged / equalized to Vss prior to the active operation.

Further, in the sense amplifier circuit 3, when a signal voltage is read out to one of the bit lines BL and BBL, a reference voltage generating circuit 3 for giving a reference voltage to the other one.
3 is provided. In this example, the reference voltage generation circuit 33
Is a capacitor C whose one end is driven by the drive line DPL.
It is constructed using r. The other end of the capacitor Cr is connected to Vss via the reset NMOS transistor QN9 during standby, and selectively activated by the NMOS transistors QN7 and QN8 during activation.
Connected to BBL.

Thus, when data is read, for example, when data is read to one bit line BL, the node of the capacitor Cr is connected to the other bit line BBL. Then, by capacitively coupling the voltage applied to the drive line DPL with the capacitor Cr,
Reference voltage Vref is applied to bit line BBL. By setting the reference voltage Vref to the middle of the read voltages of the data “0” and “1”, the sense amplifier main body 31 can determine the data.

The operation of the ferroelectric memory of this embodiment will be described. FIG. 4 is an operation timing chart of the ferroelectric memory. The unit cell MC stores the positive remanent polarization state of the ferroelectric capacitor as data “1” and the negative remanent polarization state as data “0”. During standby, all word lines WL are "H", block selection signal B
S0 and BS1 are kept at "L", and the bit lines BL and BBL and the plate lines PL and BPL are kept at the low level VSS. At this time, the ferroelectric capacitor C has its terminals short-circuited by the cell transistor T in the ON state, and holds the data.

It is assumed that the active operation is started and the word line WL6 on the cell array 1 side is selected by the row address. At this time, the cell array 1 is connected to the sense amplifier circuit 3
The select line PT0 for connecting to the line becomes "H", and at the same time, the word line WL6 becomes "L". Then bit line B
When selecting the BL-side unit cell of L and BBL, the block selection signal BS0 is set to “H” and the plate line PL is set from the low level Vss (ground voltage) to the high level Vaa.
(Positive voltage) (time t0). As a result, the voltage is applied to the ferroelectric capacitor C of the selected unit cell MC, and the signal voltage is read to the bit line BL according to the data “0” and “1”.

The signal voltage read to the bit line BL is
It is detected by comparison with the reference voltage Vref applied to the paired bit lines BBL. That is, by setting the center amplifier activation signal NSAE = "H" and PSAE = "L" at time t1, the sense amplifier SA causes the bit line BL to be changed.
Becomes Vaa when the data is "1" and Vss when the data is "0". In the read mode, the sense amplifier data is selected by the column gate 6 and transferred to the data buffer via the data lines DQ and BDQ. After that, by returning the plate line PL to Vss at time t2, the data read to the sense amplifier SA is rewritten as it is. Then, after turning off the block selection transistor, the sense amplifier SA is deactivated and the selected word line WL6 is returned to Vaa. In the write mode, externally supplied data is transferred to the sense amplifier SA in the selected column and the data is written. In both the read mode and the write mode, the data read from the unit cell is rewritten as it is in the non-selected column.

According to this embodiment, the shared sense amplifier system is adopted and the column decoders are arranged on both sides of the cell arrays 1 and 2 with the sense amplifier circuit sandwiched therebetween. Therefore, as is apparent from FIG. 1, the column selection line CSL is
It is not necessary to dispose across the regions of the cell arrays 1 and 2, and for example, the same polycrystalline silicon film as the gates of the transistors of the column gates 6 and 7 can be formed continuously with the gates. In this case, only the bit lines BL and BBL need to be arranged on the cell array. The data lines DQ and BDQ can be formed outside the cell arrays 1 and 2 with the same metal wiring as the bit lines BL and BBL. Even if a metal wiring is used as the column selection line CSL, the total number of metal wiring layers is two. Therefore, the metal wiring process after forming the ferroelectric capacitor is minimized, and the thermal damage to the ferroelectric memory can be suppressed.

Also. As shown in FIG. 3, the sense amplifier circuit 3 requires that a sense amplifier activating transistor be arranged between each pair of bit lines BL and BBL, and that a reference voltage generation circuit 33 is further required. Therefore, the area is larger than that of a normal DRAM. In this embodiment, since the sense amplifier circuit is shared by the two cell arrays, the chip area can be effectively used.

The present invention is not limited to the above embodiment.
Although the TC parallel unit serial connection type cell array configuration has been described in the above-mentioned embodiment, it is similar to the ordinary DRAM.
1T / 1C cell configuration in which a memory cell is configured by a transistor and one capacitor, or bit lines BL and BBL
The present invention can be similarly applied to the case of a 2T / 2C cell configuration in which two memory cells driven by the same word line are arranged in one and one of them operates as a reference cell.

[0025]

As described above, according to the present invention, the sense amplifier circuit is shared by the two cell arrays to reduce the sense amplifier circuit area and effectively utilize the ferroelectric memory chip area. You can

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a ferroelectric memory to which the present invention is applied.

FIG. 2 is a diagram showing a specific configuration of a cell array of the same ferroelectric memory.

FIG. 3 is a diagram showing a specific configuration of a sense amplifier circuit of the same ferroelectric memory.

FIG. 4 is an operation timing chart of the ferroelectric memory.

[Explanation of symbols]

1, 2 ... Cell array, 3 ... Sense amplifier circuit, 4, 5 ...
Select gates, 6, 7 ... Column gates, 8, 9 ... Column decoders, 31 ... Sense amplifier main body, 32 ... Equalize circuit, 33 ... Reference voltage generating circuit, MCB ... Cell block,
T ... Cell transistor, C ... Ferroelectric capacitor, MC
... Unit cells (memory cells), BL, BBL ... Bit lines, PL, BPL ... Plate lines, WL ... Word lines, D
Q, BDQ ... Data line, CSL ... Column selection line.

Claims (4)

[Claims] 1. A word line and a bit line are arranged so as to intersect with each other, and a transistor driven by the word line and one end is connected to the bit line and the other end is connected to the plate line through the transistor at the intersection. A first and a second cell array in which memory cells each composed of a ferroelectric capacitor are arranged, and a memory cell selected between the first and the second cell arrays which is arranged between the first and the second cell arrays. A ferroelectric device, comprising: a sense amplifier circuit for detecting and amplifying data of a memory cell; and a column decoder arranged at an end of each of the first and second cell arrays opposite to the sense amplifier circuit. Body memory device. 2. The first and second cell arrays each have a memory cell configured by connecting both ends of a ferroelectric capacitor to a source and a drain of a transistor, and each memory cell is driven by a plurality of word lines. 2. The ferroelectric memory device according to claim 1, wherein the cell blocks are connected in series to form a cell block. 3. One of the two cell blocks adjacent to each other in the word line direction is connected to different plate lines, and the other end is connected to a pair of bit lines via block select transistors. Claim 2
A ferroelectric memory device according to claim 1. 4. The sense amplifier circuit includes a sense amplifier body including an activation transistor, an equalizer circuit for equalizing a pair of bit lines to a predetermined potential, and a reference voltage for generating one of the pair of bit lines. And a reference voltage generating circuit.
A ferroelectric memory device according to claim 1.