JP2007149964A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To permit the improvement of a power supplying capacity or the shortening of a rise-up time by reducing the power loss of a charge-pump boosting power supply circuit accommodated in a semiconductor integrated circuit to improve an efficiency. <P>SOLUTION: One end of a plurality of capacitors C1-C6 is respectively connected to nodes between stages of a plurality of stages of transfer gates TG1-TG7 connected in series, and two-phase clock signals ϕ1, ϕ2 are supplied from clock buffers to respective other ends of a plurality of stages of capacitors to charge the capacitors by the clock signals. Thereafter, operation of transferring a boosting voltage to a next stage by the transfer gates is repeated whereby the boosting power supply circuit is provided with a pattern layout. A capacitor group and a transfer gate group are divided into two parts respectively, and are arranged at both sides of clock buffer region 20 so as to pinch the region 20 while clock signals having different phases from each other are supplied to the arrangement regions 211, 212 of the capacitor groups divided into two groups. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a circuit layout having a charge pump type booster power supply circuit.

  A flash memory capable of batch erasing and writing requires a high voltage at the time of erasing / rewriting, and therefore includes a voltage boosting and step-down circuit (for example, a negative voltage generating circuit). The charge pump type voltage booster circuit includes a plurality of transfer gates, a plurality of capacitors, and a clock buffer for generating a two-phase clock signal. A plurality of capacitors are charged by the two-phase clock signal, and the charged charges of the charged capacitors are sequentially transferred to the subsequent stage through the transfer gate, thereby generating a boosted voltage. For example, a voltage boosting circuit that performs six-step boosting boosts a power supply voltage of, for example, 2.7V to 3.6V to about 12V.

  As the storage capacity of the flash memory increases, the capacity required for the power supply increases accordingly, so the scale of the power supply circuit naturally increases. As the scale of the power supply circuit is increased, the parasitic resistance and parasitic capacitance of the wiring are remarkably increased, and the efficiency of step-up / step-down is greatly reduced.

  When a charge pump type booster power supply circuit is laid out on a semiconductor integrated circuit, conventionally, it is laid out so that a clock buffer, a transfer gate group, and a capacitor group for generating a two-phase clock signal are arranged in a line. (Conventional example 1). In addition, two wirings connecting the clock buffer and the capacitor group and a plurality of wirings connecting the transfer gate group and the capacitor group are arranged in parallel to each other.

  Such a layout pattern is effective in reducing the pattern, but when the circuit scale increases, the parasitic resistance and parasitic capacitance of the wiring are greatly increased.

  Also, when a charge pump type booster power supply circuit is laid out on a semiconductor integrated circuit, conventionally, a first phase clock signal is supplied from among a clock buffer, a transfer gate group, and a capacitor group that generate a two-phase clock signal. The first capacitor group and the second capacitor group to which the second phase clock signal is supplied are laid out in a pattern arranged in a line (conventional example 2). In addition, a wiring connecting the clock buffer and the first capacitor group, a wiring connecting the clock buffer and the second capacitor group, and a plurality of wirings connecting the transfer gate group and the capacitor group are parallel to each other. Be placed.

  In this way, capacitors (odd-stage capacitors and even-stage capacitors) to which clock signals of the same phase are supplied are arranged together, and the wells that are the substrate regions are laid out in common so that the wells It is possible to reduce the parasitic component of the wiring by reducing or reducing the parasitic capacitance. However, when the circuit scale or the like is significantly increased, the parasitic components of the wiring are significantly increased, and the boosting efficiency is reduced, that is, the power loss of the booster circuit is unavoidable.

  Patent Document 1 discloses that a charge pump circuit formed of a plurality of MOS transistors in a semiconductor memory device is laid out so that the MOS transistors are connected by an aluminum wiring of the first layer, thereby reducing the chip size. It is disclosed.

  Further, Patent Document 2 discloses a charge pump circuit formed in a nonvolatile semiconductor memory device, in which the parasitic capacitance parasitic to the boosting capacitance of the charge pump circuit is short-circuited while the parasitic capacitance is in a floating state, thereby efficiently boosting the voltage. This is disclosed.

  Further, in Patent Document 3, a charge pump circuit formed in a semiconductor integrated circuit device is formed into a cell including a charge pump circuit for performing a charge pump operation according to an output signal of a frequency divider to generate a predetermined voltage. An active unit layout is disclosed.

Patent Document 4 discloses that in a semiconductor device, a unit electrode lead line and a counter electrode lead line are drawn in different directions to suppress parasitic capacitance of the capacitor element wiring.
Japanese Patent Laid-Open No. 11-68058 JP 2003-187586 A JP 2001-127254 A JP-A-9-3212228

  The present invention has been made to solve the above-described conventional problems, and it is possible to reduce resistance and capacitance parasitic to wiring of a built-in boost power supply circuit, reduce power loss of the boost power supply circuit, and increase efficiency. An object of the present invention is to provide a semiconductor integrated circuit capable of improving the power supply capability and shortening the startup time.

  The semiconductor integrated circuit according to the first aspect of the present invention includes a plurality of transfer gates connected in series, a plurality of capacitors each having one end connected to a node between the transfer gates, and the plurality of transfer gates. A clock buffer for supplying a two-phase clock signal to each other end of the capacitor of the stage, and charging the capacitor with the clock signal and then transferring the boosted voltage to the next stage with the transfer gates of the plurality of stages. Thus, in the semiconductor integrated circuit including the charge pump type booster power supply circuit that boosts the input voltage and outputs the boosted voltage, the booster power supply circuit is divided into the plurality of stages of capacitors and the plurality of stages of transfer gates. And having a pattern layout arranged on both sides of the arrangement area of the clock buffer, the plurality of stages divided into two Wherein the different phases of the clock signal each other is supplied to Yapashita.

  A semiconductor integrated circuit according to a second aspect of the present invention includes a plurality of transfer gates connected in series, a plurality of capacitors each having one end connected to a node between the transfer gates, and the plurality of transfer gates. A first-phase clock signal is supplied to each other end of the odd-numbered first capacitor group among the capacitors in the stage, and a second-phase clock signal is supplied to each other end of the second capacitor group in the even-numbered stage. And a step of boosting the input voltage of the first-stage transfer gate by repeating the operation of transferring the boosted voltage to the next stage through the plurality of transfer gates after charging the capacitor with the clock signal. In the semiconductor integrated circuit including a charge pump type boosting power supply circuit that outputs a voltage, the plurality of stages of transfer gates and the plurality of stages of capacitors are provided in the first key. Divided into a first group of odd-numbered transfer gates among the plurality of transfer gates and the second group of capacitor gates and a second number of second-stage transfer gates of the plurality of transfer gates. The first capacitor group is arranged in a row in the first region on one side of both sides of the clock buffer arrangement region. The arranged region and the region in which the first transfer gate group is arranged are arranged close to each other in parallel, and the first output terminal of the pair of output terminals of the clock buffer and the A plurality of wirings for connecting each one end of the first capacitor group and a plurality of wirings for connecting each other end of the first capacitor group and each one end of the first transfer gate group are arranged. And In the second region on the other side of the two sides of the buffer buffer arrangement region, the region where the second capacitor group is arranged in a row and the region where the second transfer gate group is arranged are parallel to each other And a plurality of wirings that respectively connect a second output end of the pair of output ends of the clock buffer and one end of the second capacitor group, and the second A plurality of wirings connecting the other end of each capacitor group and one end of the second transfer gate group are arranged, and the entire transfer of the first transfer gate group and the second transfer gate group is further performed. A plurality of wirings connecting the gates in series are arranged.

  According to the semiconductor integrated circuit of the present invention, the parasitic resistance and capacitance in the wiring of the built-in boost power supply circuit are reduced, the power supply capability is improved by increasing the efficiency of the boost power supply circuit, the layout is reduced, and the voltage is raised. Time can be shortened, and shortening and speeding up of the operation start time of the entire system circuit can be expected.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
FIG. 1 shows an equivalent circuit of a charge pump type booster power supply circuit built in the flash memory according to the first embodiment of the semiconductor integrated circuit of the present invention. This boost power supply circuit generates a write voltage and / or an erase voltage. In the step-up power supply circuit shown in FIG. 1, each end of a plurality of stages of capacitors is connected to an inter-stage node of a plurality of stages of transfer gate transistors (hereinafter referred to as transfer gates) connected in series, and is generated by a clock buffer. A two-phase clock signal is supplied to each other end of the plurality of stages of capacitors. FIG. 1 illustrates a boosting power supply circuit in which seven stages of transfer gates are provided and six-stage boosting is performed. However, the present invention is not limited to this, and the present invention can be implemented to perform arbitrary step-up voltage.

  A specific configuration will be described below. The boosting power supply circuit of FIG. 1 includes seven stages of transfer gates TG1 to TG7 connected in series, six stages of capacitors C1 to C6 each having one end connected to an interstage node of the seven stages of transfer gates, A clock buffer 10 composed of, for example, three inverters for supplying two-phase clock signals φ1 and φ2 to the other ends of the capacitors C1 to C6. The first-phase clock signal φ1 is supplied to the other ends of the odd-numbered first capacitors C1, C3, and C5, and the second-phase clock signals φ1 are supplied to the other ends of the even-numbered second capacitors C2, C4, and C6. A clock signal φ2 is supplied. Of the seven transfer gates TG1 to TG7, the first transfer gate TG1 transfers the input voltage Vi to the next stage, and the second and subsequent transfer gates sequentially transfer the boosted voltage. Each transfer gate is, for example, an I type NMOSFET whose threshold voltage is close to zero.

  In the boosting power supply circuit having the above configuration, after the odd-numbered first capacitors C1, C3, C5 and the even-numbered second capacitors C2, C4, C6 are alternately charged by the two-phase clock signals φ1, φ2. By repeating the operation of sequentially transferring the capacitor voltage to the next stage via the transfer gates TG2 to TG7, the input voltage Vi is boosted, and the boosted voltage Vo is output from the transfer gate TG7 at the final stage.

  FIG. 2 is a plan view showing an example of a pattern layout of the boost power supply circuit of FIG. Capacitors C1 to C6 and transfer gates TG1 to TG6 are respectively divided into two parts on both sides of the clock buffer region 20 for generating the two-phase clock signals φ1 and φ2. In this case, an odd-stage first capacitor C1, C3, C5 arrangement region 211 and an odd-stage first transfer gate TG1, TG3, TG5 arrangement region 221 to which the first-phase clock signal φ1 is supplied, Divided into an even-stage second capacitor C2, C4, C6 arrangement region 212 and even-stage second transfer gates TG2, TG4, TG6 arrangement region 222 to which the second-phase clock signal φ2 is supplied. ing. In other words, the clock buffer area 20 is arranged between the arrangement areas 211 and 212 of the two capacitor groups to which clock signals having different phases are supplied. Note that the transfer gate TG7 at the final stage is arranged in or near the clock buffer region 20 in this example.

  This will be specifically described below. In a first region (right region in this example) on one side of both sides of the clock buffer region 20, a capacitor placement region 211 in which first capacitors C1, C3, and C5 are placed in a row, The transfer gate arrangement region 221 in which the transfer gates TG1, TG3, and TG5 are arranged is arranged as close as possible to each other in a parallel state. In the drawing, the transfer gate arrangement region 221 is shown adjacent to the upper side of the capacitor arrangement region 211 in the drawing, but the transfer gate arrangement region 221 may be arranged adjacent to the lower side of the capacitor arrangement region 211 in the drawing. A plurality of (three in this example) connecting the first output terminal (φ1 output terminal) of the pair of output terminals of the clock buffer region 20 and one end of each of the first capacitors C1, C3, and C5. Wirings 231 are arranged in parallel, and a plurality of (three in this example) connecting the other ends of the first capacitors C1, C3, C5 and one ends of the first transfer gates TG1, TG3, TG5. Wirings 241, 243, and 245 are arranged in parallel.

  Similarly to the above, in the second region on the other side of the clock buffer region 20 (the left region in this example), the capacitor placement region 212 in which the second capacitors C2, C4, C6 are placed in a row, and the second The transfer gate arrangement regions 222 in which the transfer gates TG2, TG4, and TG6 are arranged are arranged as close as possible in parallel with each other. A plurality (three in this example) of wirings 232 connecting the second output terminal (φ2 output terminal) of the clock buffer region 20 and one end of the second capacitor group C2, C4, C6 are arranged. A plurality of (three in this example) wirings 242, 244, 246 connecting the other ends of the second capacitors C2, C4, C6 and one ends of the second transfer gates TG2, TG4, TG6 are provided. Is arranged.

  Further, a plurality of wirings 25 for sequentially connecting the whole of the first transfer gates TG1, TG3, TG5, the second transfer gates TG2, TG4, TG6 and the final transfer gate TG7 in series are provided in the transfer gate arrangement region. They are arranged in parallel in the vicinity of the sides of 221 and 222 or on the transfer gate arrangement regions 221 and 222. That is, the other end of the transfer gate TG1 and one end of the transfer gate TG2 are connected to each other, and the other end of the transfer gate YG2 and one end of the transfer gate TG3 are connected to each other. One transfer gate is connected to each other between the first transfer gates TG1, TG3, TG5 in the stages and the second transfer gates TG2, TG4, TG6 in the even stages.

  In this case, in the right region of the clock buffer region 20, each odd-numbered capacitor is moved away from the clock buffer region 20 in the order of increasing odd numbers (in order of capacitors C1, C3, C5), and each odd-numbered transfer is performed. The gates are arranged so as to move away from the clock buffer region 20 in the order of increasing odd numbers (in the order of TG1, TG3, and TG5). On the other hand, in the left region of the clock buffer region 20, each even-numbered capacitor approaches the clock buffer region 20 in the order of increasing even-numbered numbers (in order of C2, C4, and C6). Are arranged so as to approach the clock buffer region 20 in order of increasing even numbers (in the order of TG2, TG4, TG6).

  According to such an arrangement, the wiring distance between the transfer gates TG1 and TG2, the wiring distance between the transfer gates TG2 and TG3, the wiring distance between the transfer gates TG3 and TG4, and the wiring between the transfer gates TG4 and TG5. The distances are almost equal.

  According to the configuration of the first embodiment described above, capacitors (capacitors C1, C3, C5) and (capacitors C2, C4, C6) to which clock signals of the same phase are supplied are arranged together, and the respective substrates are arranged. By laying out the common wells as regions, it is possible to reduce the parasitic capacitance of the wiring by reducing and reducing the parasitic capacitance of the wells.

  In addition, the clock buffer region 20 is arranged between the two capacitor arrangement regions 211 and 212 to which clock signals having different phases are supplied, and two transfer gate arrangement regions corresponding to the two capacitor arrangement regions 211 and 212, respectively. 221 and 222 are arranged as close as possible.

  As a result, the distance from the clock buffer region 20 to the farthest part in the capacitor placement regions 211 and 212 and the wiring distance from each transfer gate to the capacitor placement region 211 or 212 can be kept to a minimum (shortest distance). Thus, it is possible to minimize the increase in parasitic components due to the increase in circuit scale.

  Therefore, even when the scale of the boost power supply circuit is significantly increased, an increase in the parasitic component of the circuit wiring of the boost power supply circuit section can be suppressed as compared with the conventional case. An increase can be avoided. As a result, it is possible to reduce the power loss of the boosting power supply circuit unit and increase the efficiency, improve the power supply capability and shorten the startup time.

1 is an equivalent circuit diagram of a charge pump type booster power supply circuit built in a flash memory according to a first embodiment of a semiconductor integrated circuit of the present invention; FIG. 2 is a plan view showing an example of a pattern layout of the charge pump type booster power supply circuit of FIG. 1.

Explanation of symbols

TG1 to TG7: transfer gate, C1 to C6: capacitor, φ1, φ2: two-phase clock signal, Vi: input voltage, Vo: boosted voltage, 20: clock buffer region, 221: odd-stage capacitor placement region, 212 ... even-numbered capacitor placement region, 221 ... odd-numbered transfer gate placement region, 222 ... even-numbered transfer gate placement region, 231, 232, 241-246, 25 ... wiring.

Claims (5)

A plurality of transfer gates connected in series, a plurality of capacitors each having one end connected to an inter-stage node of the plurality of transfer gates, and a two-phase clock signal at each other end of the plurality of capacitors A clock buffer for supplying the voltage, and after charging the capacitor by the clock signal, by repeating the operation of transferring the boosted voltage to the next stage by the plurality of transfer gates, boosting the input voltage and outputting the boosted voltage In a semiconductor integrated circuit incorporating a charge pump type boosting power supply circuit,
The step-up power supply circuit has a pattern layout in which the plurality of stages of capacitors and the plurality of stages of transfer gates are respectively divided and arranged on both sides of the arrangement area of the clock buffer,
A semiconductor integrated circuit characterized in that clock signals having different phases are supplied to the two-stage divided capacitors. A plurality of transfer gates connected in series; a plurality of capacitors each having one end connected to an inter-stage node of the plurality of transfer gates; and an odd-numbered first capacitor of the plurality of capacitors A clock buffer for supplying a first phase clock signal to each other end of the group and supplying a second phase clock signal to each other end of the second capacitor group in an even number of stages, and the capacitor using the clock signal Built-in charge-pump booster power supply circuit that boosts the input voltage of the first-stage transfer gate and outputs the boosted voltage by repeating the operation of transferring the boosted voltage to the next stage through the multiple-stage transfer gate after charging In the semiconductor integrated circuit,
The plurality of stages of transfer gates and the plurality of stages of capacitors include the first capacitor group and the first stage of the odd number of the plurality of stages of transfer gates, the second capacitor group, and the plurality of stages. The transfer gates are divided into two even-numbered second transfer gates and are arranged on both sides of the clock buffer arrangement region.
In a first region on one side of both sides of the clock buffer arrangement region, a region where the first capacitor group is arranged in a row and a region where the first transfer gate group is arranged are mutually connected. A plurality of wirings arranged close to each other in parallel and connecting a first output terminal of the pair of output terminals of the clock buffer and one end of each of the first capacitor groups; and A plurality of wirings connecting each other end of the first capacitor group and each one end of the first transfer gate group are arranged,
In the second region on the other side of both sides of the clock buffer arrangement region, the region where the second capacitor group is arranged in a row and the region where the second transfer gate group is arranged are mutually connected. A plurality of wirings arranged close to each other in parallel and connecting a second output terminal of the pair of output terminals of the clock buffer and each one end of the second capacitor group; and A plurality of wirings connecting each other end of the second capacitor group and each one end of the second transfer gate group are arranged,
Further, a plurality of wirings for connecting the entire transfer gates of the first transfer gate group and the second transfer gate group in series are arranged. A semiconductor integrated circuit, wherein:   3. The semiconductor according to claim 2, wherein a wiring connecting the other end of the capacitor and the transfer gate is formed in an orthogonal direction with respect to a wiring connecting the clock buffer and one end of the capacitor. Integrated circuit. In the first region, each capacitor of the first capacitor group moves away from the clock buffer in order of increasing odd number, and each transfer gate of the first transfer gate group increases in order of increasing odd number. Placed away from the clock buffer,
In the second region, each capacitor in the second capacitor group approaches the clock buffer in order of increasing even number, and each transfer gate of the second transfer gate group in the order of increasing even number. 4. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is arranged so as to be close to   5. The charge pump type booster power supply circuit is built in a flash memory, and a write voltage and / or an erase voltage is generated from the booster power supply circuit. 6. Semiconductor integrated circuit.

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