JP2007149828A - Substrate for mounting electronic component - Google Patents

Substrate for mounting electronic component Download PDF

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JP2007149828A
JP2007149828A JP2005340124A JP2005340124A JP2007149828A JP 2007149828 A JP2007149828 A JP 2007149828A JP 2005340124 A JP2005340124 A JP 2005340124A JP 2005340124 A JP2005340124 A JP 2005340124A JP 2007149828 A JP2007149828 A JP 2007149828A
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electronic component
lands
substrate
land
bump bonding
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Hide Hamada
秀 濱田
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Fujifilm Corp
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Fujifilm Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

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  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for mounting an electronic component wherein the electronic component having a surface that can be appropriately soldered having a plurality of solder bumps arranged in a two-dimensional manner. <P>SOLUTION: The substrate 10 for bonding an electronic component is provided with a plane, wherein a plurality of solder bump bonding lands 12 are arranged in specified region in a two-dimensional manner, and the solder bump bonding lands 12 has lands of different sizes. For example, the solder bump bonding lands are those for bonding electronic components which have surfaces, wherein a plurality of solder bumps are arranged in a two-dimensional manner. In addition, the electronic component is a chip, of which are bump-connected in flip chip, or a semiconductor package with a BGA (Ball Grid Array) structure or a CSP (Chip Size Package) structure, for example. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、電子部品実装用基板に係り、特に複数のはんだバンプが二次元的に配設された面を有する電子部品が実装される基板に関する。   The present invention relates to an electronic component mounting substrate, and more particularly to a substrate on which an electronic component having a surface on which a plurality of solder bumps are two-dimensionally arranged is mounted.

従来、複数のはんだバンプ（はんだボールと呼ばれることもある）が二次元的に配置された面を有する電子部品として、フリップチップにおいてバンプ接続されるチップや、ＢＧＡ（Ball Grid Array）や、はんだバンプがＢＧＡよりもさらに狭ピッチで配置されたＣＳＰ（Chip Size Package）などが知られている（特許文献１）。なお、バンプ形成のための技術としてはＣ４（controlled collapsed chip connection）などが知られている。   Conventionally, as an electronic component having a surface in which a plurality of solder bumps (sometimes referred to as solder balls) are two-dimensionally arranged, a chip that is bump-connected in a flip chip, a BGA (Ball Grid Array), or a solder bump There is known a CSP (Chip Size Package) or the like arranged at a narrower pitch than BGA (Patent Document 1). As a technique for forming the bump, C4 (controlled collapsed chip connection) is known.

複数のはんだバンプが二次元的に配置された面を有する電子部品は、一般的に、リフローと呼ばれる工程を経て基板表面に接合される。リフローとは、電子部品のはんだバンプと基板表面に設けられたランド（通常、基板表面にクリームはんだにより印刷される）とを接触させ、全体的に（あるいはスポット的）に基板を加熱し、これによりバンプ等を溶融させてはんだ付け（接合）する工程をいう。   An electronic component having a surface on which a plurality of solder bumps are two-dimensionally arranged is generally bonded to the substrate surface through a process called reflow. In reflow, solder bumps of electronic components are contacted with lands (usually printed with cream solder on the substrate surface) on the substrate surface, and the substrate is heated as a whole (or spot-like). The process of melting and bumping bumps etc. and soldering (joining).

はんだバンプと基板との平坦度（コプラナリティ）（あるいはバンプ高さの平坦度）が保たれている状態で加熱される限り、すべてのはんだバンプにおいて適切にはんだ付けされるはずであるが、実際には、リフロー時の加熱（熱膨張）等による基板の反り（あるいははんだバンプ高さの不均一）などに起因して、適切にはんだ付けされない（接合不良）はんだバンプも存在する。   As long as the solder bumps are heated with the flatness (coplanarity) (or the flatness of the bump height) of the board maintained, all solder bumps should be properly soldered. There are also solder bumps that are not properly soldered (bonding failure) due to substrate warpage (or uneven solder bump height) due to heating (thermal expansion) or the like during reflow.

本出願の発明者は、接合不良のはんだバンプが中央または中央付近に比べて周囲に多い点に着目した。そして、本出願の発明者は、周囲における接合不良は主に基板の反りに起因するものであり、周囲のランドサイズを中央または中央付近のランドサイズよりも大きくすれば、周囲のランドに対するはんだバンプ溶融時の表面張力（セルフアライメント効果）も大きくなって、反った基板を平坦に戻そうとする力が作用するから、周囲においても良好なはんだ付けを実現できるとの着想を得た。
特開２００１−６８５９４号公報 The inventor of the present application has focused on the fact that there are more solder bumps with poor bonding near the center or near the center. The inventors of the present application have found that the bonding failure in the periphery is mainly caused by the warp of the substrate. If the size of the surrounding land is larger than the center or the land size near the center, the solder bumps to the surrounding land The surface tension (self-alignment effect) at the time of melting also increases, and a force acts to return the warped substrate to a flat surface. Therefore, the idea that good soldering can be realized even in the surroundings.
JP 2001-68594 A

本発明の課題は、複数のはんだバンプが二次元的に配設された面を有する電子部品の各はんだバンプにおける適切なはんだ付けを実現するための技術を提供することにある。   The subject of this invention is providing the technique for implement | achieving appropriate soldering in each solder bump of the electronic component which has the surface where the several solder bump was arrange | positioned two-dimensionally.

本発明は、上記課題を解決するためになされたものであり、次の構成を採る。   The present invention has been made to solve the above-described problems, and adopts the following configuration.

その表面一定領域に二次元的に配置された複数のはんだバンプ接合用ランドを有する基板であって、前記複数のはんだバンプ接合用ランドは異なるサイズのランドを含むことを特徴とする電子部品実装用基板。   A substrate having a plurality of solder bump bonding lands arranged two-dimensionally in a certain area of the surface, wherein the plurality of solder bump bonding lands include lands of different sizes. substrate.

本発明によれば、はんだバンプ接合用ランドは異なるサイズのランドを含むから、比較的大サイズのランドに対するはんだバンプ溶融時の表面張力（セルフアライメント効果）が大きくなる。すなわち、この基板に実装される電子部品の実装精度を高めることが可能となる。   According to the present invention, since the solder bump bonding lands include lands having different sizes, the surface tension (self-alignment effect) at the time of melting the solder bumps with respect to the relatively large lands is increased. That is, it is possible to increase the mounting accuracy of the electronic component mounted on the substrate.

上記電子部品実装用基板においては、例えば、前記複数のはんだバンプ接合用ランドは、複数のはんだバンプが二次元的に配置された面を有する電子部品の接合用ランドである。   In the electronic component mounting substrate, for example, the plurality of solder bump bonding lands are bonding lands for electronic components having a surface on which a plurality of solder bumps are two-dimensionally arranged.

これは、バンプ接合用ランドの例示である。このような電子部品としては、フリップチップにおいてバンプ接続されるチップ、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）またはＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）構造の半導体パッケージなどが考えられる。要は、複数のはんだバンプが二次元的に配置された面を有する電子部品であればよい。   This is an example of a land for bump bonding. As such an electronic component, a chip that is bump-connected in a flip chip, a semiconductor package having a BGA (Ball Grid Array) or CSP (Chip Size Package) structure, and the like are conceivable. In short, any electronic component having a surface on which a plurality of solder bumps are two-dimensionally arranged may be used.

上記電子部品実装用基板においては、例えば、前記複数のはんだバンプ接合用ランドを格子状に配置したり、あるいは、あるランド列を構成する各ランドがこれに隣接するランド列を構成する二つのランドの中間に位置するように、前記複数のはんだバンプ接合用ランドを配置することが考えられる。   In the electronic component mounting board, for example, the plurality of solder bump bonding lands are arranged in a grid pattern, or each land constituting a certain land row forms two land rows adjacent thereto. It is conceivable that the plurality of solder bump bonding lands are arranged so as to be located in the middle of each other.

これは、はんだバンプ接合用ランドの配置例である。   This is an arrangement example of lands for solder bump bonding.

上記電子部品実装用基板においては、例えば、前記表面一定領域の中心から周囲に向かうにつれてバンプ接合用ランドのサイズを大きくする。   In the electronic component mounting substrate, for example, the size of the bump bonding land is increased from the center of the fixed surface region toward the periphery.

このように周囲のランドサイズを中央または中央付近のランドサイズよりも大きくすれば、周囲のバンプ接合用ランドに対するはんだバンプ溶融時の表面張力（セルフアライメント効果）も大きくなって、反った基板を平坦に戻そうとする力が作用するから、周囲においても良好なはんだ付けを実現することが可能となる。   If the surrounding land size is made larger than the center land size or the center land size in this way, the surface tension (self-alignment effect) when the solder bump melts against the surrounding bump bonding land also increases, and the warped board becomes flat. Since a force for returning to the position acts, good soldering can be realized even in the surroundings.

上記電子部品実装用基板においては、例えば、前記表面一定領域の周囲に比較的大きいサイズのバンプ接合用ランドを配置する。   In the electronic component mounting substrate, for example, bump bonding lands having a relatively large size are arranged around the constant surface area.

このように周囲に比較的大きいサイズのバンプ接合用ランドを配置すれば、周囲のバンプ接合用ランドに対するはんだバンプ溶融時の表面張力（セルフアライメント効果）も大きくなって、反った基板を平坦に戻そうとする力が作用するから、周囲においても良好なはんだ付けを実現することが可能となる。   If a relatively large size bump bonding land is arranged in this way, the surface tension (self-alignment effect) when the solder bump melts against the surrounding bump bonding land also increases, and the warped board is returned to a flat surface. Since the force to act acts, it becomes possible to implement | achieve favorable soldering also in the circumference | surroundings.

本発明によれば、複数のはんだバンプが二次元的に配設された面を有する電子部品の各はんだバンプにおける適切なはんだ付け（接合）が可能となる。   ADVANTAGE OF THE INVENTION According to this invention, the appropriate soldering (joining) in each solder bump of the electronic component which has the surface where the several solder bump was arrange | positioned two-dimensionally is attained.

以下、本発明の一実施形態である電子部品実装用基板について図面を参照しながら説明する。   Hereinafter, an electronic component mounting substrate according to an embodiment of the present invention will be described with reference to the drawings.

図１は、本発明の一実施形態である電子部品実装用基板１０を説明するための図（平面図）である。図２は、図１に示す基板１０に電子部品２０を実装してＡ−Ａ´で切断した断面を表す断面図である。   FIG. 1 is a diagram (plan view) for explaining an electronic component mounting board 10 according to an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a cross section obtained by mounting the electronic component 20 on the substrate 10 illustrated in FIG.

本実施形態の電子部品実装用基板１０は、図２に示すように、その表面１０ａに、複数のはんだバンプ（以下単にバンプともいう）２１が二次元的に配置された面２０ａを有する電子部品２０が実装されるフレキシブル基板等の各種基板である。図１に示すように、電子部品実装用基板１０は、その表面１０ａ一定領域１１に二次元的に配置された複数のはんだバンプ接合用ランド（以下単にランドともいう）１２を備えている。この複数のランド１２は、異なるサイズのランドを含んでいる（図１では、三つのサイズのランド１２ａ、１２ｂ、１２ｃを例示）。なお、三つのサイズに限らず、図５に示すように、二つのサイズのランド１２ａ、１２ｃを配置することも考えられるし、四つ以上のサイズのランドを配置することも考えられる。   As shown in FIG. 2, the electronic component mounting substrate 10 of the present embodiment has an electronic component having a surface 20 a on which a plurality of solder bumps (hereinafter also simply referred to as bumps) 21 are two-dimensionally arranged. 20 are various substrates such as a flexible substrate on which 20 is mounted. As shown in FIG. 1, the electronic component mounting board 10 includes a plurality of solder bump bonding lands (hereinafter also simply referred to as lands) 12 two-dimensionally arranged on the surface 10 a constant region 11. The plurality of lands 12 include lands having different sizes (in FIG. 1, lands 12a, 12b, and 12c having three sizes are illustrated). In addition, not only three sizes but also two sized lands 12a and 12c may be arranged as shown in FIG. 5, and four or more sized lands may be arranged.

複数のランド１２は、電子部品２０の各バンプ２１が接合される領域であって、基板表面１０ａにクリームはんだで印刷されるか、あるいは銅箔等の金属材料により形成される。   The plurality of lands 12 are regions where the bumps 21 of the electronic component 20 are joined, and are printed on the substrate surface 10a with cream solder or formed of a metal material such as copper foil.

ランド１２の配置パターンについては各種のパターンが考えられる。   Various patterns can be considered for the arrangement pattern of the lands 12.

例えば、図１に示すように、表面１０ａ一定領域１１の周囲にのみ、各ランド１２を配置することが考えられる。   For example, as shown in FIG. 1, it is conceivable that each land 12 is arranged only around the constant region 11 of the surface 10a.

あるいは、図３、図５に示すように、格子状に配置することも考えられる。   Alternatively, as shown in FIG. 3 and FIG.

あるいは、図４、図６に示すように、あるランド列を構成する各ランド（図４では二つのランド１２ｂを例示、図６では二つのランド１２ａを例示）がこれに隣接するランド列を構成する二つのランド（図４、図６では三つのランド１２ｃを例示）の中間に位置するように、各ランド１２を配置することも考えられる。   Alternatively, as shown in FIGS. 4 and 6, each land constituting a certain land row (in FIG. 4 exemplifies two lands 12 b and in FIG. 6 exemplifies two lands 12 a) constitutes a land row adjacent thereto. It is also conceivable to arrange each land 12 so as to be located between two lands (three lands 12c are illustrated in FIGS. 4 and 6).

また、図１に示すように、各ランド１２をランド１２ａ、１２ｂ、１２ｃのように繰り返して配置することも考えられるし、図３、図５に示すように、表面１０ａ一定領域１１の中心から周囲に向かうにつれてランド１２のサイズを大きくすることも考えられる。   Further, as shown in FIG. 1, it is conceivable to repeatedly arrange each land 12 like lands 12a, 12b, and 12c, and from the center of the surface 10a constant region 11 as shown in FIGS. It is conceivable to increase the size of the land 12 toward the periphery.

なお、各図において、各ランド１２の配置間隔は、各バンプ２１の配置間隔と等しくなっている。   In each drawing, the arrangement interval of each land 12 is equal to the arrangement interval of each bump 21.

電子部品２０としては、複数のはんだバンプ（はんだボールと呼ばれることもある）２１が二次元的に配設された面２０ａを有する部品、例えば、フリップチップにおいてバンプ接続されるチップや、ＢＧＡ（Ball Grid Array）構造の半導体パッケージや、はんだバンプがＢＧＡよりもさらに狭ピッチで配設された面を有するＣＳＰ（Chip Size Package）構造の半導体パッケージなどがある。   As the electronic component 20, a component having a surface 20a in which a plurality of solder bumps (sometimes referred to as solder balls) 21 are two-dimensionally arranged, for example, a chip to be bump-connected in a flip chip, BGA (Ball There are a semiconductor package having a grid array (CSP) structure, a semiconductor package having a CSP (Chip Size Package) structure having a surface on which solder bumps are arranged at a narrower pitch than the BGA.

バンプ２１の配置パターンについては各種のパターンが考えられる。   Various patterns can be considered for the arrangement pattern of the bumps 21.

一般的には、ランド１２の配置パターンと同一または類似のパターンで配置されている。   Generally, it is arranged in the same or similar pattern as the arrangement pattern of the lands 12.

次に、以上のように構成される電子部品実装用基板１０に電子部品２０を実装する工程（リフロー）について簡単に説明する。   Next, a process (reflow) of mounting the electronic component 20 on the electronic component mounting board 10 configured as described above will be briefly described.

まず、電子部品２０の各バンプ２１と基板表面１０ａ一部領域１１に配置されたランド１２とを接触させて、全体的に（あるいはスポット的に）基板１０を加熱し、これによりバンプ２１等を溶融させてはんだ付け（接合）する。これにより電子部品２０が実装される。   First, the bumps 21 of the electronic component 20 are brought into contact with the lands 12 arranged in the partial region 11 of the substrate surface 10a to heat the substrate 10 as a whole (or in a spot manner). Melt and solder (join). Thereby, the electronic component 20 is mounted.

以上説明したように、本実施形態の電子部品実装基板１０によれば、周囲のランド１２のランドサイズを比較的大きくしたので、周囲のランド１２に対するはんだバンプ溶融時の表面張力（セルフアライメント効果）も大きくなって、反った基板を平坦に戻そうとする力が作用するから、周囲においても良好なはんだ付けを実現することが可能となる。   As described above, according to the electronic component mounting substrate 10 of the present embodiment, since the land size of the surrounding lands 12 is relatively large, the surface tension at the time of melting the solder bumps on the surrounding lands 12 (self-alignment effect) Since the force to return the warped substrate to a flat surface acts, good soldering can be realized even in the surroundings.

なお、ランド１２は、電子部品２０が有するはんだバンプ２１と同数設けてもよいし、あるいは必要なバンプ２１に対応した数のみ設けてもよい。   Note that the same number of lands 12 as the solder bumps 21 included in the electronic component 20 may be provided, or only the number corresponding to the necessary bumps 21 may be provided.

次に変形例について説明する。   Next, a modified example will be described.

上記実施形態においては、比較的大きいサイズのバンプ１２を周囲に配置するように説明したが本発明はこれに限定されない。例えば、図３においては、表面１０ａ一定領域１１の中心から周囲に向かうにつれてランド１２のサイズを大きくしてあるが、このような規則によらずに、各サイズのバンプをランダムに配置するようにしてもよい。   In the above-described embodiment, the description has been made so that the relatively large size bumps 12 are arranged around the periphery, but the present invention is not limited to this. For example, in FIG. 3, the size of the land 12 is increased from the center of the constant area 11 of the surface 10a toward the periphery, but bumps of each size are arranged randomly without depending on such rules. May be.

このようにすれば、比較的大サイズのランド１２ｂ、１２ｃに対するはんだバンプ溶融時の表面張力（セルフアライメント効果）が大きくなる。すなわち、この基板１０に実装される電子部品２０の実装精度を高めることが可能となる。   By doing so, the surface tension (self-alignment effect) at the time of melting the solder bumps with respect to the relatively large sized lands 12b and 12c is increased. That is, the mounting accuracy of the electronic component 20 mounted on the substrate 10 can be increased.

上記実施形態はあらゆる点で単なる例示にすぎない。これらの記載によって本発明は限定的に解釈されるものではない。本発明はその精神または主要な特徴から逸脱することなく他の様々な形で実施することができる。   The above embodiment is merely an example in all respects. The present invention is not construed as being limited to these descriptions. The present invention can be implemented in various other forms without departing from the spirit or main features thereof.

本発明の一実施形態である電子部品実装用基板を説明するための平面図である。It is a top view for demonstrating the electronic component mounting board | substrate which is one Embodiment of this invention. 図１に示す基板１０に電子部品２０を実装してＡ−Ａ´で切断した断面を表す断面図である。It is sectional drawing showing the cross section which mounted the electronic component 20 in the board | substrate 10 shown in FIG. 1, and cut | disconnected by AA '. 基板１０におけるランドの配置例を説明するための図である。FIG. 4 is a diagram for explaining an example of land arrangement on a substrate 10. 基板１０におけるランドの配置例を説明するための図である。FIG. 4 is a diagram for explaining an example of land arrangement on a substrate 10. 基板１０におけるランドの配置例を説明するための図である。FIG. 4 is a diagram for explaining an example of land arrangement on a substrate 10. 基板１０におけるランドの配置例を説明するための図である。FIG. 4 is a diagram for explaining an example of land arrangement on a substrate 10.

符号の説明Explanation of symbols

１０…電子部品実装用基板、１０ａ…表面、１１…実装領域、１２…ランド、２０…電子部品、２０ａ…面、２１…バンプ DESCRIPTION OF SYMBOLS 10 ... Board | substrate for electronic component mounting, 10a ... Surface, 11 ... Mounting area | region, 12 ... Land, 20 ... Electronic component, 20a ... Surface, 21 ... Bump

Claims (7)

その表面一定領域に二次元的に配置された複数のはんだバンプ接合用ランドを有する基板であって、
前記複数のはんだバンプ接合用ランドは異なるサイズのランドを含むことを特徴とする電子部品実装用基板。 A substrate having a plurality of solder bump bonding lands arranged two-dimensionally on a constant surface area thereof,
The electronic component mounting board, wherein the plurality of solder bump bonding lands include lands of different sizes. 前記複数のはんだバンプ接合用ランドは、複数のはんだバンプが二次元的に配置された面を有する電子部品の接合用ランドであることを特徴とする請求項１に記載の電子部品実装用基板。   2. The electronic component mounting board according to claim 1, wherein the plurality of solder bump bonding lands are electronic component bonding lands having a surface on which a plurality of solder bumps are two-dimensionally arranged. 前記電子部品は、フリップチップにおいてバンプ接続されるチップ、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）またはＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）構造の半導体パッケージであることを特徴とする請求項２に記載の電子部品実装用基板。   3. The electronic component mounting substrate according to claim 2, wherein the electronic component is a semiconductor package having a flip-chip chip connection, a BGA (Ball Grid Array), or a CSP (Chip Size Package) structure. 前記複数のはんだバンプ接合用ランドを格子状に配置したことを特徴とする請求項２または３に記載の電子部品実装用基板。   4. The electronic component mounting board according to claim 2, wherein the plurality of solder bump bonding lands are arranged in a grid pattern. あるランド列を構成する各ランドがこれに隣接するランド列を構成する二つのランドの中間に位置するように、前記複数のはんだバンプ接合用ランドを配置したことを特徴とする請求項１から３のいずれかに記載の電子部品実装用基板。   4. The plurality of solder bump bonding lands are arranged so that each land constituting a land row is positioned between two lands constituting a land row adjacent thereto. The electronic component mounting board according to any one of the above. 前記表面一定領域の中心から周囲に向かうにつれてバンプ接合用ランドのサイズを大きくしたことを特徴とする請求項１から５のいずれかに記載の電子部品実装用基板。   6. The electronic component mounting board according to claim 1, wherein a size of the bump bonding land is increased from the center of the constant surface region toward the periphery. 前記表面一定領域の周囲に比較的大きいサイズのバンプ接合用ランドを配置したことを特徴とする請求項１から５のいずれかに記載の電子部品実装用基板。   6. The electronic component mounting board according to claim 1, wherein bump bonding lands having a relatively large size are arranged around the constant surface area.
JP2005340124A 2005-11-25 2005-11-25 Substrate for mounting electronic component Abandoned JP2007149828A (en)

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Publication number Priority date Publication date Assignee Title
CN104425415A (en) * 2013-08-27 2015-03-18 力领科技股份有限公司 Chip lug structure
US9414488B2 (en) 2012-02-17 2016-08-09 Canon Kabushiki Kaisha Circuit board for mounting electronic components
CN108878296A (en) * 2018-06-27 2018-11-23 华中科技大学 A kind of preparation method of three-dimensional micro convex point
US10797012B2 (en) 2017-08-25 2020-10-06 Dialog Semiconductor (Uk) Limited Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices

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JPS6273639A (en) * 1985-09-26 1987-04-04 Fujitsu Ltd Method of mounting semiconductor chip
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9414488B2 (en) 2012-02-17 2016-08-09 Canon Kabushiki Kaisha Circuit board for mounting electronic components
CN104425415A (en) * 2013-08-27 2015-03-18 力领科技股份有限公司 Chip lug structure
US10797012B2 (en) 2017-08-25 2020-10-06 Dialog Semiconductor (Uk) Limited Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices
US11495567B2 (en) 2017-08-25 2022-11-08 Dialog Semiconductor (Uk) Limited Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices
CN108878296A (en) * 2018-06-27 2018-11-23 华中科技大学 A kind of preparation method of three-dimensional micro convex point

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