JP2007142757A - Differential amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential amplifier circuit capable of conducting normal operation even in a low supply voltage with little gain variation due to temperature. <P>SOLUTION: The differential amplifier circuit comprises a differential amplifier 5, a temperature fluctuation detector 2, a comparison current generator 3, and a current adjuster 4. The gain of the differential amplifier 5 is controlled according to current of a PMOS51 controlled by an adjustment signal COM. The temperature fluctuation detector 2 has a differential circuit of a configuration identical to the differential amplifier 5, and outputs a current difference Igm generated according to temperature fluctuation during biasing two input sides of the differential circuit with a minute potential difference V1-V2. The comparison current generator 3 generates a reference current Irf for comparison according to a minute potential difference V3=V1-V2. The current adjuster 4 outputs the adjustment signal COM so that the value of the current difference Igm output from the temperature fluctuation detector 2 becomes same as the one of the reference current Irf generated in the comparison current generator 3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a differential amplifier circuit with little gain fluctuation due to temperature, and particularly to a reduction in power supply voltage thereof.

JP 2001-339259 A JP 2000-174568 A

FIG. 2 is a configuration diagram of a conventional differential amplifier circuit described in Patent Document 1. In FIG.
The differential amplifier circuit includes transistors MN20 and MN21 that form a differential pair, transistors MN22 and MN23 that form a load diode, and constant current sources I241, I242, and I243. The constant current source I241 supplies current to the transistors MN20 and MN21 constituting the differential pair, and the constant current sources I242 and I243 supply bias current to the load diode.

  The constant current sources I242 and I243 adjust the magnitude of the bias current I2 supplied to the transistors MN22 and MN23 constituting the load diode, and the gate-source voltage Vgs is adjusted to make the transistors MN20 and MN21 constituting the differential pair. Regardless of the operating state, a range in which the drain current always flows with a sufficient magnitude is set in advance.

  As a result, even if the currents flowing through the transistors MN22 and MN23 constituting the load diode change due to temperature fluctuation or the like, fluctuations in the output voltages OUTN13 and OUTP14 are suppressed, and a differential amplifier circuit with little gain fluctuation due to temperature can be obtained.

However, the differential amplifier circuit has the following problems.
That is, in this differential amplifier circuit, at least three transistors are connected in series between the power supply potential VDD and the ground potential GND. Considering that the threshold voltage of a normal MOS transistor is about 0.6 V and the drain-source voltage operating in the saturation region is 0.4 V when the power supply voltage is 1.35 V, the power supply potential VDD The number of elements that can be connected in series between the ground potential GND is limited to two transistors and one passive element such as a resistor. Therefore, the differential amplifier circuit of FIG. 2 has a problem that it cannot operate normally at a low power supply voltage of 1.35V.

  An object of the present invention is to provide a differential amplifier circuit which can operate normally even with a low power supply voltage of 1.35 V, for example, and has little gain fluctuation due to temperature.

  The differential amplifier circuit of the present invention has a differential amplifier having a gain controlled according to the current of the constant current unit controlled by the adjustment signal, and a differential circuit having the same configuration as the differential amplifier. A temperature fluctuation detecting means for detecting a current difference generated according to a temperature fluctuation by biasing the two input sides of the differential circuit with a minute electric potential difference and a reference current for comparison according to the minute electric potential difference are generated. A comparison current generation unit; and a current adjustment unit that outputs the adjustment signal so that the current difference detected by the temperature fluctuation detection unit and the reference current generated by the comparison current generation unit have the same value. It is characterized by.

  In the present invention, the temperature difference detecting means biases a differential circuit having the same configuration as the differential amplifying means with a minute potential difference to detect a current difference generated according to the temperature fluctuation, and the comparison current generating means detects the same minute difference. A reference current for comparison according to the potential difference is generated, and an adjustment signal is output from the current adjustment means so that the current difference due to temperature fluctuation becomes the same value as the reference current for comparison. As a result, the gain of the differential amplifying means is controlled so as to have a ratio of resistance values, and there is an effect that fluctuations in resistance values due to manufacturing variations and fluctuations in temperature due to temperature fluctuations can be suppressed.

  The differential amplifying means, the temperature fluctuation detecting means, the comparison current generating means, and the current adjusting means have a circuit configuration in which the number of transistors connected in series between the power supply potential and the ground potential is two or less. Thereby, for example, a normal operation can be performed even with a low power supply voltage of 1.35V.

FIG. 1 is a configuration diagram of a differential amplifier circuit showing an embodiment of the present invention.
The differential amplifier circuit includes a reference voltage generation unit 1, a temperature fluctuation detection unit 2, a comparison current generation unit 3, a current adjustment unit 4, and a differential amplification unit 5.

  The reference voltage generation unit 1 includes a resistor voltage divider connected between the power supply potential VDD and the ground potential GND, and has two potentials VDD-V1 and VDD-V2 (where V1> V2) having a minute potential difference. The same potential V3 as this potential difference (V1-V2) is output.

  The temperature fluctuation detection unit 2 biases the differential circuit composed of MOS transistors with a small potential difference V1-V2 generated by the reference voltage generation unit 1, and detects a current difference Igm generated according to the ambient temperature. Is.

  The temperature fluctuation detection unit 2 has P-channel MOS transistors (hereinafter referred to as “PMOS”) 11 and 12 to which the potentials VDD-V1 and VDD-V2 from the reference voltage generation unit 1 are applied at respective gates. Yes. The sources of the PMOSs 11 and 12 are connected in common and connected to the power supply potential VDD via the PMOS 13 whose conduction state is controlled by the adjustment signal CON supplied from the current adjustment unit 4.

  The drains of the PMOSs 11 and 12 are connected to the ground potential GND through resistors 14 and 15, respectively. The drains of the PMOSs 11 and 12 are connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier (OP) 16. The output side of the operational amplifier 16 is connected to the gate of the PMOS 17, the source of the PMOS 17 is connected to the power supply potential VDD via the resistor 18, and the source is connected to the node N2.

  The node N2 is connected to the drain and gate of an N-channel MOS transistor (hereinafter referred to as “NMOS”) 19 and the gates of NMOS 20 and 21. The sources of the NMOSs 19 to 21 are connected to the ground potential GND, the drain of the NMOS 20 is connected to the drain of the PMOS 11, and the drain of the NMOS 21 is connected to the power supply potential VDD via the resistor 22. The current difference generated according to the ambient temperature is converted from the drain of the NMOS 21 into the voltage Vgm and output.

  The comparison current generator 3 generates the reference current Irf for comparison by applying the potential V3 (= V1-V2) generated by the reference voltage generator 1 to the resistor.

  The comparison current generator 3 has an operational amplifier 31 to which the potential V3 from the reference voltage generator 1 is applied to the inverting input terminal. The output side of the operational amplifier 31 is connected to the gate of the PMOS 32, and the source of the PMOS 32 is connected to the power supply potential VDD. The drain of the PMOS 32 is connected to the non-inverting input terminal of the operational amplifier 31 and is connected to the ground potential GND through the resistor 33.

  The output side of the operational amplifier 31 is further connected to the gate of the PMOS 34, and the source of the PMOS 34 is connected to the power supply potential VDD. The drain of the PMOS 34 is connected to the drain and gate of the NMOS 35 and the gate of the NMOS 36. The sources of the NMOSs 35 and 36 are connected to the ground potential GND, and the drain of the NMOS 36 is connected to the power supply potential VDD via the resistor 37. The reference current Irf for comparison is converted into a voltage Vrf and output from the drain of the NMOS 36.

  The current adjustment unit 4 generates an adjustment signal CON so that the current difference Igm detected by the temperature fluctuation detection unit 2 becomes the same value as the reference current Irf generated by the comparison current generation unit 3, and detects the temperature fluctuation. The current difference Igm output from the unit 2 is adjusted.

  The current adjustment unit 4 includes an operational amplifier 41, the non-inverting input terminal of the operational amplifier 41 is connected to the drain of the NMOS 21 of the temperature fluctuation detection unit 2, and the inverting input terminal is the drain of the NMOS 36 of the comparison current generation unit 3. It is connected to the. The output side of the operational amplifier 41 is connected to the gate of the NMOS 42, the drain of the NMOS 42 is connected to the node N 4, and the source is connected to the ground potential GND through the resistor 43. The node N4 is connected to the drain and gate of the PMOS 44, and the source of the PMOS 44 is connected to the power supply potential VDD. Further, a constant current circuit 45 is connected between the node N4 and the ground potential GND. The voltage of the node N4 is supplied to the temperature fluctuation detection unit 2 and the differential amplification unit 5 as the adjustment signal CON.

  The differential amplifier 5 controls the drive current with the adjustment signal CON supplied from the current adjustment unit 4 and amplifies the potential difference between the two input signals INP and INN to output complementary output signals OUTP and OUTN. It is.

  The differential amplifier 5 includes a PMOS 51 to which an adjustment signal CON is given to the gate. The source of the PMOS 51 is connected to the power supply potential VDD, and the drain is connected to the node N5. The node N5 is connected to the ground potential GND via a PMOS 52 and a resistor 53 connected in series, and is connected to the ground potential GND via a PMOS 54 and a resistor 55 connected in series. Input signals INP and INN are applied to the gates of the PMOSs 52 and 54, respectively, and complementary output signals OUTN and OUTP are output from the drains of the PMOSs 52 and 54, respectively.

  The operational amplifiers 16, 31, and 41 all have the same circuit configuration, and as shown in the one-dot chain line frame in the lower right of FIG. 1, the gates of the NMOSs a and B correspond to the non-inverting input terminal and the inverting input terminal, respectively. b. The sources of the NMOSa and b are connected to the ground potential GND, and the drain of the NMOSa is connected to the drain and gate of the PMOSc and the gate of the PMOSd. The sources of the PMOSs c and d are connected to the power supply potential VDD, and the drain of the PMOSd is connected to the drain of the NMOSb. The connection point between the drains of NMOSb and PMOSd is the output terminal out of this operational amplifier.

  Here, it is assumed that the constants and sizes of the elements constituting the differential amplifier circuit are set as follows.

  The resistors 14 and 15, the resistors 22 and 37, and the resistors 53 and 55 have the same resistance value. The PMOSs 11, 12, 52, 54, PMOSs 13, 44, 51, PMOSs 32, 34, NMOSs 19, 20, 21, and NMOSs 35, 36 are the same size. Also, the NMOSs a and b and the PMOSs c and d constituting the operational amplifiers 16, 31, and 41 have the same size.

  Thus, in this differential amplifier circuit, the number of transistors connected in series between the power supply potential VDD and the ground potential GND is limited to two to reduce the power supply voltage.

Next, the operation will be described.
In the temperature fluctuation detection unit 2, a differential amplifier is configured by the PMOSs 11 to 13 and the resistors 14 and 15, and the gates of the PMOSs 11 and 12 are biased to the potentials VDD-V1 and VDD-V2, respectively. Accordingly, assuming that the currents flowing through the PMOSs 11 and 12 are Ia and Ib and the current flowing through the PMOS 13 is I, VDD−V1 <VDD−V2, and therefore, the following relationship is established.
I = Ia + Ib, Ia> Ib

  The drains of the PMOSs 11 and 12 are connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier 16, respectively. Here, when the potential at the non-inverting input terminal of the operational amplifier 16 increases, the output potential also increases. Since the operational amplifier 16 forms a source follower circuit by the PMOS 17, NMOS 19 and 20, and the resistor 18, when the output potential of the operational amplifier 16 increases, the current Igm flowing through the PMOS 17 decreases. The PMOS 17 is connected in series with the NMOS 19, and the NMOS 19 and the NMOS 20 constitute a current mirror. Therefore, the current flowing through the NMOS 20 is also Igm. Therefore, when the output potential of the operational amplifier 16 rises due to the rise in the potential of the non-inverting input terminal of the operational amplifier 16, the current Igm flowing through the NMOS 20 decreases.

Since the current of the NMOS 20 is supplied from the drain of the NMOS 11, when the current of the NMOS 20 decreases, the current flowing from the drain of the NMOS 11 toward the resistor 14 increases accordingly. As a result, the voltage drop due to the resistor 14 increases, and the potential of the inverting input terminal of the operational amplifier 16 increases. By such an operation, the potentials of the inverting input terminal and the non-inverting input terminal of the operational amplifier 16 become equal, and the following equation is established.
Ia * R14 = (Ib-Igm) * R15

Here, R14 and R15 are the resistance values of the resistors 14 and 15, respectively, and these are set to the same value, so the above equation becomes as follows.
Ib = Ia-Igm (1)

Further, since the current Ia is the drain / source current of the PMOS 11, the following equation is obtained.
Ia = k × (V1−Vs−Vt) ² (2)
Here, Vs is the source potential of the PMOS 11, Vt is the threshold voltage of the PMOS 11, and k is a constant proportional to the dimension of the PMOS 11 (gate width W / gate length L).

Similarly, the current Ib is the drain-source current of the PMOS 12, and the PMOSs 11 and 12 have the same size.
Ib = k × (V2−Vs−Vt) ² ... (3)

Substituting Equations (2) and (3) into Equation (1) yields the following equation:
k * (V2-Vs-Vt) ² = k * (V1-Vs-Vt) ^2- Igm
Therefore, Igm is as follows.
Igm = k * (V1-Vs-Vt) ^2- k * (V2-Vs-Vt) ²
= K * (V1-Vs-Vt + V2-Vs-VT) * (V1-V2) (4)

Since the static characteristic of the MOS transistor is Ids = k × (Vg−Vs−Vt) ² , the conductance gm is as follows.
gm = 2k × (Vg−Vs−Vt) (5)

Here, if the conductances of the PMOSs 11 and 12 are gm1 and gm2, respectively, the following equations are obtained from the equations (4) and (5).
Igm = (gm1 / 2 + gm2 / 2) × (V1-V2) (6)

Here, when the difference between the voltages V1 and V2 is reduced, gm1 and gm2 are substantially equal. When substantially equal conductances gm1 and gm2 are gmorg, the equation (6) is as follows.
Igm = gmor × (V1−V2) (7)

The NMOSs 19 and 21 constitute a current mirror, and since their sizes are the same, the current flowing through the NMOS 21 is also Igm. Therefore, the potential Vgm of the drain of the NMOS 21 is as follows when the resistance value of the resistor 22 is R22.
Vgm = VDD-Igm × R22
= VDD-gmorg * (V1-V2) * R22 (8)

On the other hand, in the comparison current generator 3, the operational amplifier 31, the PMOS 32, and the resistor 33 constitute a voltage follower. As a result, when the potential at the inverting input terminal of the operational amplifier 31 increases, the output potential of the operational amplifier 31 decreases and the current of the PMOS 32 increases. Accordingly, the voltage drop of the resistor 33 increases, and the potential of the non-inverting input terminal of the operational amplifier 31 increases. Conversely, when the potential at the inverting input terminal decreases, the output potential of the operational amplifier 31 increases and the current of the PMOS 32 decreases. In accordance with this, the voltage drop of the resistor 33 decreases and the potential of the non-inverting input terminal of the operational amplifier 31 decreases. By such an operation, the voltage applied to the resistor 33 becomes V3 which is the same as the potential of the non-inverting input terminal of the operational amplifier 31, and the current Irf flowing through the PMOS 32 is as follows when the resistance value of the resistor 33 is R33 become.
Irf = V3 / R33

The gates of the PMOSs 32 and 34 are commonly connected to the output side of the operational amplifier 31, and since the sizes thereof are the same, the current flowing through the PMOS 34 and the NMOS 35 is also Irf. Further, since the NMOSs 35 and 36 constitute a current mirror, the current flowing through the NMOS 36 is also Irf. Therefore, the potential Vrf of the drain of the NMOS 36 is as follows when the resistance value of the resistor 37 is R37.
Vrf = VDD−Irf × R37
= VDD-V3 × R37 / R33 (9)

  The operational amplifier 41 of the current adjustment unit 4 is supplied with the potential Vgm from the temperature fluctuation detection unit 2 and the potential Vrf from the comparison current generation unit 3.

  If the potential Vgm applied to the non-inverting input terminal of the operational amplifier 41 and the potential Vrf applied to the inverting input terminal are the same, and the potential Vgm of the non-inverting input terminal rises, the output potential of the operational amplifier 41 is also increased. To rise. Since the NMOS 42 and the resistor 43 connected to the output side of the operational amplifier 41 constitute a source follower, the voltage applied to the resistor 43 increases. As a result, the current flowing through the NMOS 42 increases. Since the current flowing through the constant current circuit 45 is constant, the current flowing through the PMOS 44 increases by the same current as the increased current of the NMOS 42.

  The PMOS 44 constitutes a current mirror with the PMOS 13 of the temperature variation detection unit 2, and since these are set to the same size, the currents flowing through the PMOSs 44 and 13 have the same I. Accordingly, the current flowing through the PMOS 13 of the temperature variation detection unit 2 also increases by the same current as the increased current of the NMOS 42. As a result, the currents Ia and Ib flowing through the PMOSs 11 and 12 of the temperature fluctuation detection unit 2 also increase.

  Here, when the conductance gm in the equation (5) is expressed by another description, gm = 2√ (k × Ids), the conductance gm increases as the current flowing through the MOS transistor increases. As a result, when the currents Ia and Ib of the PMOSs 11 and 12 increase, the conductance gmor in the equation (8) increases and Vgm decreases.

Conversely, when the potential Vgm at the non-inverting input terminal of the operational amplifier 41 falls, the operation is performed so that the potential Vgm rises by the same feedback path. As a result, the potential Vgm applied to the non-inverting input terminal of the operational amplifier 41 and the potential Vrf applied to the inverting input terminal are controlled to be always the same potential. Therefore, the following equation is established from the equations (8) and (9).
VDD−V3 × R37 / R33 = VDD−gmor × (V1−V2) × R22
Thereby, gmorg is expressed by the following equation.
gmorg = V3 / (V1-V2) × R37 / (R33 × R22)
Here, since V3 = V1-V2 and R22 = R37, gmorg is as follows.
gmorg = 1 / R33 (10)

In the differential amplifying unit 5, the PMOS 51 forms a current mirror with the PMOS 41 of the current adjusting unit 4, and these PMOSs 41 and 51 are set to the same size, so that the current flowing through the PMOS 51 is also I. Therefore, when the input signals INP and INN input to the gates of the PMOSs 52 and 54 are in a balanced state, the conductance gm of the PMOSs 52 and 54 is equal to the conductance value of the PMOSs 11 and 12 in the temperature variation detection unit 2, that is, gmorg. Match. Here, the gain Gain of the differential amplifier 5 is the product of the conductance gmor of the PMOS 52 (54) and the resistance value R53 of the resistor 53 (55).
Gain = gmor × R53

Substituting equation (10) into the above equation, the gain Gain of the differential amplifying unit 5 is as follows.
Gain = R53 / R33
That is, the gain Gain of the differential amplifier 5 is determined by the resistance ratio.

  As described above, the differential amplifier circuit of this embodiment includes the temperature fluctuation detection unit 2 that detects the current difference generated according to the ambient temperature by biasing the differential circuit with the minute potential difference V1-V2, and the minute fluctuation circuit. The comparison current generation unit 3 that generates a reference current for comparison according to the potential difference V1−V2, the potential Vgm output from the temperature fluctuation detection unit 2, and the potential Vrf output from the comparison current generation unit 3 are the same. A current adjustment unit 4 that generates an adjustment signal COM for setting the value is provided, and the gain of the differential amplification unit 5 is controlled by the adjustment signal COM. As a result, the gain of the differential amplifying unit 5 can be determined by the ratio of the resistance values, so that there is an advantage that a constant gain can be obtained without depending on manufacturing variations of resistance values and temperature fluctuations.

  Further, the temperature fluctuation detection unit 2, the comparison current generation unit 3, the current adjustment unit 4, and the differential amplification unit 5 constituting the differential amplifier are transistors connected in series between the power supply potential VDD and the ground potential GND. The circuit configuration is limited to two. As a result, there is an advantage that normal operation is possible even with a low power supply voltage such as 1.35V.

  In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.

  The number of differential amplifiers 5 to be controlled is not limited to one, and a plurality of differential amplifiers can be controlled simultaneously with the same adjustment signal COM.

It is a block diagram of the differential amplifier circuit which shows the Example of this invention. It is a block diagram of the conventional differential amplifier circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reference voltage generation part 2 Temperature fluctuation detection part 3 Comparison current generation part 4 Current adjustment part 5 Differential amplification part 11-13, 17, 32, 34, 44, 51, 52, 54 PMOS
14, 15, 18, 22, 33, 37, 43, 53, 55 Resistors 16, 31, 41 Operational amplifiers 19-21, 35, 36, 42 NMOS
45 Constant current circuit

Claims (2)

Differential amplification means whose gain is controlled in accordance with the current of the constant current section controlled by the adjustment signal;
A temperature fluctuation detecting means having a differential circuit having the same configuration as the differential amplifying means, and biasing two input sides of the differential circuit with a small potential difference to detect a current difference generated according to the temperature fluctuation; ,
Comparison current generating means for generating a reference current for comparison according to the minute potential difference;
Current adjusting means for outputting the adjustment signal so that the current difference detected by the temperature fluctuation detecting means and the reference current generated by the comparison current generating means have the same value;
A differential amplifier circuit comprising:   The differential amplifying means, the temperature fluctuation detecting means, the comparison current generating means, and the current adjusting means comprise two or less transistors connected in series between a power supply potential and a ground potential. The differential amplifier circuit according to claim 1.

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