JP2007142716A - Demodulating device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a circuit by reducing a time required for normal synchronization establishment while detecting erroneous synchronization of a carrier wave in a demodulating device for satellite use that receives and demodulates a phase-modulated signal. <P>SOLUTION: A carrier wave frequency during normal synchronization is determined by utilizing symmetry of a spectrum of a phase-modulated wave from an AGC voltage 107 of an automatic gain control circuit certainly used for the demodulating device for a communication between an earth orbiting satellite and an earth station. A synchronization determination circuit 12 determines a synchronized state. A memory 11 stores an AGC voltage at that time. A determination circuit 14 determines whether it is the normal synchronization or error synchronization from the stored AGC voltage. A pulse wave 114 is generated by a sequence circuit 13 and a pulse generation circuit 15, so as to make a frequency become the determined frequency, and then, applied to a low-pass filter 4 for a phase-synchronization signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a demodulation device, and more particularly to prevention of erroneous synchronization detection of a demodulation device that demodulates a phase modulation signal.

  In order to demodulate the phase-modulated signal, it is necessary to perform synchronous detection with the regenerative carrier wave. However, when the relative distance between the transmitting station and the receiving station changes like the earth orbiting satellite and the ground station, the carrier frequency is changed to Doppler. Since it changes depending on the effect, it must be controlled so that the recovered carrier matches the input carrier. For this reason, the usual method is to arrange a phase synchronization circuit at the receiving station, and once transmit only the carrier wave, establish phase synchronization with the carrier at the receiving station, and then perform phase modulation at the transmitting station.

  However, after establishing phase synchronization and starting demodulation, if the phase synchronization is lost due to a sudden and temporary level change due to antenna nulling or fading and resynchronization occurs, the Doppler effect while the synchronization is lost Due to the change in the frequency of the input carrier due to or the shift of the recovered carrier to the optimum standby frequency, the frequency of the sideband near the carrier and the frequency of the recovered carrier may be the same, resulting in false synchronization with the sideband near the carrier. Even with such erroneous synchronization, the receiving station demodulates but does not perform correct synchronous detection, so the demodulation output is abnormal, and normal transmission cannot be performed no matter how many times the required signal is retransmitted. In order to solve this problem, a false synchronization prevention circuit is required that determines this state as false synchronization and reestablishes normal phase synchronization.

  FIG. 6 is a block diagram showing an example of a demodulator using a conventional erroneous synchronization prevention circuit (see, for example, Patent Document 1). The phase detector 3 performs phase synchronization detection using the received signal input from the input terminal 1 and the regenerated carrier wave 104 from the voltage controlled oscillator 5. The low-pass filter 6 extracts the demodulated signal 7 from the phase detection signal 102 output from the phase detector 3.

  The asynchronous amplitude detector 51 performs asynchronous amplitude detection on the demodulated signal 7 and generates a DC voltage 502. The determiner 52 compares the DC voltage 502 with the reference voltage 503 and generates an erroneous synchronization determination signal 504. The pulse generator 53 generates a phase control pulse 505 from the erroneous synchronization determination signal 504, and the low-pass filter 4 extracts the error voltage 103 from the phase detection signal 102. The signal adder 50 adds the phase control pulse 505 to the error voltage 103 and outputs it to the voltage controlled oscillator 5 as the control voltage 501.

  Next, the operation will be described. The phase detector 3 detects the phase of the received signal using the recovered carrier wave 104 from the voltage controlled oscillator 5 and outputs a phase error signal 102. The phase error signal 102 is band-limited by the low-pass filter 4, and the low-pass filter 4 outputs an error voltage 501. The phase error signal 102 is band-limited by the low-pass filter 6, and the low-pass filter 6 outputs a demodulated signal 7. The demodulated signal 7 is asynchronously detected by the asynchronous amplitude detector 51, and the asynchronous amplitude detector 51 outputs a DC voltage 502 corresponding to the signal amplitude.

  The DC voltage 502 is compared with the reference voltage 503 by the determiner 52, and the determiner 52 outputs an erroneous synchronization determination signal 504 when the two do not match. The pulse generator 53 generates a phase control pulse 505 in response to the erroneous synchronization determination signal 504. The phase control pulse 505 is added to the error voltage 501 by the adder 50, and the adder 50 outputs the control voltage 103. The control voltage 103 controls the voltage controlled oscillator 5, and the voltage controlled oscillator 5 outputs the regenerated carrier wave 104 to the phase detector 3. This operation is repeated, and when both the DC voltage 502 and the reference voltage 503 coincide with each other in the determiner 52, the erroneous synchronization is eliminated and a normal synchronization state is obtained.

  As described above, a circuit that generates a reference voltage equivalent to the asynchronous detection of the demodulated output during normal synchronization is arranged on the receiving station side, and the error is detected by comparing this reference voltage with the asynchronous detection output of the actual demodulated output. / Normal synchronization is determined in a short time, and the transition to normal synchronization is realized by applying the control voltage 103 to the voltage controlled oscillator 5 based on the determination result.

Japanese Patent Laid-Open No. 2001-077873 (page 3 to page 5, FIG. 1)

  However, in the demodulator described in Patent Document 1 described above, a signal adder 50 for adding a phase control pulse 505 based on the synchronization determination result to the error voltage 501 that is the output of the low-pass filter 4 is provided, and this adder output is controlled. The voltage 103 is applied to the voltage controlled oscillator 5. In this configuration, after normal synchronization is established with the control voltage 103 applied, that is, with the offset applied by the control voltage 103, it is necessary to shift to a normal synchronization state in which the control voltage 103 does not exist. Therefore, it is necessary to gradually reduce the application amount of the control voltage 103 to the extent that the synchronization is not lost, and finally to zero, and there is a problem that the circuit for this is complicated.

  Specifically, the pulse generator 53 adds the pulses from the pulse generation circuit and timer that operate at the time of the upper band mis-synchronization, the pulse generation circuit and timer that operate at the time of the lower band mis-synchronization, and the pulses from the two pulse generation circuits. And an adder. When each pulse generation circuit determines that the data corresponding to the change of the generated pulse is stored and the determiner 52 is in normal synchronization, the carrier frequency and the side band are the frequency of the frequency with respect to the memory. A counter that specifies an address for changing the voltage value corresponding to the difference from the voltage value to zero volts, a timer that measures the timeout time of normal synchronization, and a D / A converter that converts the data read from the memory into an analog signal Including.

  If the above operation is not performed, synchronization is maintained with the offset applied. However, in order to establish resynchronization after loss of synchronization due to antenna nulling or fading, the same offset amount is included in the calculation and synchronization control is performed. Since it is necessary to determine and apply a signal application amount, the circuit is also complicated. Further, there is a problem that the number of circuits increases because it is necessary to provide the asynchronous amplitude detector 51.

  An object of the present invention is to provide a demodulating device that can detect downsynchronization in a short time, shorten the time required to establish normal synchronization, simplify the circuit, and realize downsizing / lightening. is there.

  The demodulating device of the present invention is a demodulating device that generates a recovered carrier wave from a received signal by a phase locked loop (3 to 5 in FIG. 1) and performs synchronous detection to demodulate the phase modulated signal. Level detection means for detecting sideband levels including components, determination means for determining whether the synchronization state is normal synchronization or false synchronization from the carrier wave level or the sideband level, and a reproduced carrier wave by a control signal based on the determination And a control means for controlling the frequency.

  The level detection means includes a variable gain amplifier (2 in FIG. 1) that amplifies a received signal using the output of the level detection means as an AGC voltage, and a phase that is 90 degrees shifted in phase of the output of the phase detector in the phase locked loop. A phase shifter (8 in FIG. 1), an amplitude detector (9 in FIG. 1) that outputs an amplitude error signal by multiplying the output of the 90-degree phase shifter and the output of the variable gain amplifier, You may make it have a low-pass filter (10 of FIG. 1) which suppresses the harmonic of an error signal.

  Preferably, the determination means includes a synchronization determination circuit (12 in FIG. 1) that determines the synchronization state by comparing the output of the level detection means with a predetermined level, and a memory that stores the output of the level detection means in the synchronization state (11 in FIG. 1) and a determination circuit (14 in FIG. 1) for determining whether the synchronization state is normal synchronization or erroneous synchronization based on the output of the level detection means stored in the memory.

  The determination circuit may make a determination using the symmetry of the spectrum of the phase modulation wave centered on the normal synchronization of the AGC voltage in the erroneous synchronization.

  Preferably, the control means is a sequence circuit (13 in FIG. 1) that issues an output command when receiving an activation signal from the determination means, and a pulse generation circuit that generates a pulse signal according to the control command from the determination means when receiving an output command (15 in FIG. 1) and a low-pass filter (4 in FIG. 1) that receives the pulse signal and generates a frequency control signal.

  The control command instructs the output of the pulse signal to maintain a fixed value of + when shifting from the sideband to the upper synchronization frequency, and − when moving to the lower synchronization frequency for a certain period of time, and is in a normal synchronization state Then, the stop of the pulse signal may be ordered.

  Preferably, the low-pass filter inputs a pulse signal to an integrator which is a constituent circuit.

  In the present invention, using the fact that the AGC voltage is symmetrical when there is a false synchronization with the upper / lower sidebands, the carrier wave is identified and brought into normal synchronization after performing the synchronization operation to the carrier / sideband multiple times. In addition, the pulse wave is applied before the integrator in the loop filter in order to generate a control signal for the voltage controlled oscillator from the decision circuit. At the same time, it is possible to obtain the effect that the circuit can be simplified, reduced in size, and reduced in weight.

  Usually, in the communication between the earth-orbiting satellite and the ground station, the spatial transmission loss fluctuates according to the change in distance, so that the receiving side input level changes by 50 dB or more. In order to correct this, the receiving station side has an automatic gain control (AGC) function. The AGC function outputs the AGC signal to a low-noise amplifier and an intermediate amplifier (in the case of a heterodyne receiver) based on information obtained by synchronous amplitude detection of the received signal, and the received signal amplitude at the detection stage is constant. Work to control. Here, the AGC does not act to make the total power (amplitude) of the received signal constant, but works to make the power (amplitude) of the carrier wave or sideband locked by the phase locked loop constant.

  In phase modulation, the relative level of a carrier wave and a modulation signal (sideband wave) is determined by the type of modulation signal (sine wave or short wave) and the degree of modulation. For this reason, the AGC voltage differs between when synchronous detection is performed in synchronization with a carrier wave and when synchronous detection is performed in synchronization with a sideband wave. The AGC voltage is the same when mis-synchronized with the first upper sideband or the first lower sideband, and when mis-synchronized with the second upper sideband or the second lower sideband, the voltage is different from that of the first sideband. In the case of carrier wave synchronization, the AGC voltage is the same, and the maximum AGC voltage is different from any of these cases. If the AGC voltages are arranged at the time of the upper / lower sideband synchronization around the carrier synchronization, the AGC voltage array becomes symmetrical and decreases around the carrier synchronization.

  For this reason, once synchronized, the AGC voltage is stored in the memory when the playback carrier frequency is stepped multiple times by the modulation signal frequency once synchronized (since the frequency of the modulation signal is known), and the upper / lower sideband mis-synchronization occurs. The carrier frequency (normal synchronization frequency) is determined by using the symmetry of the AGC voltage array. Note that the change in the recovered carrier frequency is realized by applying a step voltage to the integrating circuit of the phase-locked loop filter.

As described above, the demodulator of the present invention has means for determining whether the synchronization is normal or incorrect using the automatic gain control voltage that is always used for the communication demodulator for the earth-orbiting satellite and the ground station. The synchronization determination means includes a synchronization determination circuit that determines the synchronization state by comparing the output of the level detection means with a predetermined level, a memory that stores the output of the level detection means in the synchronization state, and a level stored in the memory It has a determination circuit for determining whether the synchronization state is normal synchronization or erroneous synchronization based on the output of the detection means. Further, a low-pass filter having an adder that adds a control signal generated from the synchronization determination signal to the phase error signal is used. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Description of configuration]
FIG. 1 is a block diagram showing an embodiment of a demodulator according to the present invention. In the demodulator, the variable gain amplifier 2 is provided in the conventional demodulator shown in FIG. 5 to correct the fluctuation of the spatial transmission loss, and the received signal amplitude at the detection stage is made constant. In order to generate an AGC voltage for the variable gain amplifier 2, a 90 degree phase shifter 8, an amplitude detector 9, and a low pass filter 10 are provided.

  In addition, AGC uses the fact that the power (amplitude) of the received carrier wave is made constant, and the synchronization determination circuit 12 for determining synchronization by the AGC voltage and the symmetry of the AGC voltage when it is erroneously synchronized to the upper / lower sidebands If it is determined that it is in a synchronized state, the carrier wave is identified and brought into normal synchronization after performing the synchronization operation to the carrier wave / sideband multiple times, and the voltage controlled oscillator 5 is controlled. A memory 11, a sequence circuit 13, a determination circuit 14, and a pulse generation circuit 15 for applying a pulse wave for signal generation are provided.

  The variable gain amplifier 2 is a low noise amplifier or an intermediate amplifier (in the case of a heterodyne receiver) that amplifies the reception signal input from the input terminal 1, and the amplitude of the reception signal is made constant by the AGC voltage from the low-pass filter 10. The controlled amplified signal 101 is output. Here, the AGC does not act to make the total power (amplitude) of the received signal constant, but works to make the power (amplitude) of the received carrier wave constant.

  The phase detector 3 detects the phase of the amplified signal 101 using the recovered carrier wave 104 from the voltage controlled oscillator 5 and outputs a phase error signal 102. The phase error signal 102 is band-limited by the low-pass filter 4, and the low-pass filter 4 outputs the error voltage as the control voltage 103. The voltage controlled oscillator 5 generates a regenerated carrier wave 104 having a frequency corresponding to the control voltage 103. The phase detector 3, the low pass filter 4 and the voltage controlled oscillator 5 form a phase locked loop. The desired demodulated signal 7 is a signal obtained by band-limiting the phase error signal 102 output from the phase detector 3 by the low-pass filter 6.

  The 90-degree phase shifter 8 outputs a phase-shifted signal 105 obtained by shifting the phase of the reproduced carrier 104 by 90 degrees to the amplitude detector 9, and the amplitude detector 9 obtains the amplitude obtained by multiplying the phase-shifted signal 105 and the amplified signal 101. The error signal 106 is output to the low pass filter 10. The low-pass filter 10 generates a gain control signal (AGC voltage) 107 for the variable gain amplifier 2 by suppressing harmonics and out-of-band noise of the amplitude error signal 106.

  The synchronization determination circuit 12 determines whether or not the received signal is in a synchronized state by confirming that the AGC voltage 107 is at a predetermined level. When it is determined that the synchronization state is established, the activation signal 110 is output to the sequence circuit 13 and the synchronization determination signal 109 is output to the determination circuit 14. The synchronization determined here includes normal synchronization when synchronized with a carrier wave and erroneous synchronization when synchronized with a sideband.

  Upon receiving the activation signal 110, the sequence circuit 13 outputs a write command 111 to the memory 11 and stores an output command 112 to the pulse generation circuit 15 so as to store the AGC voltage 107 at that time. When the memory 11 receives the write command 111, the memory 11 stores the AGC voltage 107 at this time.

  When the determination circuit 14 receives the output command 112, it takes in the data of the AGC voltage stored in the memory 11, sequentially rearranges them in the order of frequency, and uses the symmetry of the AGC voltage when it is erroneously synchronized with the upper / lower sidebands. To determine normal synchronization. Since the center frequency of symmetry is the desired regenerative carrier wave, control for causing the pulse generation circuit 15 to output a desired pulse wave 114 so that the frequency of the voltage controlled oscillator 5 becomes the center frequency of symmetry is conscious of symmetry. Command 113 is output.

  The control instruction 113 at this time is as follows. If it is judged that the AGC voltage data fetched from the memory 11 is erroneously synchronized, and that it is necessary to shift to the upper side band for normal synchronization, a control command 113 for outputting the pulse wave 114 in the + direction is issued. Output. On the other hand, if it is determined that the AGC voltage data fetched from the memory 11 is mis-synchronized and it is necessary to shift to the lower sideband for normal synchronization, a control command 113 for outputting the negative-direction pulse wave 114 is issued. Output. However, if it is determined from the AGC voltage data fetched from the memory 11 that the frequency is the center of symmetry and the normal synchronization is established, the control command 113 is not output after the AGC voltage at the normal synchronization is set.

The pulse generation circuit 15 outputs a pulse wave 114 to the low-pass filter 4 according to the output command 112 and the control command 113 as described above. The pulse wave 114 is a waveform that maintains a fixed level for a certain period of time.
[Description of operation]
Next, the operation of the demodulator configured as described above will be described. The received signal from the received signal input terminal 1 is a signal in which phase modulation is applied to the carrier wave. The received signal is amplified by the variable gain amplifier 2, and the amplified signal 101 is divided into two. One is input to the phase detector 3 and the other is input to the amplitude detector 9.

  The amplified signal 101 is multiplied by the reproduced carrier wave 104 from the voltage controlled oscillator 5 in the phase detector 3 and output to the low-pass filter 4 as the phase error signal 102. The low-pass filter 4 suppresses harmonics and out-of-band noise of the phase error signal 102 and outputs a control voltage 103 for the voltage controlled oscillator 5. The voltage controlled oscillator 5 outputs the regenerated carrier wave 104 by the control voltage 103.

  On the other hand, the amplified signal 101 input to the amplitude detector 9 is multiplied by the signal 105 obtained by shifting the reproduced carrier 104 by 90 degrees by the 90-degree phase shifter 8 to become an amplitude error signal 106 and output to the low-pass filter 10. The In the low-pass filter 10, the AGC voltage 107 of the variable gain amplifier 2 is generated by suppressing harmonics of the amplitude error signal 106. The AGC voltage 107 is supplied to the AGC amplifier 2 and is used to keep the input signal power of the phase detector 3 and the amplitude detector 9 constant. In the case of satellite communication, the propagation loss changes with the distance and the received power changes, so this function is always placed on the receiving station side. This function is called an automatic gain control (AGC) function.

  The AGC voltage 107 is also supplied to the synchronization determination circuit 12 and used for synchronization determination. Normal synchronization in the determination circuit 14 from the time when the start signal 110 is output to the sequence circuit 13 when the synchronization determination circuit 12 once determines that it is in the synchronization state, or once it is determined that the synchronization state has changed from the synchronization state to the asynchronous state. Or the operation of determining whether the synchronization is incorrect.

  Upon receiving the start signal 110, the sequence circuit 13 outputs a write command 111 to the memory 11 so as to store the AGC voltage 107 at that time, and the pulse generation circuit 15 outputs a pulse wave 114 to the low-pass filter 4. The output command 112 is output.

  The pulse wave 114 is applied to the previous stage of the integration circuit in the low-pass filter 4 shown in detail in FIGS. During application of the pulse wave 114, the pulse wave 114 is integrated by the low-pass filter 4, so that the control voltage 103 for the voltage controlled oscillator 5 changes in a ramp shape. When the pulse wave 114 becomes zero, the modulation signal frequency (known) is changed. ), The value of the control signal 103 is changed and fixed. As a result, the frequency of the recovered carrier 104 is ramp swept by the modulation signal frequency (known) and then stopped. The amplitude and pulse width of the pulse wave 114 are set such that the frequency change width is as follows.

  In the case of the Earth orbiting satellite / Earth station, the low-pass filter 4 and the low-pass filter 10 have a cutoff frequency set to about several hundred Hz, so that the phase synchronization and AGC control converge in about 1 second after the frequency of the recovered carrier 104 changes. (Re-synchronize). After resynchronization, the AGC voltage is stored and the pulse wave 114 is applied again. Repeat this several times.

  The decision circuit 14 that has captured the AGC voltage data stored in the output command 112 and the memory 11 sequentially rearranges the AGC voltage data in order of frequency, and determines the symmetry of the AGC voltage when it is mis-synchronized with the upper / lower sidebands. Use to determine normal synchronization. As a result, if it is false synchronization, the frequency of the symmetric center is the desired reproduced carrier wave, so that the pulse generator circuit 15 can receive the desired pulse so that the frequency of the voltage controlled oscillator 5 becomes the symmetric center frequency in consideration of symmetry. A control command 113 for outputting the wave 114 is output. Hereinafter, this process will be specifically described. The AGC voltage when normally synchronized with the carrier wave is V0, the AGC voltage when erroneously synchronized with the first sideband is V1, and the AGC voltage when erroneously synchronized with the second sideband is V2. At this time, V2 <V1 <V0.

  Now, the case of erroneous synchronization with the first lower sideband will be described. Assume that the AGC voltage V1 is stored in the memory 11, and the pulse generation circuit 15 outputs a positive pulse wave 114 in accordance with the control command 113. If the AGC voltage V0 obtained thereby determines that the synchronization determination circuit 12 is in the synchronization state, the AGC voltage V0 at this time is stored in the memory 11. The determination circuit 14 compares the AGC voltage V1 with the AGC voltage V0.

  As a result, since V1 <V0, the pulse generation circuit 15 outputs the + pulse wave 114 again according to the control command 113. When it is determined that the synchronization determination circuit 12 is in the synchronization state based on the AGC voltage V3 (= V1) obtained in this way, the AGC voltage V1 at this time is stored in the memory 11. The determination circuit 14 compares the AGC voltage V0 and the AGC voltage V3 (= V1). As a result, since V1 <V0, the determination circuit 14 determines that the AGC voltage V0 is an AGC voltage corresponding to the normal synchronization frequency. The above procedure is shown in FIG. In FIG. 4, the relative level of the symmetrical AGC voltage is represented by the line length. If the initial synchronization state is an erroneous synchronization with the second lower sideband, the operation starts from the AGC voltage V2, so the synchronization determination circuit 12 needs to determine the synchronization again.

  On the other hand, it is assumed that the pulse generation circuit 15 outputs a negative pulse wave 114 in accordance with the control command 113 in the initial state of the AGC voltage V1. If the AGC voltage V2 obtained thereby determines that the synchronization determination circuit 12 is in the synchronization state, the AGC voltage V2 at this time is stored in the memory 11. The determination circuit 14 compares the AGC voltage V1 with the AGC voltage V2.

  As a result, since V2 <V1, the pulse generation circuit 15 outputs the positive pulse wave 114 this time in accordance with the control command 113, and once returns to the synchronized state of V1, the procedure described above is followed. In this case, since the control instruction 113 is output in the wrong direction by the determination circuit 14, the synchronization determination is required three times compared to the two synchronization determinations in the procedure of FIG. The above procedure is shown in FIG.

  Next, a case where erroneous synchronization with the first upper side band wave is described will be described. Assume that the AGC voltage V1 is stored in the memory 11, and the pulse generation circuit 15 outputs a negative pulse wave 114 in accordance with the control command 113. If the AGC voltage V0 obtained thereby determines that the synchronization determination circuit 12 is in the synchronization state, the AGC voltage V0 at this time is stored in the memory 11. The determination circuit 14 compares the AGC voltage V1 with the AGC voltage V0.

  As a result, since V1 <V0, the pulse generation circuit 15 outputs the + pulse wave 114 again according to the control command 113. When it is determined that the synchronization determination circuit 12 is in the synchronization state based on the AGC voltage V1 obtained as a result, the AGC voltage V1 at this time is stored in the memory 11. The determination circuit 14 compares the AGC voltage V0 with the AGC voltage V1. As a result, since V1 <V0, the determination circuit 14 determines that the AGC voltage V0 is an AGC voltage corresponding to the normal synchronization frequency. The above procedure is shown in FIG. If the initial synchronization state is a false synchronization with the second upper side band wave, the operation starts from the AGC voltage V2, so the synchronization determination circuit 12 needs to determine the synchronization again.

  On the other hand, it is assumed that the pulse generation circuit 15 outputs a positive pulse wave 114 in accordance with the control command 113 in the initial state of the AGC voltage V1. If the AGC voltage V2 obtained thereby determines that the synchronization determination circuit 12 is in the synchronization state, the AGC voltage V2 at this time is stored in the memory 11. The determination circuit 14 compares the AGC voltage V1 with the AGC voltage V2.

  As a result, since V2 <V1, the pulse generation circuit 15 outputs a negative pulse wave 114 this time in accordance with the control command 113, once returns to the synchronized state of V1, and then follows the above procedure. In this case, since the control instruction 113 is output in the wrong direction by the determination circuit 14, the synchronization determination is required three times compared to the two synchronization determinations in the procedure of FIG. The above procedure is shown in FIG.

  As described above, by using the symmetry of the AGC voltage arrangement (symmetry of the phase modulation wave spectrum) when mis-synchronized with the upper / lower sideband waves, the carrier wave of the received signal is identified, and the recovered carrier wave Since the desired frequency is controlled, it is possible to detect erroneous synchronization in a short time and reduce the time required for establishing normal synchronization.

  FIG. 2 shows an example in which the low-pass filter 4 of FIG. 1 is composed of an analog filter using an operational amplifier and CR. A pulse wave 114 is applied to the connection between C and R, and the control voltage 103 of the voltage controlled oscillator 5 is changed onto the lamp.

  FIG. 3 shows an example in which the low-pass filter 4 of FIG. 1 is configured with a digital filter. After the analog phase error signal 102 is converted into digital data by the A / D converter 41, the multipliers 42 and 43 multiply this by a constant multiplier. The adder 45 adds the sequential input signal from the multiplier 43 and the output of the adder 44. The output of the adder 44 is obtained by adding the pulse wave 114 to the output of the adder 45 preceding the delay time by the delay unit 47. Since the D / A converter 48 converts the output of the adder 46 into an analog signal, the control signal 103 that is the output changes in a ramp shape as in FIG.

  The amplitude of the control signal 103 generated in this way is adjusted by the control command 113, and the control command 113 is blocked in the normal synchronization state. Conventionally, the normal synchronization signal in which the control voltage 103 does not exist in the normal synchronization state. In order to shift to the state, it is necessary to gradually reduce the application amount of the control voltage 103 to the extent that synchronization is not lost, and finally to zero, and the problem that the circuit for that purpose becomes complicated is eliminated.

  The present invention is effective for a demodulator installed in a place where a person cannot work directly and cancel the false synchronization. In particular, the present invention can be applied to a satellite-mounted receiving device that requires a reduction in size / weight.

The block diagram which shows the structure of the demodulator by one Example of the demodulator of this invention FIG. 1 is a block diagram showing an example when the low-pass filter 4 in FIG. FIG. 1 is a block diagram showing an example when the low-pass filter 4 in FIG. 1 is constituted by a digital filter. Diagram for explaining the operation to control the transition from false synchronization to lower sideband to normal synchronization Diagram for explaining the operation to control the transition from the incorrect synchronization to the upper side band to the normal synchronization Block diagram showing an example of a demodulator using a conventional anti-synchronization circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input terminal 2 Variable gain amplifier 3 Phase detector 4 Low pass filter 5 Voltage control oscillator 6 Low pass filter 7 Output terminal 8 90 degree phase shifter 9 Amplitude detector
10 Low pass filter
11 memory
12 Synchronization judgment circuit
13 Sequence circuit
14 Judgment circuit
15 Pulse generation circuit

Claims (7)

  In a demodulating apparatus that generates a regenerative carrier wave from a received signal by a phase-locked loop and performs synchronous detection to demodulate a phase-modulated signal, level detecting means for detecting a carrier wave level of a phase-modulated signal or a sideband level including a modulated signal component; A determination unit that determines whether the synchronization state is normal synchronization or false synchronization from the carrier wave level or the sideband level; and a control unit that controls the frequency of the reproduced carrier wave by a control signal based on the determination. Demodulator.   The level detection means includes a variable gain amplifier that amplifies the received signal using the output of the level detection means as an AGC voltage, and a 90-degree phase shifter that shifts the phase of the output of the phase detector in the phase-locked loop by 90 degrees And an amplitude detector that outputs an amplitude error signal by multiplying the output of the 90-degree phase shifter and the output of the variable gain amplifier, and a low-pass filter that suppresses harmonics of the amplitude error signal. The demodulator according to claim 1.   The determination unit includes a synchronization determination circuit that determines a synchronization state by comparing the output of the level detection unit with a predetermined level, a memory that stores the output of the level detection unit in the synchronization state, and the memory 3. The demodulator according to claim 1, further comprising a determination circuit that determines whether the synchronization state is normal synchronization or erroneous synchronization based on the stored output of the level detection means.   4. The demodulator according to claim 3, wherein the determination circuit performs the determination using a symmetry of a spectrum of a phase modulation wave centered on a normal synchronization of the AGC voltage in the erroneous synchronization.   The control means includes a sequence circuit that issues an output command when receiving an activation signal from the determination means, a pulse generation circuit that generates a pulse signal according to a control command from the determination means when receiving the output command, and the pulse signal 5. The demodulator according to claim 1, further comprising a low-pass filter that generates a frequency control signal in response to the signal.   The control command instructs the output of the pulse signal to maintain a fixed value of + when shifting from the sideband to the upper synchronization frequency, and − when moving to the lower synchronization frequency for a certain period of time, and is in a normal synchronization state 6. The demodulating device according to claim 5, wherein the instruction is to stop the pulse signal. 7. The demodulator according to claim 5, wherein the low-pass filter inputs the pulse signal to an integrator which is a constituent circuit.

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