JP2007141905A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the nonconformity due to the difference in the depth of a contact reaching a FUSI gate electrode, and that of a contact reaching a source/drain layer. <P>SOLUTION: Two FUSI contacts 41 are arranged, passing through the thickness direction of an interlayer insulating film 4 and reaching silicide layers 35 in the upper layers of the two source/drain layers 34 and the FUSI gate electrodes 32. In the FUSI contact 41, a contact opening CH1, passing through inside the interlayer insulating film 4, is filled with a FUSI contact layer 411 which is completely turned into silicide, and the contact 41 has the same height as the FUSI gate electrode 32. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a MOS transistor having a gate electrode metallized and a manufacturing method thereof.

  In a semiconductor device of the so-called 45 nm generation or later in which the gate length of the MOS transistor is set to about 45 nm, a metal gate such as a FUSI (fully silicided) gate in which the polysilicon gate deposited on the gate insulating film is completely silicided is required. It is said that.

  An example of the manufacturing method of the FUSI gate is disclosed in Patent Document 1 with reference to FIGS.

JP 2005-243678 A

  In FIG. 14 of Patent Document 1, a contact portion reaching the source / drain layer is shown. However, when a contact portion for electrically connecting the FUSI gate electrode to the upper wiring is assumed, the contact portion is Since the depth is different from the contact portion reaching the source / drain layer, it becomes shallower by the height of the FUSI gate electrode, which may cause the following problems.

  That is, it is difficult to control the etching when forming the contact opening, and in the contact portion reaching the source / drain layer, the area of the bottom surface of the contact opening is reduced, and finally the contact between the source / drain layer and the contact portion is reduced. Contact resistance may increase. In addition, in the contact portion reaching the FUSI gate electrode, if misalignment occurs, etching proceeds at a portion off the FUSI gate electrode, and a slit-shaped opening is provided along the side surface of the FUSI gate electrode. However, there arises a problem that the barrier metal layer cannot be reliably formed in the opening.

  The present invention has been made to solve the above problems, and has solved the problem caused by the difference in depth between the contact portion reaching the FUSI gate electrode and the contact portion reaching the source / drain layer. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

  According to a first aspect of the present invention, there is provided a semiconductor device including a field effect transistor having a silicide gate electrode made of silicide and disposed on a semiconductor substrate, the semiconductor device including the field effect transistor on the semiconductor substrate. An interlayer insulating film to be covered; a wiring layer disposed on the interlayer insulating film; and the wiring layer and a source / drain layer of the field effect transistor provided to penetrate the interlayer insulating film in a thickness direction Contact means for electrically connecting to each other, and the contact means is provided on the source / drain layer, has a silicide contact portion made of the silicide, and has a height of the silicide contact portion. Has the same height as the silicide gate electrode.

  A method for manufacturing a semiconductor device according to a sixth aspect of the present invention includes the following steps (a) to (g). That is, a step (a) of selectively forming a laminated film of at least a gate insulating film and a gate polysilicon layer on a semiconductor substrate, a step (b) of forming a sidewall insulating film on a side surface of the laminated film, A step (c) of forming a source / drain layer in the surface of the semiconductor substrate by ion implantation of impurities using the stacked film and the sidewall insulating film as a mask; and after the step (c), the side A step (d) of forming an interlayer insulating film on the semiconductor substrate so as to cover the laminated film on which the wall insulating film is formed; and a contact opening reaching the source / drain layer through the interlayer insulating film Forming the contact opening, filling the contact opening with a polysilicon layer, and filling the contact opening with the polysilicon layer and the gate policy. Fully silicided Con layer, and a step (g) to form a silicide gate electrode composed of the interlayer insulating film to penetrate reach the silicide layer silicide contacts portion and silicide.

  According to the semiconductor device of the first aspect of the present invention, the contact means for electrically connecting the wiring layer and the source / drain layer of the field effect transistor is disposed on the source / drain layer and is made of silicide. Since the silicide contact portion to be formed has the same height as the silicide gate electrode, the distance from the silicide contact portion to the wiring layer and the distance from the silicide gate electrode to the wiring layer can be made the same. For this reason, for example, the contact means has a multistage structure, and a plurality of contact openings are formed so as to penetrate the interlayer insulating film existing between the silicide gate electrode and the wiring layer and reach the silicide gate electrode and the silicide contact portion. In this case, the depths of these contact openings can be made the same. Therefore, even when the contact opening reaching the silicide gate electrode is formed partially off the silicide gate electrode, overetching does not occur, and the conductor and the silicide gate filled in the contact opening It is possible to prevent a direct contact with the electrode, prevent a variation in the resistance value of the gate due to the defect of the silicide gate electrode due to the contact of both, and obtain a semiconductor device having a stable gate resistance. it can. Further, it is possible to prevent the silicide gate electrode and the source / drain layer from being short-circuited due to over-etching, and it is possible to prevent a problem from occurring in the operation of the field effect transistor. For example, when the contact means has a multistage structure, the depth of each contact opening for electrical connection between the wiring layer and the source / drain layer can be reduced. Incomplete etching is prevented, and the problem that the contact resistance between the source / drain layer and the contact means increases can be prevented.

  According to the method of manufacturing a semiconductor device according to the sixth aspect of the present invention, the polysilicon layer and the gate polysilicon layer filled in the contact opening are simultaneously silicided to have the same height as the silicide gate electrode. Since the silicide contact portion is formed, the silicide contact portion can be obtained relatively easily.

<A. Embodiment 1>
<A-1. Device configuration>
As a semiconductor device according to the first embodiment of the present invention, FIG. 1 shows a cross-sectional configuration of a semiconductor device 100 including a MOS transistor (field effect transistor) having a FUSI gate.

  As shown in FIG. 1, a FUSI gate electrode 32 disposed on an active region defined by an element isolation insulating film 2 on a semiconductor substrate 1 such as a silicon substrate with a gate insulating film 31 interposed therebetween, and a FUSI A sidewall insulating film 33 disposed on the side surface of the gate electrode 32; a source / drain layer 34 disposed on the surface of the semiconductor substrate 1 outside both sides of the FUSI gate electrode 32 in the gate length direction; A MOS transistor 30 having a silicide layer 35 formed in the upper layer portion of the source / drain layer 34 is provided.

  An interlayer insulating film 4 is disposed so as to cover the MOS transistor 30, and penetrates the interlayer insulating film 4 in the thickness direction to the silicide layer 35 and the FUSI gate electrode 32 in the upper layer portion of the two source / drain layers 34. Two reaching FUSI contact portions 41 are provided.

  The FUSI contact portion 41 is configured by filling a fully-silicided FUSI contact layer 411 in a contact opening CH1 penetrating the interlayer insulating film 4, and has the same height as the FUSI gate electrode 32. ing.

  The thickness of the interlayer insulating film 4 is set such that the upper surface of the FUSI gate electrode 32 is exposed, and the upper surfaces of the FUSI gate electrode 32 and the FUSI contact portion 41 are exposed on the surface of the interlayer insulating film 4. An interlayer insulating film 5 is provided so as to cover the interlayer insulating film 4, and a plurality of contact plugs 51 that penetrate the interlayer insulating film 5 in the thickness direction and reach the two FUSI contact portions 41 are provided. Yes.

  The contact plug 51 is configured by filling, for example, tungsten (W) as the plug layer 511 into the contact opening CH2 penetrating the interlayer insulating film 5, and the inner surface of the contact opening CH2 is made of, for example, titanium nitride (TiN). ) And titanium (Ti), and the plug layer 511 is not in direct contact with the interlayer insulating film 5.

  On the interlayer insulating film 5, a wiring layer 7 patterned so as to cover the upper portion of each contact plug 51 is disposed.

  Since the wiring layer 7 and the source / drain layer 34 are electrically connected by the FUSI contact portion 41 and the contact plug 51, the FUSI contact portion 41 and the contact plug 51 may be collectively referred to as contact means. is there.

FIG. 2 shows a plan view of the semiconductor device 100 as viewed from above.
2 corresponds to FIG. 1, but as shown in FIG. 2, the contact plug 51 connected to the FUSI gate electrode 32 is one of the FUSI gate electrodes 32 in the gate width direction. Since the contact plug 51 is provided so as to be in contact with the end portion, the cross section of the contact plug 51 does not appear in FIG. However, in FIG. 1, the contact plug 51 connected to the FUSI gate electrode 32 is also shown in a sectional view for convenience.

  Further, as shown in FIG. 2, the FUSI contact portion 41 has a length approximately the same as the width of the source / drain layer 34 and is disposed so as not to protrude from the source / drain layer 34.

<A-2. Manufacturing method>
Next, a method for manufacturing the semiconductor device 100 will be described with reference to FIGS.

  First, in the step shown in FIG. 3, an element isolation insulating film 2 is provided in the main surface of the semiconductor substrate 1 to define an active region.

  Next, in the step shown in FIG. 4, HfSiON (hafnium silicate containing nitrogen) called a so-called Hi-k film is formed on the entire surface of the semiconductor substrate 1 by using, for example, atomic layer deposition (ALD). ) A high dielectric film HD1 such as a film is formed. This later becomes the gate insulating film 31. The material of the gate insulating film 31 is not limited to the above HfSiON, but may be a silicon oxide film or a silicon nitride film.

  Next, a polysilicon layer PS1 is formed on the entire surface of the high dielectric constant film HD1 by using, for example, a CVD (chemical vapor deposition) method. Here, the thickness of the polysilicon layer PS1 is set to a thickness of 20 to 100 nm.

  Next, a silicon nitride film SN1 is formed on the entire surface of the polysilicon layer PS1 by using, for example, a CVD method. The thickness of the silicon nitride film SN1 is about 1/3 to 1/5 of the thickness of the polysilicon layer PS1.

  Next, in the step shown in FIG. 5, the silicon nitride film SN1, the polysilicon layer PS1, and the high dielectric film HD1 are selectively removed sequentially using photolithography and dry etching to insulate the semiconductor substrate 1 on the gate. A laminated film LF of the film 31, the gate polysilicon layer 320 and the cap nitride film 21 is formed.

  The cap nitride film 21 is a layer provided as a cap for the gate polysilicon layer 320 in order to prevent the gate polysilicon layer 320 from being silicided in a later silicide process.

  Subsequently, a silicon nitride film is formed using, for example, a CVD method so as to cover the entire surface of the semiconductor substrate 1 including the stacked film LF, and then the silicon nitride film on the semiconductor substrate 1 is removed by dry etching. As shown in FIG. 6, a sidewall insulating film 33 is formed on the side surface of the laminated film LF.

  Then, using the laminated film LF on which the sidewall insulating film 33 is formed as an implantation mask, impurity ions are implanted into the surface of the semiconductor substrate 1, and the semiconductor substrate outside the both side surfaces in the gate length direction of the sidewall insulating film 33 is obtained. A source / drain layer 34 is formed in the surface of 1. The source / drain layer 34 extends below the side wall insulating film 33, but this portion is a source / drain extension layer formed prior to the formation of the source / drain layer 34. Since the method for manufacturing the source / drain extension layer is well known, the description thereof is omitted.

  Next, a refractory metal layer such as Ni (nickel) is formed by, for example, a sputtering method so as to cover the entire surface of the semiconductor substrate 1 including the laminated film LF on which the sidewall insulating film 33 is formed. A nickel silicide layer is formed by causing a silicide reaction with silicon. Since the silicide reaction does not occur with the insulating film, an unreacted refractory metal layer remains on the sidewall insulating film 33 and the cap nitride film 21 and is removed, as shown in FIG. Thus, the silicide layer 35 is formed only on the upper layer portion of the source / drain layer 34.

  Note that the refractory metal layer is not limited to Ni, and any suicide metal that causes a silicide reaction, such as Co (cobalt), titanium (Ti), tungsten (W), and molybdenum (Mo), can be used.

  Next, in the process shown in FIG. 7, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 by using, for example, a CVD method so as to completely cover the laminated film LF on which the sidewall insulating film 33 is formed. Then, the silicon oxide film is planarized by a CMP (Chemical Mechanical Polishing) method to obtain the interlayer insulating film 4. The interlayer insulating film 4 is planarized so that the upper surface of the cap nitride film 21 is exposed.

  Next, in the step shown in FIG. 8, the cap nitride film 21 is removed by wet etching, and the upper surface of the gate polysilicon layer 320 is exposed. It should be noted that the trace from which the cap nitride film 21 has been removed becomes a recessed portion RP.

  Next, in the step shown in FIG. 9, a contact opening CH1 reaching the silicide layer 35 disposed on the upper layer portion of the source / drain layer 34 is formed by photolithography and dry etching.

  Next, in the process shown in FIG. 10, a polysilicon layer is formed on the entire surface of the interlayer insulating film 4 by using, for example, a CVD method to fill the contact opening CH1, and then the polysilicon layer is etched back. A structure in which the polysilicon layer 410 is filled in the contact opening CH1 is obtained. In this step, the recess RP of the interlayer insulating film 4 is also filled with the polysilicon layer 410, and the polysilicon layer 410 covers the gate polysilicon layer 320. Here, the thickness of the polysilicon layer 410 is set to 20 to 100 nm.

  Next, in the step shown in FIG. 11, a refractory metal layer, here a Ni layer having a thickness of 50 to 200 nm, is formed by sputtering, for example, so as to cover the entire surface of the interlayer insulating film 4. A silicide reaction is caused to completely silicide the gate polysilicon layer 320 and the polysilicon layer 410.

  More specifically, after forming the Ni layer, a heat treatment is performed at 300 to 400 ° C. for 10 to 60 seconds to cause a silicide reaction.

  Thereafter, the unreacted Ni layer is removed by using an APM (Ammonia-Hydrogen Peroxide Mixture) solution and the like, and further heat treatment is performed at 500 to 600 ° C. for 10 to 60 seconds to obtain the gate polysilicon layer 320 and the polysilicon layer. 410 is completely silicided to form a FUSI gate electrode 32 and a FUSI contact layer 411, respectively.

  By performing the heat treatment twice in this manner, the gate polysilicon layer 320 and the polysilicon layer 410 can be completely silicided reliably.

  In FIG. 11, after the FUSI gate electrode 32 and the FUSI contact layer 411 are formed, the interlayer insulating film 4 including the FUSI gate electrode 32 and the FUSI contact layer 411 is further polished by the CMP method.

  The polishing thickness at this time is set to a thickness corresponding to the thickness of the silicided portion of the polysilicon layer 410 formed on the gate polysilicon layer 320. Note that the portion may be used as the FUSI gate electrode 32 without being removed by polishing, but the planarity can be improved by polishing the interlayer insulating film 4 again after the silicide process.

  Here, the final thickness of the FUSI gate electrode 32 is 20 to 100 nm, and the gate length is about 40 nm.

  Next, in the step shown in FIG. 12, a silicon oxide film is formed on the entire surface of the interlayer insulating film 4 by using, for example, the CVD method, and then the silicon oxide film is planarized by the CMP method to obtain the interlayer insulating film 5. .

  Subsequently, a plurality of contact openings CH2 penetrating the interlayer insulating film 5 and reaching the two FUSI contact portions 41 and the FUSI gate electrode 32 are formed by using photolithography and dry etching.

  Thereafter, a TiN layer is formed on the entire surface of the interlayer insulating film 5 by using, for example, a CVD method, and a Ti layer is laminated thereon by using, for example, a sputtering method to cover the inner surface of the contact opening CH2. Then, a W layer is formed on the Ti layer by, for example, a CVD method, thereby filling the contact opening CH2 with the W layer.

  Subsequently, by removing the W layer, the Ti layer, and the TiN layer on the interlayer insulating film 5 by the CMP method, the contact plug 51 in which each contact opening CH2 is embedded with the multilayer metal layer 512 and the plug layer 511 is obtained. .

  Thereafter, a conductive layer is formed on the interlayer insulating film 5 with, for example, copper (Cu), and the conductive layer is patterned to cover the top of each contact plug 51 by using photolithography and dry etching. A wiring layer 7 is formed to obtain the configuration shown in FIG.

  Needless to say, the wiring layer 7 is not limited to the uppermost wiring layer, and may be formed in an interlayer insulating film further formed on the interlayer insulating film 5.

<A-3. Effect>
Prior to the description of the effects of the present invention, problems in the conventional semiconductor device will be described in more detail.

  FIG. 22 is a cross-sectional view showing a configuration of a conventional semiconductor device 90 including a MOS transistor having a FUSI gate.

  As shown in FIG. 22, a FUSI gate electrode 12 disposed on an active region defined by an element isolation insulating film 2 on a semiconductor substrate 1 such as a silicon substrate with a gate insulating film 11 interposed therebetween, and a FUSI Side wall insulating films 13 disposed on the side surfaces of the gate electrode 12 and source / drain layers 14 disposed on the surface of the semiconductor substrate 1 outside both side surfaces of the FUSI gate electrode 12 in the gate length direction, respectively. A MOS transistor 3 is provided.

  An interlayer insulating film 4 is disposed on the semiconductor substrate 1 so as to cover the MOS transistor 3, and penetrates the interlayer insulating film 4 in the thickness direction to reach the two source / drain layers 14 and the FUSI gate electrode 12. A plurality of contact portions 50 are provided.

  The contact portion 50 is filled with, for example, tungsten (W) as the plug layer 501 in the contact opening CH, and the inner surface of the contact opening CH is, for example, a laminated film of titanium nitride (TiN) and titanium (Ti). The plug layer 501 is not directly in contact with the interlayer insulating film 4.

  On the interlayer insulating film 4, a wiring layer 7 patterned so as to cover the upper part of each contact portion 50 is disposed.

FIG. 23 shows a plan view of the semiconductor device 90 as viewed from above.
23 corresponds to FIG. 22, but as shown in FIG. 23, the contact portion 50 connected to the FUSI gate electrode 12 is one of the FUSI gate electrodes 12 in the gate width direction. Since the contact portion 50 is provided so as to contact the end portion, the cross section of the contact portion 50 does not appear in FIG. However, in FIG. 22, for convenience, the contact portion 50 connected to the FUSI gate electrode 12 is also shown in a cross-sectional view.

  In the configuration shown in FIG. 22, the contact portion 50 reaching the FUSI gate electrode 12 and the contact portion 50 reaching the source / drain layer 14 have different depths, which may cause a problem as shown in FIG. 24. .

  That is, since the depth of the contact portion 50 reaching the source / drain layer 14 is deep, etching is incomplete when the contact opening CH is formed, and the area of the bottom surface of the contact opening CH is reduced. May increase the contact resistance between the source / drain layer 14 and the contact portion 50.

  Although any contact part 50 is formed at the same time, since the contact part 50 reaching the source / drain layer 14 is deep, the source / drain layer is formed even after the contact opening CH reaches the FUSI gate electrode 12. 14 does not reach the contact opening CH, and the etching of the interlayer insulating film 4 continues.

  When the contact opening CH reaches the FUSI gate electrode 12 accurately, the etching selectivity of the interlayer insulating film 4 with respect to the FUSI gate electrode 12 is large, so that the contact opening CH on the FUSI gate electrode 12 is Although it does not become deeper, if the contact opening CH is formed even partially away from the FUSI gate electrode 12, the interlayer including the sidewall insulating film 13 is included in the portion removed from the FUSI gate electrode 12. Etching of the insulating film 4 proceeds.

  A slit-like opening is provided along the side surface of the FUSI gate electrode 12 in a portion off the FUSI gate electrode 12, but there is a problem that the multilayer metal layer 502 cannot be reliably formed in the opening.

  That is, the multilayer metal layer 502 forms a barrier layer with TiN and forms an adhesion layer with the plug layer 501 with Ti, but these layers are not formed in the slit-shaped opening, and the plug layer 501 And FUSI gate electrode 12 may be in direct contact with each other.

  In such a case, silicon in the silicide reacts with tungsten, and the tungsten may absorb the silicon, so that the FUSI gate electrode 12 may be lost, and the resistance value of the gate may vary.

  When the plug layer 501 is filled in the slit-shaped opening, a part of the contact portion 50 extends along the side surface of the FUSI gate electrode 12 and comes into contact with the source / drain layer 14. There is a possibility that the gate electrode 12 and the source / drain layer 14 are short-circuited and the MOS transistor does not operate normally.

  Whereas the conventional semiconductor device has the problems as described above, in the semiconductor device of the first embodiment according to the present invention, as shown in FIG. Two FUSI contact portions 41 respectively reaching the silicide layer 35 on the upper layer of the one source / drain layer 34 are provided, and these have the same height as the FUSI gate electrode 32. A plurality of contact plugs 51 are provided so as to penetrate through the interlayer insulating film 5 disposed so as to cover the interlayer insulating film 4 and reach the two FUSI contact portions 41 and the FUSI gate electrode 32, respectively. The contact plug 51 is connected to the upper wiring layer 7.

  For this reason, the contact plug 51 connected to the FUSI contact portion 41 and the contact plug 51 connected to the FUSI gate electrode 32 have the same depth.

  Therefore, when the contact opening CH2 constituting the contact plug 51 is formed, even if the contact opening CH2 reaching the FUSI gate electrode 32 is formed partially off from the FUSI gate electrode 32, over-etching occurs. There is no. Therefore, direct contact between tungsten constituting the plug layer 511 and the FUSI gate electrode 32 is prevented, and the resistance value of the gate varies due to the loss of the FUSI gate electrode 32 due to the contact between both. Can be prevented, and a semiconductor device with stable gate resistance can be obtained.

  Further, it is possible to prevent the FUSI gate electrode 32 and the source / drain layer 34 from being short-circuited due to over-etching, and to prevent a malfunction in the operation of the MOS transistor.

  In addition, since the electrical connection between the wiring layer 7 and the source / drain layer 34 is performed via the FUSI contact portion 41 and the contact plug 51, the electrical connection between the wiring layer 7 and the source / drain layer 34 is Compared with the case of using a single contact plug, the depth of each contact opening can be reduced.

  Therefore, incomplete etching of the contact opening is prevented, and the problem that the contact resistance between the source / drain layer 34 and the contact part 41 increases can be prevented.

  9 to 11, after the FUSI gate electrode 32 and the FUSI contact layer 411 are formed, the interlayer insulating film 4 including the FUSI gate electrode 32 and the FUSI contact layer 411 is further polished by the CMP method. Therefore, the flatness is improved, and the interlayer insulating film 5 formed on the interlayer insulating film 4 can be formed relatively thin.

  In other words, if the flatness of the lower interlayer insulating film layer is not good and the unevenness is noticeable, the influence of the unevenness of the lower interlayer insulating film layer must be eliminated unless the interlayer insulating film formed on it is thick. However, when the flatness of the lower interlayer insulating film layer is good, the upper interlayer insulating film may be thin.

  If the thickness of the interlayer insulating film 5 is small, the etching depth of the contact opening CH2 constituting the contact plug 51 may be shallow, so that the effect of preventing incomplete etching is enhanced. The thickness of the interlayer insulating film 5 is set to 100 to 200 nm.

  Further, by forming the cap nitride film 21 on the gate polysilicon layer 320, the cap nitride film 21 serves as a standard for flattening the interlayer insulating film 4, so that the thickness control of the interlayer insulating film 4 can be easily performed.

  Further, by surrounding the gate polysilicon 320 layer with the cap nitride film 21 and the gate insulating film 33, the silicide layer 35 can be formed only on the source / drain layer 34 without siliciding the gate polysilicon layer 320. it can.

  The application of the present invention is not limited to the configuration in which the gate polysilicon 320 layer is surrounded by the cap nitride film 21 and the gate insulating film 33 of the silicon nitride film, but a silicon oxide film is formed instead of the cap nitride film 21. Needless to say, the gate insulating film 33 may be formed of a silicon oxide film.

<A-4. Modification>
In the above description, FIG. 2 is shown as a plan view of the semiconductor device 100 as viewed from above, and the FUSI contact portion 41 has the same length as the width of the source / drain layer 34, and Although described as being disposed so as not to protrude, the shape of the FUSI contact portion 41 in plan view is not limited thereto.

  That is, as shown in FIG. 13, the FUSI contact portion 41A is formed so as to protrude from the source / drain layer 34, and the contact plug 51 is formed in the portion of the FUSI contact portion 41A protruding from the source / drain layer 34. You may comprise so that it may connect.

  By adopting such a configuration, the degree of freedom of the position where the contact plug 51 is formed can be increased, the degree of freedom in pattern design of the wiring layer 7 connected to the contact plug 51 can be increased, and the semiconductor device can be downsized. be able to.

<B. Second Embodiment>
<B-1. Device configuration>
As a semiconductor device according to the second embodiment of the present invention, FIG. 14 shows a cross-sectional configuration of a semiconductor device 200 including a MOS transistor having a FUSI gate. Note that the same components as those of the semiconductor device 100 illustrated in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 14, in the semiconductor device 200, the wiring layer 7 patterned so as to be connected to the exposed surfaces of the two FUSI contact portions 41 and the FUSI gate electrode 32 is disposed on the interlayer insulating film 4. ing. The wiring layer 7 is disposed in the interlayer insulating film 5 disposed on the interlayer insulating film 4.

  Since the FUSI contact portion 41 electrically connects the wiring layer 7 and the source / drain layer 34, the FUSI contact portion 41 alone may be referred to as contact means.

FIG. 15 is a plan view of the semiconductor device 100 as viewed from above.
15 corresponds to FIG. 14, but the wiring layer 7 connected to the FUSI gate electrode 32 has one of the FUSI gate electrodes 32 in the gate width direction as shown in FIG. Since the wiring layer 7 is provided so as to be in contact with the end portion, the cross section of the wiring layer 7 does not appear in FIG. However, in FIG. 15, the wiring layer 7 connected to the FUSI gate electrode 32 is also shown in a sectional view for convenience.

  Further, as shown in FIG. 15, the FUSI contact portion 41 has the same length as the width of the source / drain layer 34 and is disposed so as not to protrude from the source / drain layer 34.

<B-2. Effect>
In the semiconductor device according to the second embodiment of the present invention described above, the same effects as those of the first embodiment can be achieved, and the wiring layer 7 can be directly connected to the FUSI contact portion 41 and the FUSI gate electrode 32. The contact plug 51 that is necessary in the semiconductor device 200 is not necessary, and the process for forming the contact plug 51 is not necessary, so that the manufacturing time can be shortened.

<B-3. Modification>
In the above description, FIG. 15 is shown as a plan view of the semiconductor device 200 as viewed from above, and the FUSI contact portion 41 has the same length as the width of the source / drain layer 34, and is on the source / drain layer 34. Although described as being disposed so as not to protrude, the shape of the FUSI contact portion 41 in plan view is not limited thereto.

  That is, as shown in FIG. 16, the FUSI contact portion 41A is formed so as to protrude from the source / drain layer 34, and the wiring layer 7 is connected to the portion of the FUSI contact portion 41A protruding from the source / drain layer 34. You may comprise as follows.

  By adopting such a configuration, the degree of freedom in pattern design of the wiring layer 7 connected to the contact plug 51 can be increased, and the semiconductor device can be downsized.

<C. Embodiment 3>
<C-1. Device configuration>
As a semiconductor device according to the third embodiment of the present invention, FIG. 17 shows a cross-sectional configuration of a semiconductor device 300 including a MOS transistor having a FUSI gate. Note that the same components as those of the semiconductor device 100 illustrated in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 17, the semiconductor device 300 is provided so as to penetrate the interlayer insulating film 5 disposed so as to cover the interlayer insulating film 4 and reach the FUSI contact portion 41 and the FUSI gate electrode 32, respectively. The semiconductor device 100 is the same as the semiconductor device 100 in that it has a plurality of contact plugs 51, but electrical connection between MOS transistors is performed using the FUSI wiring layer 42 formed in the same process as the FUSI contact portion 41. It has a configuration.

  That is, as shown in FIG. 17, the FUSI wiring layer 42 extends from the upper part of the source / drain layer 34 of the MOS transistor 30 to the upper part of the source / drain layer 34 of the adjacent MOS transistor 30A. It is arranged.

  The FUSI wiring layer 42 is simultaneously formed in the same process as the FUSI contact portion 41, and a completely silicided FUSI layer 412 is filled in a trench-like contact opening CH3 penetrating the interlayer insulating film 4 in the thickness direction. It has the same height as the FUSI gate electrode 32.

  Here, the MOS transistor 30A basically has the same configuration as the MOS transistor 30, and the same reference numerals are given to the same configurations as the MOS transistor 30.

  One source / drain layer 34 of the MOS transistor 30A is electrically connected to the source / drain layer 34 of the MOS transistor 30 through the FUSI wiring layer 42. The FUSI is also formed on the other source / drain layer 34. A wiring layer 42 is provided, and is configured to be electrically connected to a MOS transistor (not shown) via the FUSI wiring layer 42.

FIG. 18 shows a plan view of the semiconductor device 300 as viewed from above.
A sectional view taken along line BB in FIG. 18 corresponds to FIG. 17, but the contact plug 51 connected to the FUSI gate electrode 32 is in contact with one end of the FUSI gate electrode 32 in the gate width direction. Since the contact plug 51 is provided, the cross section of the contact plug 51 does not appear in FIG. However, in FIG. 18, the contact plug 51 connected to the FUSI gate electrode 32 is also shown in a cross-sectional view for convenience.

  As shown in FIG. 18, the semiconductor device 300 includes MOS transistors 30, 30A, and 30B. The MOS transistors 30 and 30A are arranged in a line in the gate length direction, and the MOS transistors 30A and 30B are mutually connected. A FUSI wiring layer 42 is disposed so that the gate length directions are parallel to each other and the source / drain layers 30 of the MOS transistors 30A and 30B facing each other are electrically connected. The MOS transistor 30B basically has the same configuration as that of the MOS transistor 30, and the same reference numerals are given to the same configurations as the MOS transistor 30. By adopting such a configuration, the MOS transistors 30 to 30B are connected in series.

<C-2. Effect>
In the semiconductor device according to the third embodiment of the present invention described above, the same effect as that of the first embodiment is obtained, and a MOS transistor is formed using the FUSI wiring layer 42 formed in the same process as the FUSI contact portion 41. Therefore, the wiring distance can be shortened compared to the case where the upper wiring layer 7 is used to electrically connect the MOS transistors, and the semiconductor device can be downsized.

  In the above description, the FUSI wiring layer has been described as electrically connecting the MOS transistors. However, the FUSI wiring layer is not limited to the connection between the MOS transistors. It goes without saying that a semiconductor element having at least one impurity layer can be connected by a FUSI wiring layer.

  Needless to say, in the semiconductor device 200 described in the second embodiment, electrical connection between adjacent semiconductor elements may be performed by a FUSI wiring layer.

<D. Embodiment 4>
<D-1. Device configuration>
As a semiconductor device according to the fourth embodiment of the present invention, FIG. 19 shows a cross-sectional configuration of a semiconductor device 400 including a MOS transistor having a FUSI gate. Note that the same components as those of the semiconductor device 100 illustrated in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 19, in the semiconductor device 400, the interlayer insulating film 6 disposed so as to cover the interlayer insulating film 4 is penetrated in the thickness direction to the FUSI contact portion 41 and the FUSI gate electrode 32. A wiring layer 8 having a contact portion 8a provided so as to reach and a wiring portion 8b integrally formed with the contact portion 8a and disposed in the interlayer insulating film 6. The wiring layer 8 is a dual damascene. It is formed by the law.

  The contact portion 8a and the wiring layer 8b are made of copper (Cu), and have a barrier metal layer 8c made of TaN, for example, between the contact portion 8a and the wiring layer 8b and the interlayer insulating film 6, The material constituting the contact portion and the wiring layer is not in direct contact with the interlayer insulating film 6.

<D-2. Manufacturing method>
Next, a method for manufacturing the semiconductor device 400 will be described with reference to FIGS. The steps until the FUSI contact portion 41 shown in FIG. 20 is formed are the same as those of the semiconductor device 100 described with reference to FIGS.

  In the step shown in FIG. 20, a silicon oxide film is formed on the entire surface of the interlayer insulating film 4 by using, for example, a CVD method, and then the silicon oxide film is planarized by the CMP method to obtain the interlayer insulating film 6.

  Subsequently, a plurality of contact openings CH4 that penetrate the interlayer insulating film 5 in the thickness direction and reach the two FUSI contact portions 41 and the FUSI gate electrode 32 are formed by using photolithography and dry etching.

  Next, in the step shown in FIG. 21, a plurality of wiring trenches TR communicating with the plurality of contact openings CH4 are patterned using photolithography and dry etching.

  Here, the depth of the wiring trench TR is set to about 1/3 to 1/2 of the thickness of the interlayer insulating film 5, and is formed according to the wiring pattern of the wiring layer 8b to be formed later.

  Thereafter, a TaN layer is formed on the entire surface of the interlayer insulating film 6 by, for example, a sputtering method to form a barrier metal layer BM, and the inner surfaces of the plurality of contact openings CH4 and the plurality of wiring trenches TR are covered with the barrier metal layer BM. Then, a copper layer ML is formed on the entire surface of the interlayer insulating film 6 by a CVD method or a plating method, and the plurality of contact openings CH4 and the plurality of wiring trenches TR are filled with the copper layer ML.

  Subsequently, by removing the copper layer ML and the barrier metal layer BM on the interlayer insulating film 6 by CMP, the wiring layer 8 having the contact portion 8a, the wiring layer 8b, and the barrier metal layer 8c shown in FIG. obtain.

<D-3. Effect>
The semiconductor device according to the fourth embodiment of the present invention described above has the same effects as those of the first embodiment, and the contact portion 8a and the wiring layer 8b are formed by the dual damascene method. As in the case of the contact plug 51 of the semiconductor device 100, the number of processes can be reduced and the manufacturing time can be reduced as compared with the case where the contact portion connected to the FUSI contact portion 41 and the FUSI gate electrode 32 is formed alone.

It is sectional drawing which shows the structure of the semiconductor device of Embodiment 1 which concerns on this invention. It is a top view which shows the structure of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 1 which concerns on this invention. It is a top view which shows the structure of the modification of the semiconductor device of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the structure of the semiconductor device of Embodiment 2 which concerns on this invention. It is a top view which shows the structure of the semiconductor device of Embodiment 2 which concerns on this invention. It is a top view which shows the structure of the modification of the semiconductor device of Embodiment 2 which concerns on this invention. It is sectional drawing which shows the structure of the semiconductor device of Embodiment 3 which concerns on this invention. It is a top view which shows the structure of the semiconductor device of Embodiment 3 which concerns on this invention. It is sectional drawing which shows the structure of the semiconductor device of Embodiment 4 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 4 which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of Embodiment 4 which concerns on this invention. It is a figure which further demonstrates the problem of the conventional semiconductor device. It is a figure which further demonstrates the problem of the conventional semiconductor device. It is a figure which further demonstrates the problem of the conventional semiconductor device.

Explanation of symbols

4, 5, 6 Interlayer insulating film, 7, 8 wiring layer, 8a contact portion, 8b wiring portion, 21 cap nitride film, 31 gate insulating film, 33 sidewall insulating film, 34 source / drain layer, 35 silicide layer, 41 Silicide contact portion, 42 silicide wiring layer, 51 contact plug, 320 gate polysilicon layer, 410 polysilicon layer, RP recess, CH1 contact opening.

Claims (8)

A field effect transistor disposed on a semiconductor substrate and having a silicide gate electrode made of silicide;
An interlayer insulating film covering the semiconductor substrate including the field effect transistor;
A wiring layer disposed on the interlayer insulating film;
Contact means provided so as to penetrate the interlayer insulating film in the thickness direction, and electrically connecting the wiring layer and the source / drain layer of the field effect transistor;
The contact means includes
A silicide contact portion disposed on the source / drain layer and made of the silicide;
The height of the silicide contact portion is the same as that of the silicide gate electrode. The interlayer insulating film is
A first interlayer insulating film covering the field effect transistor such that an upper surface of the silicide gate electrode is exposed;
A second interlayer insulating film disposed on the first interlayer insulating film,
The silicide contact portion is
Penetrating through the first interlayer insulating film in the thickness direction, the upper surface thereof is exposed,
The contact means includes
A contact plug penetrating through the second interlayer insulating film in the thickness direction and having a lower surface in contact with the upper surface of the silicide contact portion and an upper surface exposed;
The semiconductor device according to claim 1, wherein the wiring layer is disposed on the second interlayer insulating film so as to cover the upper surface of the contact plug. The silicide contact portion is
Penetrating the interlayer insulating film in the thickness direction, the upper surface thereof is exposed,
The semiconductor device according to claim 1, wherein the wiring layer is disposed on the interlayer insulating film so as to cover the upper surface of the silicide contact portion. The interlayer insulating film is
A first interlayer insulating film covering the field effect transistor such that an upper surface of the silicide gate electrode is exposed;
A second interlayer insulating film disposed on the first interlayer insulating film,
The silicide contact portion is
Penetrating through the first interlayer insulating film in the thickness direction, the upper surface thereof is exposed,
The wiring layer is
A contact portion that penetrates through the second interlayer insulating film in the thickness direction, and a lower surface of which contacts the upper surface of the silicide contact portion;
The semiconductor device according to claim 1, further comprising: a wiring portion that is disposed in an upper layer portion of the second interlayer insulating film so as to be integrated with the contact portion, and an upper surface of which is exposed. A semiconductor element having at least one impurity layer disposed in a surface of the semiconductor substrate;
A silicide wiring layer composed of the silicide and disposed to extend from the source / drain layer to the impurity layer of the semiconductor element;
The semiconductor device according to claim 1, wherein a height of the silicide wiring layer has the same height as the silicide gate electrode. (a) selectively forming a laminated film of at least a gate insulating film and a gate polysilicon layer on a semiconductor substrate;
(b) forming a sidewall insulating film on the side surface of the laminated film;
(c) performing ion implantation of impurities using the stacked film and the sidewall insulating film as a mask to form source / drain layers in the surface of the semiconductor substrate;
(d) after the step (c), forming an interlayer insulating film on the semiconductor substrate so as to cover the laminated film on which the sidewall insulating film is formed;
(e) forming a contact opening that reaches the source / drain layer through the interlayer insulating film;
(f) filling the contact opening with a polysilicon layer;
(g) The polysilicon layer and the gate polysilicon layer filled in the contact opening are completely silicided, and are formed of a silicide contact portion and silicide that penetrates the interlayer insulating film and reaches the silicide layer. Forming a silicide gate electrode. A method for manufacturing a semiconductor device. The step (g)
Forming a silicide metal layer on the entire surface of the interlayer insulating film, and then performing a heat treatment at 300 to 400 ° C. for 10 to 60 seconds;
The method for manufacturing a semiconductor device according to claim 6, further comprising a step of performing a heat treatment at 500 to 600 ° C. for 10 to 60 seconds after removing the unreacted silicide metal layer. The step (a)
Forming a cap nitride film serving as a cap on the gate polysilicon layer;
The step (b)
Forming the sidewall insulating film with a silicon nitride film,
The step (d)
Planarizing the interlayer insulating film until an upper surface of the cap nitride film is exposed;
Prior to step (e),
The method of manufacturing a semiconductor device according to claim 6, further comprising a step of removing the cap nitride film and forming a recess in which the gate polysilicon layer is exposed at a bottom.

Images