JP2007141440A - Mram reference cell sub-array and its manufacturing method, mram array, mram cell sub-array and its manufacturing method, mram cell sub-array writing device, and mram cell sub-array writing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an MRAM array which performs more stable data read-out operation. <P>SOLUTION: A reference cell sub-array 200 having: a plurality of reference cells 205 arranged in rows and columns; a bit lines couple consisting of bit lines 207, 208; and a connection section 270 connecting the bit lines 207, 208 each other, is included. The reference cells 205 of a first column arranged along the bit line 207 are connected in parallel with the reference cells 205 of a second column arranged along the bit line 208, and the reference cells 205 of the first and second columns positioned on the same row are in a magnetized state different each other. Thus, a stable reference current based on the plurality of reference cells 205 is provided. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an MRAM reference cell subarray having a plurality of magnetic tunnel junction elements, an MRAM array, an MRAM cell subarray, an MRAM cell subarray writing device, a method of manufacturing such an MRAM reference cell subarray, and a method of manufacturing an MRAM cell subarray , And an MRAM cell sub-array writing method.

  Conventionally, volatile memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) have been used as general-purpose memories used in information processing apparatuses such as computers and mobile communication devices. These volatile memories lose all information unless they are constantly supplied with current. For this reason, it is necessary to separately provide a non-volatile memory (for example, a flash EEPROM) as a means for storing the situation. Since this nonvolatile memory is strongly required to increase the processing speed, in recent years, a magnetic random access memory (MRAM) has attracted attention as a nonvolatile memory.

  The MRAM has an array structure in which a plurality of magnetic memory cells including magnetoresistive elements are arranged in a matrix so as to form rows and columns. As the magnetoresistive effect element, a magnetic tunnel junction (MTJ) element that can obtain a larger resistance change rate is suitable. This MTJ element consists of two ferromagnetic layers separated by a tunnel barrier layer (a magnetization free layer whose magnetization direction changes according to the applied magnetic field and a permanent magnetization so that the magnetization direction is parallel to the easy axis) Magnetized pinned layer). Although the magnetization free layer has a freely rotatable magnetization direction, it is stable in terms of energy when the magnetization direction is aligned along the easy magnetization axis exhibiting magnetocrystalline anisotropy. The tunnel barrier layer is a thin film made of an insulating material and has a thickness that allows charge carriers (generally electrons) to pass through the tunnel effect based on quantum mechanics. Since the probability that charge carriers are transmitted depends on the electron spin direction associated with the magnetization directions of the two ferromagnetic layers, the tunnel current also changes when the magnetization direction changes in a state where a voltage is applied. The magnitude of the tunnel current depends on the ratio of up spin to down spin.

  FIG. 14 shows an example of a cross-sectional structure of the magnetic memory cell 10. Each magnetic memory cell 10 has an MTJ element 15 provided between a bit line 25 and a write word line 30 which are orthogonal to each other without being in contact with each other. The MTJ element 15 has a free layer 18, a tunnel barrier layer 17, and a pinned layer 16 in this order from the bit line 25 side. The direction of the magnetization J18 of the free layer 18 changes according to the external magnetic field, while the direction of the magnetization J16 of the pinned layer 16 is fixed in a specific direction (for example, a direction along the bit line 25). The direction of the magnetization J16 is determined in the manufacturing process of the MTJ element 15. Each magnetic memory cell 10 holds digital data corresponding to the relative directions of the magnetization J16 and the magnetization J18 in the MTJ element 15.

  The free layer 18 located on one side of the MTJ element 15 is in direct contact with the bit line 25, but a conductive wire 45 is provided between the MTJ element 15 and the write word line 30 so as to be in contact with the pinned layer 16. It has been. The write word line 30 is arranged in the vicinity thereof without making electrical contact with the MTJ element 15. A write word line current 40 flows through the write word line 30 in a certain direction. A magnetic field is formed by the write bit line current 35 flowing through the bit line 25 and the write word line current 40 flowing through the write word line 30, and the direction of the magnetization J18 of the free layer 18 is determined. The state of the digital data is determined by the direction of the magnetization J18. An isolation transistor 20 (hereinafter simply referred to as the transistor 20) is provided at one end of the conducting wire 45 connected to the pinned layer 16. The source of the transistor 20 is grounded, and the gate of the transistor 20 is connected to the read word line 50.

  When writing to the magnetic memory cell 10, the write bit line current 35 is caused to flow through the bit line 25 and the write word line current 40 is caused to flow through the write word line 30. At this time, the direction of the write bit line current 35 determines the direction of the magnetization J18 of the free layer 18. As a result, digital data corresponding to the relative directions of the magnetization J16 and the magnetization J18 in the MTJ element 15 is recorded in the MTJ cell 10. During the write operation, the transistor 20 is deactivated through the read word line 50 to prevent the current from the bit line 25 from flowing through the MTJ element 15 and the like.

  In the read operation, transistor 20 is activated by read word line 50, and read cell current 55 is applied to bit line 25, MTJ element 15 and transistor 20 as shown in FIG. 14B and FIG. Pass in order and ground. At this time, the resistance when passing through the MTJ element 15 is determined by the relative direction between the direction of the magnetization J18 of the free layer 18 and the direction of the magnetization J16 of the pinned layer 16. FIG. 15 is a circuit diagram corresponding to the magnetic memory cell 10 shown in FIG. As described above, the bit line 25 is related to the read operation from the MTJ cell 10 as well as the write operation for determining the direction of the magnetization J18 of the free layer 18.

  A read operation in the conventional MRAM will be described in detail with reference to the circuit diagram of FIG. In the read operation, the read cell current 55 passes through the magnetic memory cell 10 to be read. When the write cell current 55 passes through the MTJ element 15, the data voltage Vdat which is the first input signal input to the sense amplifier 60 is formed. On the other hand, the reference voltage Vref is input to the sense amplifier 60 as the second input signal. The reference voltage Vref is generated by a reference current 75 that flows through a reference cell 65 provided separately from the magnetic memory cell 10 and is grounded. The reference cell 65 is connected to the bit line 70, and a reference current 75 is supplied by the bit line 70. Further, the reference cell 65 is configured such that an MTJ element 67a and an MTJ element 69a connected in series and an MTJ element 67b and an MTJ element 69b connected in series are connected in parallel. The MTJ elements 67a and 67b are magnetized to have a low resistance, and the MTJ elements 69a and 69b are magnetized to have a high resistance. The MTJ elements 67a and 67b and the MTJ devices 69a and 69b are connected so that the midpoint resistance is equivalent. The data voltage Vdat is compared with the reference voltage Vref to determine the state of the digital data stored in the magnetic memory cell 10.

  The following technologies are known as techniques relating to such an MRAM array.

DeBrosse et al. Discloses a 16 megabit MRAM array featuring a novel bootstrap write drive circuit (see, for example, Non-Patent Document 1).
DeBrosse et al., “16Mb MRAM Featuring Bootstrapped Write Drivers”, Digest of Technical Papers, 2004 Symposium on VLSI Circuit, 2004 June, pp. 454-457

Brennan et al. Discloses a capacitively coupled sensor device used as an MRAM array (see, for example, Patent Document 1). The device (apparatus) fixes the offset voltage of the sense amplifier. The sense amplifier is selectively coupled to a selected bit line in the MRAM array, and communicates with the MRAM cell to be read using the selected bit line. The read current passes through the MRAM cell during the read operation, and the reference current passes through the selected bit line. A signal voltage is generated in response to the read current and the reference current and is sensed on the selected bit line. The signal voltage is tied to the input signal of the sense amplifier, and the sense amplifier supplies an output reflecting the data state of the MRAM cell.
US Pat. No. 6,816,403

Han et al. Disclose a reference cell that provides a voltage increase on the bit line. This reference cell is proportional to the voltage increase on other bit lines formed by a capacitively coupled thyristor (TCCT) based on an on-state memory cell, and preferably results in a voltage increase that is approximately half that. Is. The reference cell includes a negative differential resistance (NDR) device. A device such as a gate is disposed in the vicinity of the NDR device, and a first resistor connects the NDR device and the bit line.
US Pat. No. 6,845,037

In addition, the following technologies are known as technologies related to the MRAM array.
US Pat. No. 6,711,068 US Patent Application Publication No. 2004/0001360 US Pat. No. 6,754,123 US Pat. No. 6,791,887 US Pat. No. 6,791,890

  By the way, with respect to such an MRAM array, improvement in reading accuracy has been a problem. However, for example, as shown in FIG. 16, even in an MRAM array that performs reading using a reference current from a reference cell, it is difficult to say that sufficient reading accuracy is obtained.

  The present invention has been made in view of such problems, and a first object thereof is an MRAM array capable of performing a stable data reading operation, and an MRAM reference cell sub-array and an MRAM cell suitable for such an MRAM array. It is to provide a subarray. A second object of the present invention is to provide an MRAM reference cell subarray and a method for manufacturing the MRAM cell subarray as described above. Furthermore, a third object of the present invention is to provide an MRAM cell subarray writing apparatus and an MRAM cell subarray writing method suitable for writing data into the MRAM cell subarray as described above.

The MRAM reference cell sub-array of the present invention is used in an MRAM array having a plurality of MRAM data cell sub-arrays and a plurality of sense amplifiers, and supplies a reference current to the sense amplifiers. It is equipped with.
(A1) A plurality of MRAM reference cells arranged in the row direction and the column direction.
(A2) First and second bit lines extending in the column direction and connected to and adjacent to free layers included in a plurality of MRAM reference cells arranged in the column direction. Bit line pair.
(A3) A connecting portion for connecting the first and second bit lines in the bit line pair to each other.
Here, the MRAM reference cells in the first column aligned along the first bit line are connected in parallel to the second MRAM reference cells aligned along the second bit line, and are located in the same row. The MRAM reference cells in the first and second columns have different magnetization states.

A first MRAM array according to the present invention includes a plurality of MRAM data cell subarrays, a sense amplifier that communicates with the plurality of MRAM data cell subarrays, and a plurality of MRAM reference cell subarrays that supply a reference current to the sense amplifier. The MRAM reference cell subarray includes the following constituent elements B1 to B3.
(B1) A plurality of MRAM reference cells arranged in the row direction and the column direction.
(B2) First and second bit lines extending in the column direction and connected to and adjacent to free layers included in a plurality of MRAM reference cells arranged in the column direction. Bit line pair.
(B3) A connecting portion for connecting the first and second bit lines in the bit line pair to each other.
Here, the MRAM reference cells in the first column aligned along the first bit line are connected in parallel to the second MRAM reference cells aligned along the second bit line, and are located in the same row. The MRAM reference cells in the first and second columns have different magnetization states.

  In the MRAM reference cell sub-array and the first MRAM array of the present invention, the MRAM reference cells and the second MRAM reference cells in the first column have different magnetization states and are connected in parallel by a connecting portion. Therefore, a stable reference current based on a plurality of MRAM reference cells can be obtained.

The MRAM cell sub-array of the present invention is an MRAM cell sub-array used for an MRAM array together with a plurality of sense amplifiers, and has the following constituent elements C1 to C3.
(C1) A plurality of MRAM cells arranged in the row direction and the column direction.
(C2) A plurality of bit lines extending in the column direction and connected to the free layers included in the plurality of MRAM cells arranged in the column direction and arranged in the row direction.
(C3) A connecting portion that connects a pair of bit lines among a plurality of bit lines to form a bit line pair.
Here, the MRAM cells in the first column aligned along one bit line of the bit line pair are connected in parallel to the second MRAM cells aligned along the other bit line of the bit line pair. In addition, the MRAM cells in the first and second columns located in the same row have different magnetization states.

The second MRAM array of the present invention includes a plurality of MRAM cell subarrays and a sense amplifier that communicates with the plurality of MRAM cell subarrays, and includes the following constituent elements D1 to D3.
(D1) The MRAM cell sub-array is a plurality of MRAM cells arranged in the row direction and the column direction.
(D2) A plurality of bit lines extending in the column direction and connected to the free layers included in the plurality of MRAM cells arranged in the column direction and arranged in the row direction (D3) Of the plurality of bit lines A connecting portion that connects a pair of bit lines to each other to form a bit line pair.
Here, the MRAM cells in the first column aligned along one bit line of the bit line pair are connected in parallel to the second MRAM cells aligned along the other bit line of the bit line pair. In addition, the MRAM cells in the first and second columns located in the same row have different magnetization states.

  In the MRAM cell sub-array and the second MRAM array of the present invention, the MRAM cell in the first column and the MRAM cell in the second column have different magnetization states, and one set of a plurality of bit lines Since the bit lines are connected in parallel by the connecting portion to form a bit line pair, a stable reference current based on a plurality of MRAM cells can be obtained.

A method for manufacturing an MRAM reference cell subarray according to the present invention is a method for manufacturing an MRAM reference cell subarray that is used in an MRAM array having a plurality of MRAM data cell subarrays and sense amplifiers and supplies a reference current to the sense amplifiers. The following steps E1 to E4 are included.
(E1) A step of forming a plurality of MRAM reference cells so as to be arranged in the row direction and the column direction.
(E2) The bit is formed by arranging the first and second bit lines so as to be connected to and adjacent to the free layers included in the plurality of MRAM reference cells extending in the column direction and arranged in the column direction. Forming a line pair;
(E3) A connecting portion that connects the first and second bit lines in the bit line pair to each other is formed, and the first column of MRAM reference cells arranged along the first bit line and the second bit line A step of connecting in parallel a second MRAM reference cell lined up along.
(E4) A step of setting the MRAM reference cells in the first and second columns located in the same row to different magnetization states.

  In the manufacturing method of the MRAM reference cell sub-array of the present invention, the bit line pair having the first column MRAM reference cell and the second MRAM reference cell, which have different magnetization states and are connected in parallel by the connecting portion, is provided. As a result, a stable reference current based on a plurality of MRAM reference cells can be obtained.

The manufacturing method of an MRAM cell subarray of the present invention is a manufacturing method of an MRAM cell subarray used for an MRAM array together with a plurality of sense amplifiers, and includes the following steps F1 to F4.
(F1) A step of forming a plurality of MRAM cells so as to be arranged in the row direction and the column direction.
(F2) A step of forming a plurality of bit lines extending in the column direction and arranged in the row direction so as to be connected to the free layers included in the plurality of MRAM cells arranged in the column direction.
(F3) A bit line pair is formed by providing a connecting portion that connects one set of bit lines of a plurality of bit lines to each other, and the first column arranged along one bit line of the bit line pairs Connecting in parallel the MRAM cell and a second MRAM cell arranged along the other bit line of the bit line pair.
(F4) A step of setting one of the MRAM cells in the first and second columns located in the same row to a high resistance state and the other to a low resistance state.

  In the manufacturing method of the MRAM cell sub-array of the present invention, a bit line pair having a first column MRAM cell and a second MRAM cell that have different magnetization states and are connected in parallel by a connecting portion is obtained. Thus, a stable reference current based on a plurality of MRAM cells can be obtained.

The MRAM cell sub-array writing device of the present invention includes a holding body for holding a substrate on which a plurality of MRAM cell sub-arrays and sense amplifiers connected so as to be communicable with each other, a MRAM cell sub-array connected to the MRAM cell sub-array, A control device that controls the MRAM cell subarray so as to be separated from the magnetic field generator, a magnetic field generator that generates a magnetic field in a predetermined direction with respect to the MRAM cell subarray, and a writing device that performs writing to the MRAM cell subarray, The MRAM cell sub-array has the following constituent elements G1 to G3.
(G1) A plurality of MRAM cells arranged in the row direction and the column direction.
(G2) A plurality of bit lines extending in the column direction and connected to free layers included in the plurality of MRAM cells arranged in the column direction and arranged in the row direction.
(G3) A connecting portion that connects a pair of bit lines among a plurality of bit lines to form a bit line pair.
Here, the MRAM cells in the first column aligned along one bit line of the bit line pair are connected in parallel to the second MRAM cells aligned along the other bit line of the bit line pair. The writing device, when writing to the MRAM cell sub-array, passes a write current for the free layer to one bit line of the bit line pair in the first direction and then passes through the coupling portion. And function to lead to the other bit line of the bit line pair in the second direction.

  In the MRAM cell sub-array writing device of the present invention, the MRAM cell in the first column and the second MRAM cell are connected in parallel, and flowed in the first direction to one bit line of the bit line pair. After that, a plurality of MRAM references are provided because the writing device functioning to guide the other bit line of the pair of bit lines to the second direction opposite to the first direction is provided via the connecting portion. A stable reference current based on the cell is obtained.

  The MRAM cell sub-array writing method of the present invention includes a plurality of MRAM cells arranged in the row direction and the column direction, and a free layer extending in the column direction and included in the plurality of MRAM cells arranged in the column direction. A plurality of bit lines that are connected to each other and arranged in the row direction, and a pair of bit lines of the plurality of bit lines connected to each other to form a bit line pair. A method for writing to a communicably connected MRAM cell sub-array, the step of separating a selected MRAM cell to be written from a plurality of MRAM cells from a sense amplifier, and a free layer of the selected MRAM cell Forming a magnetic field indicating the direction in which the magnetization is in a desired direction, placing the magnetic field in the vicinity of the selected MRAM cell, and writing bits to the free layer. A line current is caused to flow in one bit line of the bit line pair in the first direction, and then is passed through the connecting portion, and the second bit line in the bit line pair is opposite to the first direction in the second direction. And a step of flowing in the direction of.

  In the writing method of the MRAM cell sub-array of the present invention, the write bit line current for the free layer is caused to flow in the first direction to one bit line of the bit line pair, and then the bit line is passed through the connecting portion. Since the other bit line of the pair is caused to flow in the second direction, a stable reference current based on a plurality of MRAM reference cells can be obtained.

  According to the MRAM reference cell sub-array of the present invention, since the MRAM reference cell and the second MRAM reference cell in the first column have different magnetization states and are connected in parallel by the connecting portion, A stable reference current based on the MRAM reference cell can be obtained. Therefore, according to the first MRAM array of the present invention using this MRAM reference cell subarray, a highly accurate read operation can be performed based on a stable reference current.

  According to the MRAM cell sub-array of the present invention, the MRAM cell in the first column and the MRAM cell in the second column have different magnetization states, and one set of bit lines of the plurality of bit lines is Since the bit line pairs are configured in parallel by the connecting portion, a stable reference current based on a plurality of MRAM cells can be obtained. Therefore, according to the second MRAM array of the present invention using this MRAM cell sub-array, a highly accurate read operation can be performed based on a stable reference current.

  According to the manufacturing method of the MRAM reference cell subarray of the present invention, the bit line having the MRAM reference cells and the second MRAM reference cells in the first column having different magnetization states and connected in parallel by the connecting portion Since a pair can be manufactured, an MRAM reference cell sub-array that can obtain a stable reference current based on a plurality of MRAM reference cells can be realized.

  According to the manufacturing method of the MRAM cell sub-array of the present invention, a bit line pair having a first column MRAM cell and a second MRAM cell that have different magnetization states and are connected in parallel by a connecting portion is manufactured. Therefore, it is possible to realize an MRAM cell sub-array that can obtain a stable reference current based on a plurality of MRAM cells.

  According to the MRAM cell sub-array writing device of the present invention, the MRAM cell in the first column and the second MRAM cell are connected in parallel, and one bit line of the bit line pair is connected in the first direction. Since a writing device that functions to guide the second bit line of the pair of bit lines to the second direction opposite to the first direction is provided via the connecting portion after flowing, A stable reference current based on the MRAM reference cell can be obtained. Therefore, if this cell subarray writing device is applied to an MRAM array, a highly accurate read operation can be performed based on a stable reference current.

  According to the writing method of the MRAM cell sub-array of the present invention, the write bit line current for the free layer is passed through one bit line of the bit line pair in the first direction, and then passed through the connecting portion. Since the second bit line of the bit line pair is caused to flow in the second direction, an MRAM cell sub-array that can obtain a stable reference current based on a plurality of MRAM reference cells can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
First, the configuration of the magnetic memory cell array according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a schematic diagram showing the overall configuration of a magnetic memory cell array (hereinafter referred to as an MRAM array) 1 according to the present embodiment. The MRAM array 1 is used as a so-called semiconductor memory chip, and includes an upper array block 300 and a lower array block 305 arranged with a sense amplifier 330 interposed therebetween. Each of the upper and lower array blocks 300 and 305 has a plurality of MRAM data cell subarrays (hereinafter simply referred to as data cell subarrays) 100 arranged in a line. The upper and lower array blocks 300 and 305 are further provided with one MRAM reference cell subarray (hereinafter simply referred to as a reference cell subarray) 200 between them (for example, in the center).

  Further, upper write line group 310 and upper read write line group 315 are provided so as to sandwich upper array block 300, and are connected to each data cell subarray 100 and reference cell subarray 200 in upper array block 300, respectively. ing. Similarly, a lower write line group 325 and a lower read write line group 320 are provided so as to sandwich the lower array block 305, and are connected to each data cell subarray 100 and reference cell subarray 200 in the lower array block 305, respectively. Has been.

  The other ends of upper read write line group 315 and lower read write line group 320 are connected to sense amplifier 330. The sense amplifier 330 detects digital data of the selected data cell 105 (described later) in the selected data cell sub-array 100. The reference cell subarray 200 functions to generate a reference current and input it to the sense amplifier 330. The reference current is used to determine the digital data state of the data cell 105 of the selected data cell subarray 100 during the read operation. Digital data reproduced by the sense amplifier 330 is transferred to the data driver 360 and output as output data 365 to an external circuit. The digital data may be a single bit, or may have a data width of 8 bits, 16 bits, or 32 bits.

  The MRAM array 1 further includes an address bus 335, a word line decoder 350, column decoder sections 375a to 375d, a control decoder 355, and the like.

  The address bus 335 supplies a digital address word (address data), and is connected to the word line decoder 350 and the column decoder sections 375a to 375d. The word line decoder 350 decodes the digital address word to select the location of the data cell 500 that contains the desired digital data.

  Control decoder 355 receives digital timing signals and digital control signals from read / write control line 345 and clock line 340, and provides for word line decoder 350, column decoder sections 375a-375d, and upper and lower array blocks 300, 305. Provide the necessary timing and control signals. When digital data is read from the desired data cell 105 or written to the desired data cell sub-array 100 by the control decoder 355, the selected data cell sub-array 100 and the reference cell sub-array 200 corresponding thereto are set in the active state. Signal is formed.

  Next, the configuration of the data cell sub-array 100 will be described with reference to FIG. FIG. 2 is a schematic diagram showing a planar configuration of the data cell sub-array 100 and its periphery in the MRAM array 1.

  The data cell sub-array 100 includes a plurality of MRAM data cells (hereinafter simply referred to as data cells) 105 arranged and organized in columns and rows. FIG. 3 shows an example of a cross-sectional structure of the data cell 105. Each data cell 105 has an MTJ element 90 provided between a bit line 107 and a write word line 109 which are orthogonal to each other without being in contact with each other. The MTJ element 90 has a free layer 91, a tunnel barrier layer 92, and a pinned layer 93 in this order from the bit line 107 side. The direction of the magnetization J91 of the free layer 91 changes according to the external magnetic field, while the direction of the magnetization J93 of the pinned layer 93 is fixed in a specific direction (for example, a direction along the bit line 107). The direction of the magnetization J93 is determined in the manufacturing process of the MTJ element 90. Each data cell 105 holds digital data corresponding to the relative directions of magnetization J93 and magnetization J91 in the MTJ element 90.

  The free layer 91 located on one side of the MTJ element 90 is in direct contact with the bit line 107, but a conductor 94 is provided between the MTJ element 90 and the write word line 109 so as to be in contact with the pinned layer 107. It has been. The write word line 109 is arranged in the vicinity thereof without making electrical contact with the MTJ element 90. A write word line current Ir flows in the write word line 109 in a certain direction. A combined magnetic field is formed by the write bit line current Ic flowing through the bit line 107 and the write word line current Ir flowing through the write word line 109, and the direction of the magnetization J91 of the free layer 91 is determined. The state of the digital data is determined by the direction of the magnetization J91. An isolation transistor 95 (hereinafter simply referred to as a transistor 95) is provided at one end of the conducting wire 94 connected to the pinned layer 93. The source of the transistor 95 is grounded, and the gate of the transistor 95 is connected to the read word line 165.

Bit lines 107 (107 _a , 107 _b ,..., 107 _n−1 , 107 _n ) are provided so as to extend along the data cells 105 arranged in the column direction and in the row direction. Are connected to the free layer 91 of each data cell 105. Similarly, the write word lines 109 (109 _a , 109 _b ,..., 109 _n−1 , 109 _n ) extend along the data cells 105 aligned in the row direction and are aligned in the column direction. Is provided. Each write word line 109 is arranged close to the data cell 105.

One end of each bit line 107 is connected to the source of the block read / write select transistor 110 (110 _a , 110 _b ,..., 110 _n−1 , 110 _n ). The other end of each bit line 107 is connected to the drain of a block write selection transistor 115 (115 _a , 115 _b ,..., 115 _n−1 , 115 _n ). The drain of each block read / write select transistor 110 is connected to the read / write line 130. This read / write line 130 is included in upper read / write line group 315 and lower read / write line group 320 shown in FIG. On the other hand, the source of each block write selection transistor 115 is connected to the write line 135. This write line 135 is included in upper write line group 310 and lower write line group 325 shown in FIG. A block read / write select line 120 is connected to the gates of all the block read / write select transistors 110. Further, a block write selection line 125 is connected to the gates of all the block write selection transistors 115.

One end of each write word line 109 is all connected to the source of the block selection transistor 145. The other end of each write word line 109 is connected to the drain of a write row selection transistor 155 (155 _a , 155 _b ,..., 155 _m−1 , 155 _m ). The drain of the block selection transistor 145 is connected to the current source 140 of the row direction current, and the gate of the block selection transistor 145 is connected to the block selection line 150. The source of each row selection transistor 155 is grounded to a potential reference point, and the gate of each row selection transistor 155 is connected to a row selection write line 160 (160 _a , 160 _b ,..., 160 _m−1 , 160 _m ). Each is connected. Block select line 150 controls activation and deactivation of block select transistor 145. The block selection transistor 145 is for controlling the write word line current Ir flowing from the current source 140 so as to pass through the vicinity of the selected data cell 105. Row select write line 160 is used to control the active and inactive of row select transistor 155 to direct the write word line current from current source 140 through write word line 109.

The data cell subarray 100 is provided with read word lines 165 (165 _a , 165 _b ,..., 165 _m−1 , 165 _m ) along each row of the data cells 105. This read word line 165 is connected to the gate of the isolation transistor 95 of each data cell 105. Read word line 165 controls activation and deactivation of isolation transistors of data cells 105 arranged in the row direction. Data cell subarray 100 is activated during a reproducing operation for guiding a read current from bit line 107 so as to pass through MTJ element 90 (described later) of selected data cell 105.

  When performing a write operation to each row or each column of data cell 105, block read / write select transistor 110 is turned on (driven) using block read / write select line 120, and block write is performed. The block write selection transistor 115 is driven using the selection line 125. In such a state, the write bit line current Ic flows between the read write line 130 and the write line 135 via the bit line 107. The direction of the write bit line current Ic is determined by the state of the digital data to be written.

  When a write operation to the data cell 105 is performed, the block selection transistor 145 is set to be active by a signal from the block selection line 150. In such a state, the write word line current Ir in the row direction flows through the write line 109 selected from the current source 140. At this time, the row selection transistor 155 is activated so that the write word line current Ir flows through the predetermined write word line 109 by the selected row selection write line 160. The write word line current Ir in the row direction and the write bit line current Ic in the column direction form a combined magnetic field in the vicinity of the intersection, and the free layer 91 of the selected (desired) data cell 105 is generated by the combined magnetic field. The magnetization direction (described later) is set. In data cell 105 corresponding to a location where either write word line current Ir or write bit line current Ic does not flow, the magnetization direction of free layer 91 is not changed (not inverted). That is, in order to reverse the magnetization direction of the free layer 91 of the desired data cell 105, it is necessary that both the write word line current Ir and the write bit line current Ic corresponding to the position flow.

  In a read operation from a desired data cell 105 in data cell subarray 100, block read / write select transistors 110 corresponding to all blocks are turned on by block read / write select line 120. And the block write selection line 125 is set so that the block write selection transistor 115 is turned on. Further, read word line 165 is set to turn on isolation transistors 95 for selecting a desired row in data cell subarray 100. In such a state, the cell current 96 flows as shown in FIG. The cell current 96 is detected by the sense amplifier 330. The operation and function of the sense amplifier 330 will be described later.

  Next, the configuration of the reference cell subarray 200 will be described with reference to FIG. FIG. 4 is a schematic diagram showing a planar configuration of the reference cell sub-array 200 and its periphery in the MRAM array 1.

  The reference cell sub-array 200 includes a plurality of MRAM reference cells (hereinafter simply referred to as reference cells) 205 arranged and organized in columns and rows. Each reference cell 205 basically has the same cross-sectional structure as the data cell 105 as shown in FIG. However, each reference cell 205 has an MTJ element 90 between a bit line 207 (or bit line 208) and a write word line 209 which are orthogonal to each other without being in contact with each other. The MTJ element 90 has a common configuration with the data cell 105. The gate of transistor 95 is connected to read word line 265.

In the reference cell sub-array 200, bit lines 207 (207 _a , 207 _b ,..., 207 _n−1 , 207 extend along the reference cells 205 aligned in the column direction and are aligned in the row direction. _n ) and bit lines 208 (208 _a , 208 _b ,..., 208 _n−1 , 208 _n ) are provided. The bit lines 207 and 208 are connected to the free layer 91 of the reference cell 205, respectively. The column of the reference cells 205 corresponding to the bit line 207 and the column of the reference cells 205 corresponding to the bit line 208 form a pair, and the bit line 207 and the bit line 208 that are paired are connected by the connecting unit 270, respectively. Are connected to each other. That is, the reference cells 205 in the first column aligned along the bit line 207 are connected in parallel with the second reference cells aligned along the bit line 208. Here, of a pair of reference cells 205 located in the same row, one is programmed to have a magnetization direction corresponding to a state showing a high resistance value, and the other has a magnetization direction corresponding to a state showing a low resistance value. Programmed to have. Note that the reference cell 205 is selectively programmed to be in either a high resistance state or a low resistance state.

In the reference cell sub-array 200, write word lines 209 (209 _a , 209 _b ,..., 209 _n−1) extend along the reference cells 205 aligned in the row direction and are aligned in the column direction. , 209 _n ). Each write word line 209 is arranged close to the reference cell 205.

  One end of each of bit lines 207 and 208 is connected to each source of block read / write select transistors 211 and 212, and the other end is connected to each drain of block write select transistors 215 and 216, respectively. Each is connected. The drains of the block read / write selection transistors 211 and 212 are connected to the read / write line 230, respectively, and the sources of the block write selection transistors 215 and 216 are connected to the write line 235, respectively. Read write line 230 is included in upper read write line group 315 and lower read write line group 320 shown in FIG. 1, and write line 135 is an upper write line group shown in FIG. 310 and the lower write line group 325.

  The gates of all the block read / write selection transistors 212 are connected to the block read / write reference selection line 220. Each drain of the block read / write select transistor 212 is connected to the bit line 208. The gates of all the block read / write select transistors 211 are connected to the block read / write reference select line 222. Each drain of the block read / write select transistor 211 is connected to the bit line 207.

  Further, the block write reference selection line 225 is connected to the gates of all the block write selection transistors 215, and the source of the block write selection transistor 215 is connected to the bit line 207. Further, the block write reference selection line 227 is connected to the gates of all the block write selection transistors 216, and the source of the block write selection transistor 216 is connected to the bit line 208.

  In selecting an arbitrary MRAM reference cell sub-array 200, the block read / write reference selection lines 220 and 222 and the block write reference selection lines 225 and 227 make the bit lines 207 and 208 selected (active), respectively. To be used).

One end of each write word line 209 is all connected to the source of the block selection transistor 245. The other end of each write word line 209 is connected to the drain of a write row selection transistor 255 (255 _a , 255 _b ,..., 255 _m−1 , 255 _m ). The drain of the block selection transistor 245 is connected to the current source 240 of the row direction current, and the gate of the block selection transistor 245 is connected to the block selection line 250. Each source of the row selection transistor 255 is grounded, and each gate of the row selection transistor 255 is connected to a row selection write line 260 (260 _a , 260 _b ,..., 260 _m−1 , 260 _m ), respectively. It is connected. The block selection line 250 controls the block selection transistor 245 to be in an active state or an inactive state, and the write word line current flowing from the current source 240 to the write line 209 in the reference cell 205 of the selected row. Ir is allowed to flow. The row selection write line 260 controls the active and inactivity of the row selection transistor 255 so that the write word line current Ir from the current source 240 passes through the desired write line 209.

The reference cell subarray 200 is provided with read word lines 265 (265 _a , 265 _b ,..., 265 _m−1 , 265 _m ) along each row of the reference cells 205. This read word line 265 is connected to the gate of the isolation transistor 95 of each reference cell 205. Read word line 265 controls the active and inactive states of isolation transistor 95. In the read operation, the active state is entered, and the cell current 96 is guided to flow from the bit lines 207 and 208 to the MTJ element 90 of the selected reference cell 205. A read operation and a write operation using the reference cell subarray 200 will be described later.

  FIG. 5 illustrates the control and data flow when reading digital data from the upper array block 300. In reading the digital data, an arbitrary data cell sub-array 100 in the upper array block 300 is selected. When a predetermined data cell sub-array 100 is selected from the upper array block 300, the reference cell sub-array 200 in the lower array block 305 is automatically attached. Column decoder sections 375b and 375c (FIG. 1) decode input digital address words to identify selected data cell subarray 100. After that, the column decoder sections 375b and 375c activate the read write line 130 corresponding to the selected data cell subarray 100, and the column of the data cell 105 in the selected data cell subarray 100 is connected to the read write line 130. Thus, the block read / write select transistor 110 is driven by the block read / write select line 120.

  Here, the word line decoder 350 (FIG. 1) decodes the input digital address word in order to determine the row of the selected data cell sub-array 100. Word line decoder 350 activates read word line 165 in order to read data from a desired row. Read word line 165 drives transistor 95 of each data cell 105 included in the selected row, so that cell current 96 passes from read write line 130 to MTJ element 90 in selected data cell 105. To. The control decoder 355 further deactivates the block write selection line 125 so that the write line 135 is blocked from all the bit lines 107 of the selected data cell sub-array 100.

  Column decoder section 375c activates upper read / write line 130 and drives block read / write select transistor 110 to connect the column of data cells 105 in selected data cell subarray 100 to read / write line 130. When the block read / write selection line 120 is set as described above, the read / write line 230 is similarly activated, and the block read / write reference selection lines 220 and 222 are activated, so that the block read / write select transistor is activated. 211 and 212 are turned on. Thus, read / write line 230 is connected to the column of reference cells 205 in the corresponding reference cell sub-array 200. The word line decoder 350 activates the selected read word line 265 and drives the transistor 95 in the reference cell 205 of the selected row in the reference cell subarray 200.

  The first bit line 107 (for example, 107a) in the data cell subarray 100 and the first bit line 207 (for example, 207a) in the reference cell subarray 200 are connected via the read / write line 130a and the read / write line 230a, respectively. Are connected to the sense amplifier 400a. Similarly, second bit line 107 (for example, 107b) in data cell subarray 100 and second bit line 208a in reference cell subarray 200 are connected via read write line 130b and read write line 230b, respectively. Are connected to the sense amplifier 400b.

  FIG. 6 shows that the inherent switching bias voltage 412 drives the transistors 405a, 405b, 407a and 407b of the sense amplifiers 400a and 400b, and the node voltages of these transistors 405a, 405b, 407a and 407b are represented in the data cell subarray. The figure shows that the bias voltage level necessary for the conductivity of the MTJ element 90 of the 100 data cells 105 and the reference cells 205 of the reference cell subarray 200 is maintained. Read / write lines 130a and 130b are set to bias voltage levels 420a and 420b, respectively. Bias voltage level 420a provides sense current 422a and bias voltage level 420b provides sense current 422b. The sense currents 422a and 422b flow from the bit line 107 of the data cell subarray 100 to the selected data cell 105. The magnitudes of the sense currents 422a and 422b are determined by the resistance of the MTJ element 90 in the selected data cell 105.

  Read / write lines 230a and 230b are set to reference bias voltage levels 425a and 425b, respectively. Reference bias voltage level 425a provides a reference current 427a, and reference bias voltage level 425b provides a reference current 427b. The reference current 427 a flows from the bit line 207 of the reference cell subarray 200 through the column of the selected reference cell 205. The magnitudes of the reference currents 427a and 427b are determined by the resistance of the MTJ element 90 in the column of the selected reference cells 205.

  In the reference cell subarray 200, the MTJ element 90 of the reference cell 205 of the bit line 207a is programmed to have a high resistance state, for example, so that the magnetization J91 of the free layer 91 is opposite to the magnetization J93 of the pinned layer 93. It is assumed that the MTJ element 90 of the reference cell 205 of the bit line 208a is programmed so that the magnetization J91 of the free layer 91 is in the same direction as the magnetization J93 of the pinned layer 93 and is in a low resistance state. In this case, the current IMTJH flowing through the reference cell 205 connected to the bit line 207a is lower than the current IMTJL flowing through the reference cell 205 connected to the bit line 208a. However, due to the presence of the connecting portion 270, the reference currents 427a and 427b are basically average values of the current IMTJH and the current IMTJL, respectively.

  The reference currents 427a and 427b behave as reference input currents to the sense amplifiers 400a and 400b. The sense currents 422a and 422b are applied to the sense amplifiers 400a and 400b, respectively. The sense amplifiers 400a and 400b are differential amplifiers, compare the sense currents 422a and 422b with the reference currents 427a and 427b, and determine the digital data state of the data cell subarray 100 at the outputs 415a and 415b.

  Read / write lines 130a and 130b are separated from the external circuit by external connection gate transistors 409a and 409b, and read / write lines 230a and 230b are separated from the external circuit by external connection gate transistors 409c and 409d. The functions of the external connection gate transistors 409a to 409d will be described later.

  FIG. 7 is a flowchart illustrating a read operation from a desired data cell 105 in the MRAM array 1 shown in FIG. First, the addresses are combined (step S700). Next, it is selected whether the data cell sub-array 100 to be read is in the upper array block 300 or the lower array block 305 (step S702). When the upper array block 300 is selected, the read write line 130 in the upper read write line group 315 is activated (step S704) and connected to the sense amplifier group 330. On the other hand, in the lower read / write line group 320, the read / write line 230 connected to the corresponding reference cell sub-array 200 is activated (step S706) and connected to the sense amplifier 330. Next, the read word line 165 corresponding to the selected data cell 105 is activated to turn on the transistor 95 of the data cell 105 (step S708). At the same time, the read word line 265 of the reference cell 205 corresponding to the selected data cell 105 is activated to turn on the transistor 95 of the reference cell 205 (step S710).

  In order to apply a bias to the MTJ element 90 in the selected data cell 105, a bias voltage is set for the read / write line 130 (step S712). Similarly, in order to apply a bias to the MTJ element 90 in the reference cell 205 corresponding to the selected data cell 105, a bias voltage is set for the read / write line 230 (step S714). Thereafter, the sense amplifier 330 detects a difference between the cell current flowing through the selected data cell 105 and the cell current flowing through the corresponding reference cell 205 (step S728). A voltage representing the digital data state of the selected data cell 105 is output from the sense amplifier 330 (step S730).

  When the lower array block 305 is selected, the read / write line 130 in the lower read / write line group 320 is activated (step S716) and connected to the sense amplifier group 330. On the other hand, in the upper read / write line group 315, the read / write line 230 connected to the corresponding reference cell sub-array 200 is activated (step S718) and connected to the sense amplifier 330. Next, the read word line 165 corresponding to the selected data cell 105 is activated to turn on the transistor 95 of the data cell 105 (step S720). At the same time, the read word line 265 of the reference cell 205 corresponding to the selected data cell 105 is activated to turn on the transistor 95 of the reference cell 205 (step S722).

  In order to apply a bias to the MTJ element 90 in the selected data cell 105, a bias voltage is set for the read / write line 130 (step S724). Similarly, in order to apply a bias to the MTJ element 90 in the reference cell 205 corresponding to the selected data cell 105, a bias voltage is set for the read / write line 230 (step S726). Thereafter, similarly, the sense amplifier 330 detects the difference between the cell current flowing through the selected data cell 105 and the cell current flowing through the corresponding reference cell 205 (step S728). A voltage representing the digital data state of the selected data cell 105 is output from the sense amplifier 330 (step S730).

  Next, a method for manufacturing the reference cell subarray 200 will be described. In manufacturing the reference cell sub-array 200, first, a plurality of reference cells 205 are formed so as to be aligned in the row direction and the column direction, and then a plurality of reference cells 205 extending in the column direction and aligned in the column direction. Bit lines 207 and 208 are formed so as to be connected to the free layer 91 included in each. At this time, the bit lines 207 and the bit lines 208 are alternately arranged in the column direction. Further, by forming a connecting portion 207 that connects the bit line 207 and the bit line 208, the reference cell 205 in the first column aligned along the bit line 207 and the second reference cell aligned along the bit line 208. 205 is connected in parallel. Finally, the reference cell subarray 200 is obtained by setting (programming) the reference cells 205 of the first and second columns located in the same row to different magnetization states.

  To set different magnetization states, for example, the first column of reference cells 205 along the bit line 207 is set to the high resistance state and the second column of reference cells 205 along the bit line 208 is set to the low resistance state. Or, the opposite setting.

  The reference cell subarray 200 is programmed in the inspection process. Hereinafter, a method for programming the reference cell 205 will be described in detail with reference to FIG. First, the block read / write selection lines 120 corresponding to all the data cell subarrays 100 in the upper array block 300 and the lower array block 305 are deactivated (step S750). Similarly, the block read / write reference selection lines 220 and 222 corresponding to all the reference cell subarrays 200 in the upper array block 300 and the lower array block 305 are deactivated (step S752). Next, the block selection line 250 is activated (step S754) and the selected write word line 209 is activated (step S756). Thereafter, the write word line current Ir is supplied from the current source 240 to the selected write word line 209 (step S758). Further, after the block write reference selection lines 225 and 227 are activated (step S760), the bit line current source (not shown) transfers to the bit line 207 which is one of the bit line 207 and the bit line 208 which form a pair. Write bit line current Ic is supplied (step S762). The write bit line current Ic flows into the other bit line 208 via the connecting portion 270 and flows through the bit line 208 (step S764). The combined magnetic field generated by the bit line current Ic and the word line current Ir acts so as to set the free layer 91 of the reference cell 205 at a crossing point of the bit line current Ic and the word line current Ir in a predetermined direction to perform writing ( Step S766). At this time, the write bit line current Ic flowing through one bit line 207 and the write bit line current Ic flowing through the other bit line 208 are relatively opposite to each other. One of the reference cells 205 in the first column along the line 207 and the reference cells 205 in the second column along the bit line 208 is in a high resistance state, and the other is in a low resistance state. Thereafter, it is confirmed that each reference cell 205 is programmed to a predetermined magnetization state (step S768). Specifically, the cell current 96 passing through the read word line 265 from the bit line 207 or the bit line 208 via each reference cell 205 is measured for each row to determine whether it is equivalent to the standard current. If the cell current 96 is not equivalent to the standard current (step S770), programming is performed again (step S772). If the cell current 96 is equivalent to the standard current (step S770), the write word line current Ir and the write bit line current Ic are stopped, and the sense amplifier 330 is reconnected to the corresponding reference cell 205. To complete.

  As described above, according to the MRAM array 1 of the present embodiment, the reference cells 205 and the second reference cells 205 in the first column have different magnetization states and are connected in parallel by the connecting portion 270. Therefore, a stable reference current based on the plurality of reference cells 205 along the bit lines 207 and 208 can be obtained, and a highly accurate read operation can be performed based on this.

[Second Embodiment]
Next, the configuration of the magnetic memory cell array according to the second embodiment of the present invention will be described with reference to FIGS.

  FIG. 9 is a schematic diagram showing an overall configuration of a magnetic memory cell array (hereinafter referred to as an MRAM array) 2 according to the present embodiment. The MRAM array 2 is used as a so-called semiconductor memory chip, and includes an upper array block 3605 and a lower array block 606 arranged with a sense amplifier 630 interposed therebetween. Each of the upper and lower array blocks 605 and 606 has a plurality of MRAM data cell subarrays (hereinafter simply referred to as data cell subarrays) 600a and 600b arranged in a line. Each data cell sub-array 600a, 600b has a pair of reference columns 515 in the center.

  Further, an upper write line group 610 and an upper read write line group 615 are provided so as to sandwich the upper array block 605, and are connected to each data cell sub-array 600a in the upper array block 605. Similarly, a lower write line group 625 and a lower read write line group 620 are provided so as to sandwich the lower array block 606, and are connected to each data cell sub-array 600b in the lower array block 306.

  The other ends of upper read write line group 615 and lower read write line group 620 are connected to sense amplifier 630. The sense amplifier 630 detects digital data of the selected data cell 500 (described later) in the selected data cell subarrays 600a and 600b. The reference string 515 functions to generate a reference current and input it to the sense amplifier 630. The reference current is used to determine the digital data state of the selected data cell 105 during the read operation. The digital data reproduced by the sense amplifier 630 is transferred to the data driver 660 and output as output data 665 to an external circuit. The digital data may be a single bit, or may have a data width of 8 bits, 16 bits, or 32 bits.

  The MRAM array 2 further includes an address bus 635, a word line decoder 650, column decoder sections 675a to 675d, a control decoder 655, and the like.

  The address bus 635 supplies a digital address word (address data), and is connected to the word line decoder 650 and the column decoder sections 675a to 675d. The word line decoder 650 decodes the digital address word to select the location of the data cell 500 that contains the desired digital data.

  Control decoder 655 receives digital timing signals and digital control signals from read / write control line 645 and clock line 640 and provides to word line decoder 650, column decoder sections 675a-675d, and upper and lower array blocks 605,606. Provide the necessary timing and control signals. When digital data is read from the desired data cell 500 or written to the desired data cell subarrays 600a and 600b by the control decoder 655, the selected data cell subarrays 600a and 600b and the corresponding reference column 515 are stored. A signal to activate is formed.

  Next, the configuration of the data cell sub-array 600 will be described with reference to FIG. FIG. 10 is a schematic diagram showing a planar configuration of the data cell sub-array 600 and its periphery in the MRAM array 2.

  Data cell sub-array 600 includes a plurality of MRAM data cells (hereinafter simply referred to as data cells) 500 arranged and organized in columns and rows. The structure of each data cell 500 is the same as the data cell 105 in FIG. However, each data cell 500 has the MTJ element 90 between the bit line 507 (or 508) and the write word line 509 which are orthogonal to each other without being in contact with each other. The gate of transistor 95 is connected to read word line 565.

The data cell sub-array 600 extends along the data cells 500 arranged in the column direction, and, as arranged in the row direction bit lines _{507 (507 a, 507 b,} ···, 507 n-1, 507 _n ) and bit lines 508 (508 _a , 508 _b ,..., 508 _n−1 , 508 _n ). Bit lines 507 and 508 are connected to the free layer 91 of the data cell 500, respectively. The column of the data cells 500 corresponding to the bit line 507 and the column of the data cells 500 corresponding to the bit line 508 make a pair, and the bit line 507 and the bit line 508 that are paired are connected by the connecting unit 580, respectively. Are connected to each other. In other words, the data cells 500 in the first column aligned along the bit line 507 are connected in parallel to the second data cells 500 aligned along the bit line 508. Here, one of the pair of data cells 500 located in the same row is programmed to have a magnetization direction corresponding to a state showing a high resistance value, and the other has a magnetization direction corresponding to a state showing a low resistance value. Programmed to have. Note that the data cell 500 is selectively programmed to be in either a high resistance state or a low resistance state.

The data cell sub-array 600 further includes write word lines 509 (509 _a , 509 _b ,..., 509 _n extending along the data cells 500 arranged in the row direction and arranged in the column direction. _-1, 509 _n) is provided. Each write word line 509 is arranged close to the data cell 500.

  One end of each of the bit lines 507 and 508 is connected to the respective sources of the block read / write selection transistors 520 and 521, and the other end is connected to the respective drains of the block write selection transistors 535 and 536. Each is connected. The drains of the block read / write selection transistors 520 and 521 are connected to the read / write line 530, and the sources of the block write selection transistors 535 and 536 are connected to the write line 545, respectively. Read write line 530 is included in upper read write line group 615 and lower read write line group 620 shown in FIG. 9, and write line 545 includes upper write line group shown in FIG. 610 and lower write line group 625 are included.

  The gate of the block read / write select transistor 521 in the data column 510 other than the reference column 515 is connected to the block read / write select line 522, and the gate of the block read / write select transistor 521 in the reference column 515 is connected to the block read. It is connected to the write reference selection line 524a. Each drain of the block read / write select transistor 521 is connected to the bit line 508.

  The gate of block read / write select transistor 520 in data column 510 other than reference column 515 is connected to block read / write select line 523, and the gate of block read / write select transistor 520 in reference column 515 is connected to block read. It is connected to the write reference selection line 524b. Each drain of the block read / write select transistor 520 is connected to the bit line 507.

  The block write selection line 537 is connected to the gate of the block write selection transistor 535 in the data column 510 other than the reference column 515, and the block write selection transistor 535 in the reference column 515 has a gate connected to the block. A write reference selection line 539a is connected. Each source of the block write selection transistor 535 is connected to the bit line 507.

  Further, the block write selection line 538 is connected to the gate of the block write selection transistor 536 in the data column 510 other than the reference column 515, and the block write selection transistor 536 in the reference column 515 has a gate connected to the block. A write reference selection line 539b is connected. Each source of the block write selection transistor 536 is connected to the bit line 508.

One end of each write word line 509 is all connected to the source of the block selection transistor 550. The other end of each write word line 509 is connected to the drain of a write row selection transistor 560 (560 _a , 560 _b ,..., 560 _m−1 , 560 _m ). The drain of the block selection transistor 550 is connected to the current source 555 of the row direction current, and the gate of the block selection transistor 550 is connected to the block selection line 575. Each source of the row selection transistor 560 is grounded, and each gate of the row selection transistor 560 is connected to a row selection write line 565 (565 _a , 565 _b ,..., 565 _m−1 , 565 _m ), respectively. It is connected. The block selection line 575 controls the block selection transistor 550 to be in an active state or an inactive state, and the write word line current flowing from the current source 555 to the write line 509 in the data cell 500 of the selected row. Ir is allowed to flow. Row select write line 565 controls the active and inactive states of row select transistor 560 so that write word line current Ir from current source 555 passes through desired write line 509.

The data cell sub-array 600 is provided with read word lines 570 (570 _a , 570 _b ,..., 570 _m−1 , 570 _m ) along each row of the data cells 500. This read word line 570 is connected to the gate of the isolation transistor 95 of each data cell 500. Read word line 570 controls the active and inactive states of isolation transistor 95. In the read operation, the active state is entered, and a cell current (not shown) is guided to flow from the bit lines 507 and 508 to the MTJ element 90 of the selected data cell 500. Read and write operations using data cell subarray 600 will be described later.

  FIG. 11 illustrates the control and data flow when reading digital data from the upper array block 605. In reading the digital data, an arbitrary data cell sub-array 600a in the upper array block 605 is selected. When a predetermined data cell sub-array 600a is selected from the upper array block 605, a pair of reference columns 515 included in the data cell sub-array 600b in the lower array block 606 are automatically attached. Column decoder sections 675b and 675c (FIG. 9) decode input digital address words to identify a pair of data columns 510 in selected data cell sub-array 600a. After that, the column decoder section 675c activates the upper read write lines 615a and 615b corresponding to the selected data cell subarray 600a, and the data column 510 in the selected data cell subarray 600a becomes the upper read write lines 615a and 615b. The block read / write select transistors 520 and 521 are driven by the block read / write select lines 522 and 523 so as to be connected to each other.

  Here, word line decoder 650 decodes the input digital address word in order to determine the row of selected data cell sub-array 600a to be read. Word line decoder 650 activates read word lines 570 in an active state in order to perform reading from a desired row. Read word line 570 drives transistor 95 of each data cell 500 included in the selected row. As a result, current passes from upper read write lines 615a and 615b to MTJ element 90 in selected data cell 500. Like that.

  Column decoder 675d inactivates block write selection lines 537 and 538, and blocks upper write lines 610a and 610b from bit lines 507 and 508 of selected data cell sub-array 600a.

  When word line decoder 650 and column decoder section 675c select data cell subarray 600a, column decoder section 675b selects a pair of corresponding reference columns 515 from data cell subarray 600b in lower array block 606. When the block read / write reference selection lines 524a and 524b are activated, the block read / write select transistors 520 and 521 are turned on. As a result, the bit lines 507 and 508 of the reference column 515 are connected to the lower read / write lines 620a and 620b. Word line decoder 650 activates selected read word line 570, and turns on the isolation transistor of data cell 205 in the selected column of data cell subarray 600b.

  A selected data column 510 in data cell subarray 600a is connected to a reference column 515 in data cell subarray 600b corresponding thereto, sense amplifier 630a via upper read / write lines 615a and 615b and lower read / write lines 620a and 620b. , 630b.

  Here, the inherent bias voltage 654 drives the gate transistors 631a, 631b, 633a, and 633b of the sense amplifier 630, and the node voltages of these gate transistors 631a, 631b, 633a, and 633b are used as data cells in the data cell subarrays 600a and 600b. The bias voltage level required for the conductivity of the 500 MTJ elements is maintained. Upper read / write lines 615a and 615b are each set to a bias voltage level of 400 mV in order to apply a bias to the MTJ element of data cell 500. The bias voltage 654 provides a sense current that flows from the bit lines 507, 508 of the selected data column 510 in the data cell subarray 600a to the data cells 500 in the selected row. The magnitude of the sense current is determined by the resistance of the MTJ element 90 in the selected data cell 500.

  Lower read / write lines 620a and 620b are set to the respective reference bias voltage levels. The reference bias voltage level provides a reference current. The reference current flows through the selected data cell 500 from the bit lines 507 and 508 extending in the column direction of the data cell sub-array 600b. The magnitude of the reference current is determined by the resistance of the MTJ element 90 in the selected data cell 500.

  In the data cell sub-array 600b, the MTJ element 90 of the data cell 500 of the bit line 507j (FIG. 10) is programmed so that, for example, the magnetization J91 of the free layer 91 is opposite to the magnetization J93 of the pinned layer 93. The MTJ element 90 of the data cell 500 of the bit line 508j (FIG. 10) is programmed so that the magnetization J91 of the free layer 91 is in the same direction as the magnetization J93 of the pinned layer 93, and the low resistance state is established. Suppose that In this case, the current flowing through the data cell 500 connected to the bit line 507j is lower than the current flowing through the data cell 508j connected to the bit line 508j. However, due to the presence of the connecting portion 580, a reference current having an average value thereof can be obtained.

  The reference current thus obtained behaves as a reference input current to the sense amplifiers 630a and 630b. The sense current is applied to the sense amplifiers 630a and 630b, respectively. The sense amplifiers 630a and 630b are differential amplifiers that compare the sense current with the reference current and determine the digital data state of the MRAM cell group at the outputs 635a and 635b.

  Upper read / write lines 615a and 615b are separated from the external circuit by read / write gate transistors 645a and 645b, and lower read / write lines 620a and 620b are separated from the external circuit by read / write gate transistors 635a and 635b. It is.

Next, a method for manufacturing the data cell subarray 600 will be described. In manufacturing the data cell sub-array 600, first, a plurality of data cells 500 are formed so as to be aligned in the row direction and the column direction, and then the plurality of data cells 50 extending in the column direction and aligned in the column direction are formed. Bit lines 507 and 508 are formed so as to be connected to the free layer 91 included in each. At this time, the bit lines 507 and the bit lines 508 are alternately arranged in the column direction.
Further, a connecting portion 580 that connects a pair of bit lines 507j and 508j of the plurality of bit lines 507 and 508 to each other is provided to form a bit line pair, and data in the first column lined up along the bit line 207 The cell 500 and the second reference cell 500 arranged along the bit line 208 are connected in parallel. Finally, the data cell sub-array 600 is obtained by setting (programming) the data cells 500 in the first and second columns located in the same row to different magnetization states.

  As described above, according to the MRAM array 2 of the present embodiment, the data cells 500 in the first column and the data cells 500 in the second column have different magnetization states, and one set of data cells Since the bit lines 507j and 508j are connected in parallel by the connecting portion 580 to form a reference column (bit line pair), a stable reference current based on the plurality of data cells 500 along the bit lines 507j and 508j can be obtained. Based on this, a highly accurate read operation can be performed.

  While the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and various modifications can be made. That is, as can be understood by those skilled in the art, the above embodiment is a specific example of the present invention, and the present invention is not limited to the above content. Modifications and changes in manufacturing method, structure, dimensions, etc., are made corresponding to the preferred embodiments as long as they are consistent with the invention.

  For example, in the first embodiment, programming of the reference cell sub-array 200 is performed using the combined magnetic field generated by the write word line current and the write bit line current. However, the present invention is not limited to this. Absent. Specifically, as shown in FIG. 12, a magnetic field 815 generated by a magnetic field generator 810 may be used. The magnetic field generator 810 is placed at a position where the distance from the reference cell subarray 200 is correctly adjusted so that the magnetization of the free layer has a desired orientation. The magnetic field 815 has directivity, and its strength is controlled by the magnetic field generator 810. The magnetic field generator 810 is only one example for providing an external magnetic field. The external magnetic field can be provided in various ways.

  Further, the following modification is possible for the programming method after step S766 of FIG. 8 in the first embodiment. Hereinafter, the modification is demonstrated with reference to FIG. 5 and FIG.

  First, after preparing the MRAM array 1 formed on the substrate (step S900), programming of an arbitrary reference cell 205 included in the reference cell subarray 200 is performed (step S905). After that, the sense amplifiers 400a and 400b are separated from the read / write lines 130 and 230 by inactivating the external connection gate transistors 409a to 409d (step S910). The externally connected gate transistors 409a to 409d become inactive when the internal bias voltage 412 turns off the gate transistors 405a, 405b, 407a, and 407b of the sense amplifiers 400a and 400b. Next, in order to measure the current flowing through the bit lines 207 and 208 in the reference cell subarray 200, an external current detection device (not shown) is connected to the read / write lines 130 and 230 (step S915). Further, the external switching bias voltage 410 is activated, and the external connection gate transistors 409a to 409d are driven. By making the block read / write reference selection lines 220 and 222 active, the block read / write selection transistors 211 and 212 are driven, and the bit lines 207 and 208 in the reference cell sub-array 200 are connected to the read / write line 230. (Step S920). Next, the read word line 265 corresponding to the predetermined reference cell 205 is selected and activated (step S925). As for external switching bias voltage 410, read / write lines 130 and 230 are set to a level (for example, 400 mV) sufficient to apply a bias voltage to the MTJ element. In this state, the cell current flowing through the selected reference cell 205 is measured by the external current detection device (step S930). Since the bit line pairs in the reference cell sub-array 200 are connected by the connecting portion 270, the reference current flowing through the read / write line 230 is basically the average of the sum of the currents flowing through both of the bit line pairs. Finally, the address of the read word line 265 is checked to determine whether the cell current measurement is completed for all the columns in the reference cell sub-array 200 (step S935). If the cell current measurement is not completed for all the columns, the address is increased so that the read word lines 265 are sequentially selected, and the cell current is measured for the remaining columns of the reference cells 205 (step S940). . When measurements have been made for all columns in step S935, those measurements are evaluated to determine whether the MRAM cells of the MRAM reference cell subarray 200 have been programmed. When the confirmation of the cell current is completed for all the columns, the programming is finished.

1 is a schematic diagram showing an overall configuration of an MRAM array 1 as a first embodiment of the present invention. FIG. 2 is a schematic diagram illustrating a planar configuration of the data cell subarray 100 illustrated in FIG. 1. FIG. 2 is a cross-sectional view illustrating a cross-sectional configuration of a data cell 105 illustrated in FIG. 1. FIG. 2 is a schematic diagram illustrating a planar configuration of a reference cell subarray 200 illustrated in FIG. 1. FIG. 2 is a circuit diagram showing a main part of the MRAM array 1 shown in FIG. 1. FIG. 6 is a circuit diagram showing another main part of the MRAM array 1 shown in FIG. 1. 3 is a flowchart for explaining a read operation from a desired data cell 105 in the MRAM array 1 shown in FIG. 5 is a flowchart illustrating a method for programming a reference cell 205. It is the schematic showing the whole structure of the MRAM array 2 as the 2nd Embodiment of this invention. FIG. 10 is a schematic diagram illustrating a planar configuration of the data cell sub-array 600 illustrated in FIG. 9. It is a circuit diagram which shows the principal part of the MRAM array 2 shown in FIG. FIG. 5 is a schematic diagram for explaining a magnetic field generator for writing to the reference cell subarray 200 shown in FIG. 4. 6 is a flowchart for explaining a modification of the programming method of the MRAM array 1 shown in FIG. 1. It is sectional drawing showing the cross-sectional structure of the conventional MRAM cell. FIG. 15 is a circuit diagram illustrating a circuit configuration corresponding to the MRAM cell illustrated in FIG. 14. FIG. 15 is a circuit diagram illustrating another circuit configuration corresponding to the MRAM cell illustrated in FIG. 14.

Explanation of symbols

Ic: Write bit line current, Ir: Write word line current, 1, 2 ... Magnetic memory cell array (MRAM array), 90 ... MTJ element, 91 ... Free layer, 92 ... Tunnel barrier layer, 93 ... Pinned layer, 96 ... Read cell current, 100 ... Data cell subarray, 105 ... MRAM data cell, 107,207,208,507,508 ... Bit line, 109,209,509 ... Write word line, 110, 211,212 ... Block read , Block write select transistor, 120 block read write select line, 125 block write select line, 130, 230 read write line, 135, 235 write line, 140, 240, 555 ... current source, 145, 245, 550 ... block selection transistor, 150, 250, 575 ... Lock selection line, 155, 255 ... row selection transistor, 160, 260 ... row selection write line, 165, 265, 570 ... read word line, 205 ... MRAM reference cells 220, 222 ... block read write reference selection line, 225 , 227... Block write reference selection line, 300, 605. Upper array block, 305, 606. Lower array block, 310, 610... Upper write line group, 315, 615. ... Lower read write line group, 325, 625 ... Lower write line group, 330, 630 ... Sense amplifier, 335, 635 ... Address bus, 340, 640 ... Clock line, 345, 645 ... Read / write control line, 500 ... MRAM data cells, 515 ... reference columns.

Claims (76)

An MRAM reference cell subarray that is used in an MRAM array having a plurality of MRAM data cell subarrays and sense amplifiers and supplies a reference current to the sense amplifiers,
A plurality of MRAM reference cells arranged in a row direction and a column direction;
The first and second bit lines that extend in the column direction and are connected to and adjacent to free layers included in the plurality of MRAM reference cells arranged in the column direction. A bit line pair;
A connecting portion connecting the first and second bit lines in the bit line pair to each other;
The MRAM reference cells in the first column aligned along the first bit line are connected in parallel with the second MRAM reference cells aligned along the second bit line,
The MRAM reference cell subarray, wherein the MRAM reference cells of the first and second columns located in the same row have different magnetization states. The MRAM reference cells in the first column are in a high resistance state when the MRAM reference cells in the second column are in a low resistance state, and are low in resistance when the MRAM reference cells in the second column are in a high resistance state. The MRAM reference cell subarray according to claim 1, wherein the MRAM reference cell subarray is in a state. The MRAM reference cell according to claim 1, further comprising a plurality of write word lines extending in the row direction and connected to the plurality of MRAM reference cells arranged in the row direction. Subarray. A current source connected to the plurality of write word lines and configured to supply a write word line current to the plurality of write word lines when writing to a predetermined MRAM reference cell; The MRAM reference cell subarray according to claim 3. The MRAM reference cell is
Directing the write word line current to the write word line;
Separating the MRAM reference cell from the sense amplifier;
A write current for the free layer is caused to flow through the first bit line in a first direction, then through the connecting portion, and a second bit line opposite to the first direction is passed through the second bit line. The MRAM reference cell subarray according to claim 4, wherein the MRAM reference cell subarray is programmed by a method including: flowing in a direction. The MRAM reference cell is
6. The programming word line is completed by stopping the write word line current and the write current, and reconnecting the plurality of sense amplifiers to the corresponding MRAM reference cells, respectively. The described MRAM reference cell subarray. The MRAM reference cell is
Separating the MRAM reference cell from the sense amplifier;
Forming a magnetic field indicating a direction in which the magnetization of the free layer in the MRAM reference cell is in a desired direction;
A write current for the free layer is caused to flow through the first bit line in a first direction, then through the connecting portion, and a second bit line opposite to the first direction is passed through the second bit line. Flowing in the direction,
The MRAM reference cell subarray of claim 1, programmed by a method comprising: removing the magnetic field. A plurality of write word lines extending in the row direction and connected to the plurality of MRAM reference cells arranged in the row direction;
8. The MRAM reference cell subarray according to claim 7, wherein the MRAM reference cell is programmed by a method further comprising a step of passing a write word line current to each of the plurality of write word lines. The MRAM reference cell is
9. The programming word line is completed by stopping the write word line current and the write current and reconnecting the plurality of sense amplifiers to the corresponding MRAM reference cells, respectively. The described MRAM reference cell subarray. 2. A plurality of read word lines extending in the row direction and connected to the plurality of MRAM reference cells arranged in the row direction via isolation transistors. MRAM reference cell subarray. The MRAM reference cell is
Separating the MRAM reference cell from the sense amplifier;
Applying a bias for each column to the plurality of MRAM reference cells;
Supplying an activation signal for each row to the plurality of MRAM reference cells;
Measuring the current passing through the first column of MRAM reference cells and the corresponding second column of MRAM reference cells for each row;
Determining whether the current is equivalent to a standard current;
The MRAM reference cell sub-array according to claim 1, wherein the MRAM reference cell sub-array is tested by a method including re-programming when the current is not equivalent to a standard current. A plurality of MRAM data cell subarrays;
A sense amplifier in communication with the plurality of MRAM data cell subarrays;
A plurality of MRAM reference cell subarrays for supplying a reference current to the sense amplifier;
The MRAM reference cell sub-array is
A plurality of MRAM reference cells arranged in a row direction and a column direction;
The first and second bit lines that extend in the column direction and are connected to and adjacent to free layers included in the plurality of MRAM reference cells arranged in the column direction. A bit line pair;
A connecting portion for connecting the first and second bit lines in the bit line pair to each other;
The MRAM reference cells in the first column aligned along the first bit line are connected in parallel with the second MRAM reference cells aligned along the second bit line,
The MRAM array, wherein the MRAM reference cells in the first and second columns located in the same row have different magnetization states. The MRAM reference cells in the first column are in a high resistance state when the MRAM reference cells in the second column are in a low resistance state, and are low in resistance when the MRAM reference cells in the second column are in a high resistance state. The MRAM array according to claim 12, wherein the MRAM array is in a state. The MRAM array according to claim 12, wherein the MRAM reference cell subarray is provided inside the plurality of MRAM data cell subarrays. The MRAM array according to claim 14, wherein a selected MRAM data cell subarray of the plurality of MRAM data cell subarrays is included in a group different from the MRAM reference cell subarray. The MRAM reference cell sub-array is
The MRAM array according to claim 12, further comprising a plurality of write word lines extending in the row direction and connected to the plurality of MRAM reference cells arranged in the row direction. A current source connected to the write word line and supplying a write word line current to the write word line when writing to a predetermined MRAM reference cell; The MRAM array according to claim 16. The MRAM reference cell is
Directing the write word line current to the write word line;
Separating the MRAM reference cell from the sense amplifier;
And a method of programming the free layer by flowing a write current to the first bit line in a first direction and then guiding the write current to the second bit line through the coupling portion. The MRAM array according to claim 17, wherein the MRAM array is provided. The MRAM reference cell is
19. The programming word line is completed by stopping the write word line current and the write current and reconnecting the plurality of sense amplifiers to the corresponding MRAM reference cells, respectively. The MRAM array as described. The MRAM reference cell is
Separating the plurality of MRAM reference cells from the sense amplifier;
Forming a magnetic field indicating a direction in which the magnetization of the free layer in the MRAM reference cell is in a desired direction;
Directing a write current to the free layer in the first direction through the first bit line and then leading to the second bit line via the coupling portion;
The MRAM array of claim 12, programmed by a method comprising: removing the magnetic field. A plurality of write word lines extending in the row direction and connected to the plurality of MRAM cells arranged in the row direction;
21. The MRAM array of claim 20, wherein the MRAM reference cell is programmed by a method further comprising passing a write word line current to each of the plurality of write word lines. The MRAM reference cell is
The programming word line is completed by stopping the write word line current and the write current, and reconnecting the plurality of sense amplifiers to the corresponding MRAM cells, respectively. MRAM array. 13. A plurality of read word lines extending in the row direction and connected to the plurality of MRAM reference cells arranged in the row direction via isolation transistors are provided. MRAM array. The MRAM reference cell is
Separating the plurality of MRAM reference cells from the sense amplifier;
Applying a bias for each column to the MRAM reference cell;
Supplying an activation signal for each row to the MRAM reference cell;
Measuring the current passing through the first column of MRAM reference cells and the corresponding second column of MRAM reference cells for each row;
Determining whether the current is equivalent to a standard current;
13. The MRAM array according to claim 12, wherein the MRAM array has been tested by a method including re-programming if the current is not equivalent to a standard current. An MRAM cell sub-array for use in an MRAM device with a plurality of sense amplifiers,
A plurality of MRAM cells arranged in a row direction and a column direction;
A plurality of bit lines extending in the column direction and connected to free layers included in the plurality of MRAM cells arranged in the column direction and arranged in the row direction;
A set of bit lines of the plurality of bit lines are connected to each other, and a connecting portion that forms a bit line pair is provided.
The MRAM cells in the first column aligned along one bit line of the bit line pair are connected in parallel to the second MRAM cells aligned along the other bit line of the bit line pair. ,
The MRAM cell sub-array, wherein the MRAM cells in the first and second columns located in the same row have different magnetization states. The MRAM cells in the first column are in a high resistance state when the MRAM cells in the second column are in a low resistance state, and are in a low resistance state when the MRAM cells in the second column are in a high resistance state. 26. The MRAM cell subarray of claim 25. The MRAM cell subarray according to claim 25, further comprising a plurality of write word lines extending in the row direction and connected to the plurality of MRAM cells arranged in the row direction. A current source connected to the plurality of write word lines and supplying a write word line current to the plurality of write word lines when writing to a predetermined MRAM cell; 28. The MRAM recell subarray of claim 27. The MRAM cell is
Directing the write word line current to the write word line;
Separating the MRAM cell from the sense amplifier;
A step of causing a write current for the free layer to flow in a first direction to one bit line of the bit line pair and then leading to the other bit line of the bit line pair through the connecting portion. 29. The MRAM cell subarray of claim 28, programmed by a method comprising: The MRAM cell is
30. The MRAM according to claim 29, wherein programming is completed by stopping the write word line current and the write current and reconnecting the sense amplifier to the corresponding MRAM cell. Cell subarray. The MRAM cell is
Separating the MRAM cell from the sense amplifier;
Forming a magnetic field indicating a direction in which the magnetization of the free layer in the MRAM cell is in a desired direction;
A write current for the free layer is supplied to one bit line of the bit line pair in a first direction, and then passed through the coupling unit to the other bit line of the bit line pair. Flowing in a second direction opposite to the first direction;
26. The MRAM cell subarray of claim 25, programmed by a method comprising: removing the magnetic field. A plurality of write word lines extending in the row direction and connected to the plurality of MRAM cells arranged in the row direction;
32. The MRAM cell subarray of claim 31, wherein the MRAM cell is programmed by a method further comprising flowing a write word line current to each of the write word lines. The MRAM cell is
33. The MRAM according to claim 32, wherein programming is completed by stopping the write word line current and the write current and reconnecting the sense amplifier to the corresponding MRAM cell. Cell subarray. 26. A plurality of read word lines extending in the row direction and connected to the plurality of MRAM cells arranged in the row direction via isolation transistors. MRAM cell subarray. The MRAM cell is
Separating the MRAM cell from the sense amplifier;
Applying a bias to the MRAM cell for each column;
Supplying an activation signal for each row to the MRAM cell;
Measuring the current through the first column of MRAM cells and the corresponding second column of MRAM cells for each row;
Determining whether the current is equivalent to a standard current;
26. The MRAM cell sub-array of claim 25, wherein the MRAM cell sub-array has been tested by a method that includes re-programming if the current is not equivalent to a standard current. A plurality of MRAM cell sub-arrays;
A sense amplifier that communicates with the plurality of MRAM cell sub-arrays;
The MRAM cell sub-array is connected to a plurality of MRAM cells arranged in a row direction and a column direction, and a free layer extending in the column direction and included in the plurality of MRAM cells arranged in the column direction, respectively. And a plurality of bit lines arranged in the row direction and a set of bit lines of the plurality of bit lines connected to each other to form a bit line pair,
The MRAM cells in the first column aligned along one bit line of the bit line pair are connected in parallel to the second MRAM cells aligned along the other bit line of the bit line pair. ,
The MRAM array characterized in that the MRAM cells of the first and second columns located in the same row have different magnetization states. The MRAM cells in the first column are in a high resistance state when the MRAM cells in the second column are in a low resistance state, and are in a low resistance state when the MRAM cells in the second column are in a high resistance state. 37. The MRAM array of claim 36. 37. The MRAM array according to claim 36, wherein an MRAM cell different from the first column MRAM cell and the second MRAM cell is a selected MRAM data cell. The MRAM array according to claim 36, further comprising a plurality of write word lines extending in the row direction and connected to the plurality of MRAM cells arranged in the row direction. A current source connected to the plurality of write word lines and supplying a write word line current to the plurality of write word lines when writing to a predetermined MRAM cell; 37. The MRAM array of claim 36. The MRAM cell is
Directing the write word line current to the write word line;
Separating the MRAM cell from the sense amplifier;
A step of causing a write current for the free layer to flow in a first direction to one bit line of the bit line pair and then leading to the other bit line of the bit line pair through the connecting portion. 37. The MRAM array of claim 36, programmed by a method comprising: The plurality of MRAM cells are:
37. The MRAM according to claim 36, wherein programming is completed by stopping the write word line current and the write current and reconnecting the sense amplifier to the corresponding MRAM cell. array. The MRAM cell is
Separating the MRAM cell from the sense amplifier;
Forming a magnetic field indicating a direction in which the magnetization of the free layer in the MRAM cell is in a desired direction;
A write current for the free layer is passed through the first bit line in a first direction, then passed through the connecting portion, and a second bit line opposite to the first direction is passed through the second bit line. Flowing in the direction of
37. The MRAM array of claim 36, programmed by a method comprising: removing the magnetic field. A plurality of write word lines extending in the row direction and connected to the plurality of MRAM cells arranged in the row direction;
44. The MRAM array of claim 43, wherein the plurality of MRAM cells are programmed by a method further comprising flowing a write word line current to each of the plurality of write word lines. The MRAM cell is
45. The programming is completed by stopping the write word line current and the write current, and reconnecting the plurality of sense amplifiers to the corresponding MRAM cells, respectively. MRAM array. 37. A plurality of read word lines extending in the row direction and connected to the plurality of MRAM cells arranged in the row direction via isolation transistors are provided. MRAM array. The MRAM cell is
Separating the plurality of MRAM cells from the sense amplifier;
Applying a bias to the MRAM cell for each column;
Supplying an activation signal for each row to the MRAM cell;
Measuring the current through the first column of MRAM cells and the corresponding second column of MRAM cells for each row;
Determining whether the current is equivalent to a standard current;
37. The MRAM array of claim 36, wherein the MRAM array has been tested by a method that includes re-programming if the current is not equivalent to a standard current. A method of manufacturing an MRAM reference cell subarray that is used in an MRAM device having a plurality of MRAM data cell subarrays and sense amplifiers and supplies a reference current to the sense amplifiers,
Forming a plurality of MRAM reference cells so as to be arranged in a row direction and a column direction;
The first and second bit lines are arranged so as to be connected to and adjacent to free layers included in the plurality of MRAM reference cells extending in the column direction and arranged in the column direction. Forming a line pair;
A connecting portion that connects the first and second bit lines in the bit line pair to each other is formed, and a first column of MRAM reference cells arranged along the first bit line, and the second bit line are connected to each other. Connecting in parallel a second MRAM reference cell lined up along;
And a step of setting the MRAM reference cells in the first and second columns located in the same row to different magnetization states. A method of manufacturing an MRAM reference cell subarray, comprising: Bringing the first column of MRAM reference cells into a high resistance state and the second column of MRAM reference cells into a low resistance state;
49. The method of manufacturing an MRAM reference cell subarray according to claim 48, wherein the MRAM reference cells in the first column are set in a low resistance state and the MRAM reference cells in the second column are set in a high resistance state. . 49. The manufacture of an MRAM reference cell subarray according to claim 48, wherein the plurality of write word lines extending in the row direction are formed to be connected to the plurality of MRAM reference cells arranged in the row direction. Method. Forming a current source for supplying a write word line current to the plurality of write word lines when writing to a predetermined MRAM reference cell is connected to the plurality of write word lines; 51. A method of manufacturing an MRAM reference cell sub-array according to claim 50. Separating the plurality of MRAM reference cells from the plurality of sense amplifiers;
Directing the write word line current to the write word line;
A method in which a write current for the free layer is passed through the first bit line in a first direction and then led to the second bit line via the connecting portion. 52. The method of manufacturing an MRAM reference cell subarray according to claim 51, wherein programming is performed. Programming to the MRAM reference cell is as follows:
53. The MRAM reference cell subarray according to claim 52, which is completed by stopping the write word line current and the write current and reconnecting the plurality of sense amplifiers to the corresponding MRAM reference cells. Manufacturing method. Separating the plurality of MRAM reference cells from the plurality of sense amplifiers;
Forming a magnetic field indicating a direction in which the magnetization of the free layer in the MRAM reference cell is in a desired direction;
Directing a write current to the free layer in the first direction through the first bit line and then leading to the second bit line via the coupling portion;
50. The method of manufacturing an MRAM reference cell subarray according to claim 49, wherein the MRAM reference cell is programmed by a method comprising: removing the magnetic field. Forming a plurality of write word lines extending in the row direction so as to be connected to the plurality of MRAM reference cells arranged in the row direction;
55. The fabrication of an MRAM reference cell sub-array according to claim 54, further comprising programming the plurality of MRAM reference cells by a method further comprising flowing a write word line current to each of the plurality of write word lines. Method. Programming to the MRAM reference cell is as follows:
56. The MRAM reference cell subarray according to claim 55, wherein the MRAM reference cell subarray is completed by stopping the write word line current and the write current and reconnecting the plurality of sense amplifiers to the corresponding MRAM reference cells. Manufacturing method. 49. A step of forming a plurality of read word lines extending in the row direction so as to be connected to the plurality of MRAM reference cells arranged in the row direction via isolation transistors. A manufacturing method of the described MRAM reference cell subarray. Separating the MRAM reference cell from the sense amplifier;
Applying a bias for each column to the MRAM reference cell;
Supplying an activation signal for each row to the MRAM reference cell;
Measuring the current passing through the first column of MRAM reference cells and the corresponding second column of MRAM reference cells for each row;
Determining whether the current is equivalent to a standard current;
49. The MRAM reference cell subarray according to claim 48, further comprising the step of inspecting the plurality of MRAM reference cells by a method including re-programming if the current is not equivalent to a standard current. Manufacturing method. A method of manufacturing an MRAM cell sub-array for use in an MRAM device with a plurality of sense amplifiers, comprising:
Forming a plurality of MRAM cells so as to be arranged in a row direction and a column direction;
Forming a plurality of bit lines extending in the column direction and arranged in the row direction so as to be respectively connected to free layers included in the plurality of MRAM cells arranged in the column direction;
A first column MRAM arranged along one bit line of the bit line pair by forming a bit line pair by providing a connecting portion that connects a pair of bit lines of the plurality of bit lines to each other Connecting the cell and a second MRAM cell aligned along the other bit line of the bit line pair in parallel;
A method of manufacturing an MRAM cell sub-array, comprising: setting one of the MRAM cells in the first and second columns located in the same row to a high resistance state and setting the other to a low resistance state. . 60. The MRAM according to claim 59, wherein the plurality of write word lines extending in the row direction are respectively connected to pinned layers included in the plurality of MRAM cells arranged in the row direction. Manufacturing method of cell subarray. Forming a current source for supplying a write word line current to the plurality of write word lines when writing to a predetermined MRAM reference cell is connected to the plurality of write word lines; 61. A method of manufacturing an MRAM cell sub-array according to claim 60. Separating the MRAM cell from the sense amplifier;
Directing the write word line current to the write word line;
A step of causing a write current for the free layer to flow in a first direction to one bit line of the bit line pair and then leading to the other bit line of the bit line pair through the connecting portion. 62. The method of manufacturing an MRAM cell sub-array according to claim 61, wherein the MRAM cell is programmed by a method including: Programming to the MRAM cell is as follows:
64. The fabrication of an MRAM cell subarray according to claim 62, wherein the fabrication is completed by stopping the write word line current and the write current and reconnecting the plurality of sense amplifiers to the corresponding MRAM cells respectively. Method. Separating the MRAM cell from the sense amplifier;
Forming a magnetic field indicating a direction in which the magnetization of the free layer in the MRAM cell is in a desired direction;
A write bit line current for the free layer is supplied to one bit line of the bit line pair in a first direction, and then to the other bit line of the bit line pair via the connecting portion. A guiding step,
61. The method of manufacturing an MRAM cell sub-array according to claim 60, wherein the MRAM cell is programmed by a method comprising: removing the magnetic field. Programming to the MRAM cell is as follows:
65. The manufacture of an MRAM cell subarray according to claim 64, wherein the MRAM cell sub-array is completed by stopping the write word line current and the write current and reconnecting the plurality of sense amplifiers to the corresponding MRAM cells. Method. 61. A step of forming a plurality of read word lines extending in the row direction so as to be connected to the plurality of MRAM cells arranged in the row direction via isolation transistors. Manufacturing method of the MRAM cell sub-array. Separating the MRAM cell from the sense amplifier;
Applying a bias to the MRAM cell for each column;
Supplying an activation signal for each row to the MRAM cell;
Measuring the current passing through the first column of MRAM cells and the corresponding second column of MRAM cells for each row;
Determining whether the current is equivalent to a standard current;
49. The fabrication of an MRAM cell sub-array according to claim 48, further comprising the step of inspecting the plurality of MRAM cells by a method comprising re-programming if the current is not equivalent to a standard current. Method. A holding body for holding a substrate on which a plurality of MRAM cell sub-arrays and sense amplifiers that are communicably connected to each other are formed;
A controller connected to the MRAM cell sub-array and controlling the MRAM cell sub-array to be separated from the sense amplifier;
A magnetic field generator for generating a magnetic field in a predetermined direction with respect to the MRAM cell sub-array;
A writing device for writing to the MRAM cell sub-array,
The MRAM cell sub-array is connected to a plurality of MRAM cells arranged in a row direction and a column direction, and a free layer extending in the column direction and included in the plurality of MRAM cells arranged in the column direction, respectively. And a plurality of bit lines arranged in the row direction and a set of bit lines of the plurality of bit lines connected to each other to form a bit line pair,
The MRAM cells in the first column aligned along one bit line of the bit line pair are connected in parallel to the second MRAM cells aligned along the other bit line of the bit line pair. ,
When writing to the MRAM cell sub-array, the writing device applies a write current to the free layer to one bit line of the bit line pair in a first direction, and then connects the connection. The MRAM cell sub-array writing device, wherein the MRAM cell sub-array writing device functions to guide the other bit line of the pair of bit lines to a second direction opposite to the first direction. The MRAM cell sub-array has a plurality of write word lines extending in the row direction and connected to the plurality of MRAM cells arranged in the row direction;
A current source connected to the plurality of write word lines and supplying a write word line current to the plurality of write word lines when writing to a predetermined MRAM cell; 69. The MRAM cell sub-array writer according to claim 68. The MRAM cell is
70. The write word line current and write current are stopped, and the plurality of sense amplifiers are reconnected to the corresponding MRAM cells to complete writing. The MRAM cell sub-array writing device as described. The MRAM cell is
Stopping the write current by the writing device;
Stopping the write word line current by the current source;
70. The MRAM cell sub-array writing device according to claim 69, wherein writing is completed by reconnecting the plurality of sense amplifiers to the corresponding MRAM cells. A plurality of MRAM cells arranged in a row direction and a column direction, and a free layer extending in the column direction and included in the plurality of MRAM cells arranged in the column direction are connected to the row direction. An MRAM cell having a plurality of bit lines arranged and a connecting portion that connects a pair of bit lines of the plurality of bit lines to form a bit line pair and is communicably connected to a plurality of sense amplifiers A sub-array writing method comprising:
Separating a selected MRAM cell to be written from among the plurality of MRAM cells from the sense amplifier;
Forming a magnetic field indicating a direction in which the magnetization of the free layer in the selected MRAM cell is in a desired direction;
Placing the magnetic field in the vicinity of the selected MRAM cell;
A write bit line current for the free layer is caused to flow through one bit line of the bit line pair in a first direction, and then is passed through the connecting portion to be the other bit line of the bit line pair. Flowing in a second direction opposite to the first direction. A method for writing an MRAM cell sub-array, comprising: 75. The MRAM cell subarray of claim 72, further comprising: supplying a write word line current to a write word line extending in the row direction and connected to the selected MRAM cell. Writing method. The method of claim 72, further comprising: stopping the write current and reconnecting the selected MRAM cell with the corresponding sense amplifier. 74. The MRAM cell subarray write of claim 73, further comprising: stopping the write word line current and write current and reconnecting the selected MRAM cell with the corresponding sense amplifier. Method. 74. The method of claim 73, further comprising: supplying a reference current that is an average value of a write bit line current flowing through each of the bit line pairs corresponding to the selected MRAM cell to the sense amplifier. A method for writing to an MRAM cell sub-array.

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