JP2007140824A - Device system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology allowing initialization of a loop bus even when a configuration change is taken place in a device system having a plurality of devices connected to the loop bus, and allowing suppression of increase of cost of the device system accompanying the initialization. <P>SOLUTION: In this device system, at least two devices each comprises a processor, a communication path is formed in a loop state by sequentially connecting a first node and at least one second node to circulate a packet comprising a plurality of packet elements to one direction, and each node sequentially inputs the packet in packet element units nearly in synchronization with the other node, and sequentially sends the packet in the packet element units. The second node adds either flag of a flag showing that it is a payload part and a flag showing that it is a header part to the packet element as a first flag according to sending order when sending the packet in the packet element units. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a device system including a plurality of devices connected to a loop communication path.

  Like a multiprocessor system, a device system including a plurality of devices such as a plurality of processors, a memory controller, a cache controller, and an I / O interface is formed by sequentially connecting nodes included in each device. Some have a loop communication path (hereinafter also referred to as “loop bus”) (for example, see Patent Documents 1 and 2 below).

JP 2001-125875 A Japanese Patent Laid-Open No. 58-4427

  In the device system having the loop bus as described above, it is necessary to initialize the loop bus at the time of startup. For example, consider a device system in which a packet consisting of a header part and a payload part circulates a predetermined number of loop buses after initialization.

  In such a device system, a device to transmit data finds an empty packet among circulating packets, and sends control information in the header part and data to be transmitted in the payload part for the empty packet. , Store and send each. On the other hand, when the ID of the receiving device is stored in the header of the circulating packet, the receiving device captures the data stored in the payload of the packet.

  In order for each device to perform such an operation, it is necessary to know the header position of the packet that each device circulates. If each device does not know the header position, it cannot determine whether or not the control information is stored in the header portion of the packet circulating around the loop bus, so whether or not the packet is an empty packet. This is because it cannot be determined. Further, since each device cannot determine whether or not the destination ID is its own ID for the circulating packet, it cannot determine whether or not the packet is a packet addressed to itself. It is.

  Therefore, as an initialization process of the loop bus, it is necessary to transmit a signal indicating the header position of each circulating packet to each device.

  Conventionally, such initialization processing is executed by any one node (master node) among nodes (functional units that control communication) included in each device. However, in this case, the master node may be lost due to a configuration change in the device system.

  Therefore, a configuration is also possible in which each device can execute initialization processing, and when there is no master node, another device executes initialization processing instead. However, in such a configuration, hardware for causing each device to execute an initialization process must be mounted in advance, which increases the manufacturing cost of the device system.

  The present invention has been made to solve at least a part of the above-described problems. In a device system including a plurality of devices connected to a loop bus, even when a configuration change occurs, the initialization of the loop bus is performed. It is an object of the present invention to provide a technique capable of executing the above-described functions and suppressing an increase in the cost of the device system associated with the initialization.

  In order to solve at least a part of the above-described problem, a first device system of the present invention is a device system including a plurality of devices connected by a loop communication path, and among the plurality of devices, At least two or more devices are configured by a processor, and the communication path is formed in a loop by sequentially connecting a first node provided in each device and at least one second node; It is possible to circulate a packet composed of a plurality of packet elements in one direction, and each node substantially synchronizes with other nodes, and the packet element is sent from the upstream node via the communication path. Sequentially input in units, and sequentially transmitted to the downstream node in units of packet elements via the communication path, and the second node A flag indicating that the packet element to be transmitted is a header part, or a flag indicating that the packet element to be transmitted is a payload part. The gist is to add one of the flags to the packet element to be transmitted as the first flag according to the order of transmission.

  As described above, in the first device system of the present invention, at least one second node is connected to the loop communication path, and the second node sends a packet to a downstream node as a packet element unit. Depending on the order of transmission, either the flag indicating that the packet element to be transmitted is the header part or the flag indicating that the packet element to be transmitted is the payload part. The flag is added to the packet element to be transmitted as the first flag.

  Therefore, the first node provided in each device confirms the first flag added to the packet element, so that the packet element input via the communication path is the header part or the payload part. Therefore, the communication path is initialized. In this way, since the second node different from the first node provided in the device initializes the communication path, even if a configuration change such as device replacement occurs, the initial communication path Will be performed.

  In addition, since the second node initializes the communication path, it is not necessary to provide a function unit for causing each device to execute the initialization process. Therefore, an increase in manufacturing cost of the device system can be suppressed as compared with a configuration in which a functional unit for executing initialization processing in all devices is provided.

  In the first device system, each packet element includes, in addition to the first flag, a flag indicating that the packet element is valid, or a flag indicating that the packet element is invalid. , Any one of the flags is added as a second flag, and when the second node inputs the packet in units of packet elements from the upstream node via the communication path, the packet Each of the second flags added to each of the packet elements constituting each of the packet elements, and whether or not the pattern indicated by the second flag is a predetermined reference pattern is determined. When the packet is determined not to be the predetermined reference pattern, the packet is configured when the packet is sent to the downstream node in units of the packet elements. It said second flag indicates a pattern wherein is added to the packet elements is such that the specific pattern of the predetermined reference pattern, may be changed to the second flag.

  When a second flag added to a plurality of packet elements constituting one packet is added to each packet element such that the pattern indicated by the second flag is a predetermined reference pattern, If an error occurs in the second flag due to a change in the output signal level of the node, the pattern indicated by the second flag is a pattern different from the predetermined reference pattern. At this time, there is a high possibility that an error has occurred in the packet as well.

  Even in such a case, by adopting the above configuration, the pattern indicated by the second flag for the packet that is input via the communication path in the downstream node of the second node is the predetermined pattern. By confirming that it is a specific pattern, it is possible to determine not to receive even a packet addressed to itself. As a result, a packet in which an error has occurred can be prevented from being captured by the first node.

  In the first device system, it is preferable that the specific pattern is a pattern indicating that the packet transmitted to the downstream node in units of packet elements is an empty packet.

  With such a configuration, as described later, the first node determines whether or not a packet input via the communication path is an empty packet according to the pattern indicated by the second flag. If there is, it is possible to cause the first node to determine a packet having a high possibility of an error as an empty packet.

  In the first device system, the first node configures whether or not a packet input in units of packet elements from an upstream node via the communication path is an empty packet. The determination is made based on the pattern indicated by the second flag added to each packet element, and when the first node determines that the packet is an empty packet, among the packet elements constituting the packet, A header including control information is stored in the packet element that is the header portion indicated by the first flag, and the first address that is the destination is stored in the packet element that is the payload portion indicated by the first flag. Data to be transmitted to one node is stored, and consists of a packet element storing the header and a packet element storing the data. Packets, via the communication path, may be may be sent in the packet element units of the downstream side node.

  By adopting such a configuration, when the first node having data to be transmitted determines that a packet that is likely to have an error is a free packet in the second node, the free node Data and a header to be transmitted are stored in the packet, and the packet is transmitted to the downstream node in units of packet elements. As a result, it is possible to prevent a packet that is highly likely to have an error from continuing to circulate through the communication path without being captured by any of the first nodes.

  In the first device system, the packet may be composed of two packet elements.

  In this way, in each node, in order to determine whether the pattern indicated by the second flag is a predetermined reference pattern, the second flag that is sequentially input via the communication path is buffered. Therefore, a relatively small area is required. For example, if a packet is composed of three packet elements, an area for buffering up to three second flags is necessary to determine the pattern indicated by the three second flags. On the other hand, with the above configuration, only a region for buffering up to two second flags is required.

  The first device system may be integrated on one semiconductor substrate.

  By doing so, the physical size of the entire device system can be made relatively compact.

  The second device system of the present invention is a device system comprising a plurality of devices connected by a loop communication path, and at least two of the plurality of devices are constituted by a processor, The communication path is formed in a loop shape by sequentially connecting a first node provided in each device and at least one second node, and circulates a packet composed of a plurality of packet elements in one direction. Each node can sequentially input the packet from the upstream node via the communication path in units of the packet elements, and substantially communicate with the downstream node. The packet elements are sequentially transmitted via a route, and a flag is added to each packet element, and the second node is connected to the upstream side. When the packet is input in units of packet elements from the network via the communication path, each of the flags added to each packet element constituting the packet is detected, and the pattern indicated by the flags is: It is determined whether or not the predetermined reference pattern, and when the second node determines that it is not the predetermined reference pattern, when sending the packet to the downstream node in units of the packet elements, The gist is to change the flag so that a pattern indicated by the flag added to the packet element constituting the packet becomes a specific pattern of the predetermined reference pattern.

  Thus, in the second device system of the present invention, at least one second node is connected to the loop communication path, and this second node inputs from the upstream side via the communication path. When it is determined whether or not the pattern indicated by the flag for the packet is a predetermined reference pattern, and the packet is determined not to be the predetermined reference pattern, when the packet is sent to the downstream node in units of packet elements, the packet The flag is changed so that the pattern indicated by the flag added to the packet element that constitutes is a specific pattern of a predetermined reference pattern.

  Therefore, in the first node, the pattern indicated by the flag for the packet input in packet element units via the communication path is a predetermined reference pattern. Therefore, if the predetermined reference pattern is a pattern in which the header part and the payload part of the packet element can be identified, the packet element input via the communication path is the header part in each node. Or the payload portion, the communication path is initialized. In this way, since the second node different from the first node provided in the device initializes the communication path, even if a configuration change such as device replacement occurs, the initial communication path Will be performed.

  In addition, since the second node initializes the communication path, it is not necessary to provide a function unit for causing each device to execute the initialization process. Therefore, an increase in manufacturing cost of the device system can be suppressed as compared with a configuration in which a functional unit for executing initialization processing in all devices is provided.

  Further, when an error occurs in a flag due to a change in the output signal level of a certain node, the pattern indicated by this flag becomes a pattern different from a predetermined reference pattern. At this time, there is a high possibility that an error has occurred in the packet as well.

  Even in such a case, by adopting the above configuration, if the specific pattern is, for example, a pattern indicating an empty packet, the first node checks the pattern indicated by this flag, thereby setting the communication path. It is possible to determine that a packet input via the packet is a vacant packet, and it is possible to determine not to receive even a packet addressed to itself. As a result, a packet in which an error has occurred can be prevented from being captured by the first node. Further, since the first node having data to be transmitted can transmit data to be transmitted using this packet, a packet that is highly likely to have an error is transmitted to any of the first nodes. It is possible to prevent the communication path from being continuously circulated without being taken in.

Hereinafter, the best mode for carrying out the present invention will be described in the following order based on examples.
A. Example:
A1. Device system overview:
A2. Node configuration and operation:
A3. Cleaner node configuration and initialization:
A4. Control bit correction processing:
A5. Effects of the embodiment:
B. Variation:

A. Example:
A1. Device system overview:
FIG. 1 is an explanatory diagram showing a schematic configuration of a device system as an embodiment of the present invention.

  A device system 10 shown in FIG. 1 includes four devices 20A to 20D, and is a microprocessor in which these devices 20A to 20D are integrated on one semiconductor substrate.

  The device system 10 includes a device 20A and a device 20B as processors, a device 20C as an I / O interface, and a device 20D as a memory controller.

  In addition, the processor which is the device 20A and the device 20B means a unit including peripheral circuits such as a cache memory, a ROM, a RAM, and a node (functional unit for controlling communication) in addition to the CPU. Similarly, the I / O interface, which is the device 20C, and the memory controller, which is the device 20D, mean units including peripheral circuits such as nodes in addition to the functional units that perform main control.

  The four devices 20A to 20D are connected to each other via a communication path NIO formed in a loop shape by sequentially connecting the nodes 22A to 22D included therein.

  Specifically, as shown in FIG. 1, the node 22A of the device 20A and the node 22B of the device 20B are connected via a first partial path NIO1 constituting the communication path NIO, and the node of the device 20B 22B and the node 22C of the device 20C are connected via the second partial path NIO2 constituting the communication path NIO, and the node 22C of the device 20C and the node 22D of the device 20D constitute the communication path NIO. The node 22D of the device 20D and the node 22A of the device 20A are connected via a fourth partial path NIO4 constituting the communication path NIO.

  Here, a cleaner node 30 which is a characteristic part of the present invention is provided between the device 20A and the device 20B, and the partial path NIO1 includes an NIO 1a connecting the node 22A and the cleaner node 30, and a cleaner node. 30 and the node 22B are divided into NIO1b.

  The cleaner node 30 is a functional unit that controls communication in the same manner as the nodes 22A to 22D included in the devices 20A to 20D. However, unlike the nodes 22A to 22D, the cleaner node 30 performs initialization processing for the communication path NIO in addition to communication control. The detailed configuration of the cleaner node 30 and the nodes 22A to 22D will be described later.

  The nodes 22A to 22D described above correspond to the first node in the claims, and the cleaner node 30 corresponds to the second node in the claims.

  In the device system 10 described above, the devices 20A to 20D communicate with each other by transmitting and receiving data indicating predetermined communication contents via the nodes 22A to 22D connected to the communication path NIO.

  Examples of the predetermined communication contents include a write request message for writing data to a destination device, a read request message for reading data from the destination device, a response message for these request messages, and the like. Data transmitted / received between the devices is configured as a so-called packet.

  FIG. 2 is an explanatory diagram showing a data structure of a packet transmitted / received between devices.

  As shown in FIG. 2, a packet transmitted through the communication path NIO has a fixed length of 64 bits and is roughly composed of a header part of the first half 32 bits and a payload part of the second half 32 bits.

  The header part further comprises a control information part of the first 16 bits and an address part of the second 16 bits. The control information part, in order from the top, includes a field (TYPE) indicating the type of communication content (read request message, write request message, etc.), a field (Dsize) indicating the data size, a field (DID) indicating the destination ID, and transmission. It consists of a field (SID) indicating the original ID. The address portion includes a field indicating the address of a communication memory secured in a memory (not shown) for writing data to be written to the transmission destination device and data to be read from the transmission destination device.

  On the other hand, the payload part is a field for storing communication data to be transmitted and received in all 32 bits. The header part and the payload part correspond to the packet element in the claims.

  Each of the nodes 22A to 22D transfers the packet having such a structure in parallel every 32 bits.

  FIG. 3 is an explanatory diagram showing a detailed configuration of the communication path NIO shown in FIG.

  In FIG. 3, a part of the partial path NIO1 is shown in an enlarged manner in the communication path NIO shown in FIG. As shown in FIG. 3, the communication path NIO is composed of 34 communication wires from the first to the 34th. The first communication line and the second communication line are dedicated lines for transmitting control bits (H bit and V bit), which will be described later, and the third communication line to the 34th line. A total of 32 lines of communication lines are dedicated lines for transmitting the aforementioned packets.

  In FIG. 3, the node 22A can transfer control bits (2 bits) and bits (packet bits) (32 bits) constituting a packet in one cycle of the system clock. Therefore, when viewed from the cleaner node 30 which is a downstream node, a header part (32 bits) and a payload part (32 bits) are added with a control bit (2 bits) every cycle, and alternately. It is transmitted from the node 22A which is the upstream node.

  Similar to the node 22A described above, the other nodes 22B to 22D and the cleaner node 30 also transfer packets in parallel every 32 bits.

  Here, the aforementioned H bit is a control bit indicating whether a packet bit transmitted through the third to 34th communication wirings in the same cycle is a header portion or a payload portion. Specifically, when the H bit is “1”, it indicates that the packet bit of the same cycle is the header part, and when the H bit is “0”, the packet bit of the same cycle is the payload part. Indicates.

  Therefore, in the cleaner node 30 shown in FIG. 3, “1” and “0” are alternately transmitted from the node 22A as the H bit for each cycle. Not only the cleaner node 30 but also the other nodes 22A to 22D, “1” and “0” are input as the H bits for each cycle via the communication path NIO.

  On the other hand, the aforementioned V bit is a control bit indicating whether or not the packet bits transmitted through the third to 34th communication wires in the same cycle are valid or invalid. Specifically, when the V bit is “1”, it indicates that the packet bit of the same cycle is valid, and when the V bit is “0”, it indicates that the packet bit of the same cycle is invalid. .

  Here, in the nodes 22A to 22D, when two packet bits (header part and payload part) constituting one packet are both invalid, there is data to be transmitted by regarding the packet as an empty packet. In that case, the data is stored and transmitted.

  Therefore, each of the nodes 22A to 22D and the cleaner node 30 uses the V bit to determine whether a packet input via the communication path NIO is an empty packet or a normal packet that is not an empty packet (any node 20A ˜20D to identify whether the data to be transmitted is stored.

  Specifically, each of the nodes 22A to 22D and the cleaner node 30 has two V bits transmitted in the same cycle (two consecutive cycles) as two packet bits (header portion and payload portion) constituting one packet. If the combination is “0, 0”, it is identified as an empty packet, and if it is “1, 1”, it is identified as a normal packet.

  The aforementioned H bit corresponds to the first flag in the claims, and the aforementioned V bit corresponds to the second flag in the claims.

A2. Node configuration and operation:
FIG. 4 is an explanatory diagram illustrating a configuration of a node included in the device. In FIG. 4, the node 22A is shown as a representative, but the other nodes 22B to 22D have the same configuration.

  A node 22A illustrated in FIG. 4 includes a first register 221, a second register 222, and a transmission / reception control unit 223. Note that the reception buffer 24 and the transmission buffer 26 shown in FIG. 4 are part of a communication memory (not shown) provided in the processor 20A.

  The first register 221 is a register having a storage area with the number of bits equal to the 34-bit wiring width of the partial path NIO4 connected to the input side of the node 22A. Similarly, the second register 222 is a register having a storage area with the number of bits equal to the 34-bit wiring width of the NIO 1a connected to the output side of the node 22A.

  The writing operation of the first register 221 is controlled by a control signal CTL1 output from the transmission / reception control unit 223, and the writing operation of the second register 222 is controlled by a control signal CTL2 output from the transmission / reception control unit 223. .

  The transmission / reception control unit 223 outputs a control signal CTL1 for each cycle in synchronization with the system clock SCK, and controls a write operation to the first register 221 of data input from the input-side partial path NIO4. At the same time, the control signal CTL2 is output to control the writing operation of the data output from the first register 221 to the second register 222.

  The node 22A transmits and receives one packet for every two cycles of the system clock, as will be described below.

  FIG. 5 is an explanatory diagram for explaining the packet transmission / reception operation in the node 22A.

  In FIG. 5, the upper stage shows the H bit inputted through the partial path NIO4 at the node 22A, the middle stage shows the V bit inputted through the partial path NIO4 at the node 22A, and the lower stage passes through the partial path NIO4 at the node 22A. Each packet bit input is shown.

  As will be described later, since the node 22A transmits and receives one packet every two cycles, the two cycles are divided into a first cycle and a second cycle for convenience of explanation. That is, the first cycle, the second cycle, the first cycle, the second cycle,... Are alternately repeated.

  In FIG. 5, bits (H bit, V bit, packet bit) stored in the first register 221 and bits (H bit, V bit, packet bit) stored in the second register 222 in each cycle. The combinations are shown in a rectangle. In this combination, the right side shows the bits stored in the first register 221 and the left side shows the bits stored in the second register 222.

  In FIG. 5, the above-described combination in the first cycle is indicated by 1-n, and the above-described combination in the second cycle is indicated by 2-n. “N” represents a natural number of 1, 2, 3,..., 1-n represents the nth first cycle, and 2-n represents the nth second cycle. Show. Therefore, two cycles are repeated in the order of cycle 1-1, cycle 2-1, cycle 1-2, cycle 2-2,.

  Specifically, for example, in cycle 1-1, the first register 221 stores “0” as the H bit, “1” as the V bit, and “payload part” as the packet bit. In addition, the second register 222 stores “1” as the H bit, “1” as the V bit, and “header part” as the packet bit.

  Now, in cycle 2-1, as shown in FIG. 5, the H bit “1”, the V bit “1”, and the packet bit “header part” are written in the first register 221, and the second register 222 is written. , H bit “0”, V bit “1”, and packet bit “payload part” are written.

  The transmission / reception control unit 223 shown in FIG. 4 has already been written in the first register 221 before the next cycle 1-2 shown in FIG. 5 is started. Based on the H bit “1” to be written and the H bit “0” that has been transmitted through the partial path NIO4 and is to be written to the first register 221 in cycle 1-2, the next cycle 1- 2, it is determined that the packet bits (total of 64 bits) to be written to the second register 222 and the first register 221 are one packet.

  If the combination of H bits is “1, 0” (second register 222, first register 221), the combination of packet bits is “header part, payload part” (second register 222, first register 221). Register 221). Here, as shown in FIG. 2, since the packet is transmitted in the order of the header part and the payload part, when the H bit is the above combination (1, 0), the packet bit combination is one packet. Will be shown.

  In conjunction with the determination of whether or not the packet is a single packet, the transmission / reception control unit 223 has already been written in the first register 221 and is scheduled to be written in the second register 222 in cycle 1-2. Based on the bit and the V bit transmitted through the partial path NIO4 and to be written to the first register 221 in the cycle 1-2, it is determined whether or not this one packet is a normal packet.

  As shown in FIG. 5, since the combination of V bits in the cycle 1-2 is scheduled to be “1, 1” (second register 222, first register 221), in this case, the transmission / reception control unit 223 Therefore, it is determined that the packet is a normal packet.

  When the transmission / reception control unit 223 determines that the packet is a normal packet, based on the DID described in the packet bit “header part” to be written to the second register 222 in the next cycle 1-2, It is determined whether this packet is a packet addressed to itself.

  At this time, if the transmission / reception control unit 223 determines that the packet is addressed to itself, the transmission / reception control unit 223 captures the input packet bit and the output packet bit of the first register 221 at the write timing of the cycle 1-2 and stores them in the reception buffer 24. Furthermore, all “0” s are written as packet bits to the first register 221 and the second register 222, and both “0” are written as V bits to the first register 221 and the second register 222. To start transmission of an empty packet from the partial path NIO1a on the output side. In this way, the node 22A receives a packet addressed to itself.

  On the other hand, if the transmission / reception control unit 223 determines that the packet is not addressed to itself, the transmission / reception control unit 223 does not store the packet bit in the reception buffer 24 and writes the packet bit to the first register 221 at the write timing of the cycle 1-2. Each bit (H bit, V bit, packet bit) is written to the second register 222, and each bit (H bit, V bit, packet bit) inputted from the partial path NIO4 on the input side is written to the first register 221 is written, and transmission of a packet not addressed to itself is started from the partial path NIO1a on the output side.

  In the above description, the packet input from the partial path NIO4 is a normal packet. However, if the input packet is an empty packet and a transmission waiting packet is stored in the transmission buffer 26, transmission / reception is performed. In the cycle 1-2 described above, the control unit 223 stores the packet bit (header portion and payload portion), H bit (1, 0), V bit (1, 1) in the second register 222 and the first register 221. ) Can be transmitted from the communication path NIOa on the output side.

  In this way, the node 22A of the device 20A can receive and transmit one packet every two cycles of the system clock. Similarly, the nodes 22B to 22D of the other devices 20B to 20D can receive and transmit one packet every two cycles of the system clock.

  As described above, each of the nodes 22A to 22D determines whether or not the combination of packet bits to be stored in the two registers in the next cycle is one packet based on the H bit. The header portion is identified, and it is determined whether or not the packet is addressed to itself based on the DID described in the header portion.

  However, at the time of activation of the device system 10, the H bit is not transmitted in the communication path NIO so as to alternate with 1, 0, 1, 0... In this state, “0” is transmitted in all cycles. Accordingly, in this state, each of the nodes 22A to 22D does not know the cycle in which the header part is transmitted as a packet bit, and cannot perform packet transmission / reception.

  Therefore, as an initialization process for the communication path NIO, the cleaner node 30 sends an alternate value of 1, 0, 1, 0,... For each cycle as the H bit to the communication path NIO. .

A3. Cleaner node configuration and initialization:
FIG. 6 is an explanatory diagram showing the configuration of the cleaner node 30.

  The cleaner node 30 illustrated in FIG. 6 includes a first register 301, a second register 302, and a transmission / reception control unit 303, similarly to the nodes 22A to 22D. Note that the first register 301 and the second register 302 are the same as the first register 221 and the second register 222 shown in FIG.

  The writing operation of the first register 301 is controlled by the first control signal CTL10 output from the transmission / reception control unit 303, and the second register 302 is controlled by the second control signal CTL20 output from the transmission / reception control unit 303. The write operation is controlled. Note that the transmission / reception control unit 303 receives the system clock SCK as in the transmission / reception control unit 223 described above.

  When the device system 10 is activated, in the cleaner node 30 illustrated in FIG. 6, the transmission / reception control unit 303 stores the communication path NIO in the second register 302 at the write timing of the first cycle as an initialization process. H bit “1”, V bit “0”, and packet bit “all 0” are written, and H bit “0”, V bit “1”, and packet bit “all 0” are written to the first register 301.

  The transmission / reception control unit 303 also writes the H bit “0” and the V bit “0” written in the first register 301 in the previous cycle (first cycle) at the write timing of the second cycle. 0 ”and packet bit“ all 0 ”are written in the second register 302, and H bit“ 1 ”, V bit“ 1 ”, and packet bit“ all 0 ”are written in the first register 301. Then, the transmission / reception control unit 303 repeatedly executes the operations of the first cycle and the second cycle described above.

  In this way, the H-bit is repeatedly sent to the partial path NIO1b on the output side of the cleaner node 30 alternately as 1, 0, 1, 0,... The nodes 22A to 22D can know the cycle in which the header part is transmitted as packet bits. At this time, since the empty packet is transmitted from the cleaner node 30, each of the nodes 22A to 22D can transmit data to other nodes using the empty packet.

  Then, after starting the above initialization process, the cleaner node 30 is either an empty packet returned after one week of the communication path NIO or a normal packet in which any node stores data in the payload portion. Is input, the transmission of the empty packet to the communication path NIO is stopped, and the control bit correction process described later is performed.

A4. Control bit correction processing:
After the initialization of the communication path NIO, there is a possibility that an H-bit or V-bit error may occur due to a sudden change in the output signal level at the node. Then, when an error occurs in the H bit, each node erroneously breaks the packet so that, for example, the received packet bit is a bit indicating the payload portion, but the header portion is determined. May occur.

  In such a case, the destination node erroneously determines the DID, and determines that the packet is addressed to another node even though it is addressed to itself. As a result, as described above, the destination node outputs the packet addressed to itself to the partial path on the output side as it is, so that this packet continues to circulate in the communication path NIO.

  When an error occurs in the V bit, for example, the combination of the V bits corresponding to the combination of the packet bits constituting the packet is not the original combination “1, 1” although the packet is a normal packet. , “1, 0” or “0, 1” may occur.

  In such a case, the destination node determines that the packet is not a normal packet. In this case, the destination node performs the same process on the packet as when the packet not addressed to itself is received. That is, although the packet is originally addressed to itself, the packet is output as it is to the partial path on the output side without being taken into the reception buffer 24. As a result, the normal packet continues to circulate in the communication path NIO.

  Similarly, there is a case where the combination of V bits becomes “1, 0” or “0, 1” instead of the original combination “0, 0” in spite of being an empty packet. This empty packet continues to circulate in the communication path NIO.

  Therefore, the cleaner node 30 monitors the H bit and V bit as control bit correction processing in order to suppress such inconvenience, and corrects the bit when an invalid H bit or V bit is found. I have to.

  On the other hand, the cleaner node 30 does not monitor the packet bit, and the packet input from the input side partial path NIO1a is output to the output side partial path NIO1b as it is, regardless of whether it is a normal packet or an empty packet. I have to.

  FIG. 7 is an explanatory diagram for explaining the control bit correction processing in the cleaner node 30.

  7A shows an H bit input to the cleaner node 30 via the partial path NIO1a, and FIG. 7B shows a V bit input to the cleaner node 30 via the partial path NIO1a. In FIG. 7, the rectangle (1-n / 2-n) surrounding each bit is the same as the rectangle (1-n / 2-n) shown in FIG.

  Now, in cycle 2-11, as shown in FIG. 7, the H bit “1” and the V bit “1” are written in the first register 301 of the cleaner node 30, and the second register 302 has It is assumed that H bit “0” and V bit “1” are written.

  The transmission / reception control unit 303 shown in FIG. 6 has already been written in the first register 301 before the next cycle 1-12 shown in FIG. 7 is started, and in the second register 302 in cycle 1-12. Normality of the H bit based on the H bit “1” to be written and the H bit “1” that is transmitted through the partial path NIO1a and is to be written to the first register 301 in cycles 1-12. Judging.

  In this case, since the transmission / reception control unit 303 is followed by “1” instead of “0”, the H bit scheduled to be written to the first register 301 in cycle 1-12 is an invalid H bit. Judge that there is. In this case, as shown by the bold rectangle in FIG. 7A, the transmission / reception control unit 303 stores the second register 302 in the second register 302 in cycle 2-11 at the write timing of the next cycle 1-12. “1” written in the register 301 of 1 is written as H bit, while “0” is written as H bit in the first register 301 instead of “1” transmitted to the partial path NIO1a. Try to write.

  By doing so, an illegal H bit is corrected, and erroneous determination of packet breaks can be suppressed.

  Further, the transmission / reception control unit 303 corrects the V bit together with the correction of the H bit described above.

  Specifically, as shown by the bold rectangle in FIG. 7B, the second register 302 is written in the first register 301 in cycle 2-11 at the write timing of the next cycle 1-12. Instead of “1”, “0” is written as the V bit, and similarly, “0” is written to the first register 301 in place of “1” transmitted to the partial path NIO1a. Write as a bit.

  In this way, the cleaner node 30 outputs the normal packet in which the H-bit error has occurred to the partial path NIO1b as an empty packet. In this way, the V bit is corrected together with the correction of the H bit and the normal packet is changed to an empty packet. If an error occurs in the H bit, the packet bit may have an error as well. This is to prevent packets containing such errors from being stored in the reception buffer at the destination node. Also, by making the packet free, this packet can be used for other nodes to transmit data.

  The H bit error described above was originally the case where the H bit in the same cycle became “1” instead of “0” even though the packet bit was the payload part. In addition, even when the packet bit is originally a header part, even when the H bit of the same cycle becomes “0” or when an error of the V bit occurs, the cleaner node 30 And V-bit correction is performed.

  FIG. 8 is an explanatory diagram showing an example of H-bit or V-bit correction in the control bit correction process.

  In FIG. 8, for the two cases (cases A and B) in which an H-bit error has occurred and the two cases (cases C and D) in which a V-bit error has occurred, the combination of H bits before and after correction and A combination of V bits is shown.

  In each case A to D shown in FIG. 8, the combination of H bits before correction is such that the left side is the H bit that is to be written to the second register 302, and the right side is the H bit that is to be written to the first register 301. Are shown respectively.

  On the other hand, in each of the cases A to D shown in FIG. 8, the corrected H bit combination is that the left side is actually written to the second register 302 and the right side is actually written to the first register 301. The H bits to be written are shown respectively.

  Since the combination of V bits is the same as the combination of H bits, the description is omitted. In FIG. 8, “x” indicates a value of “1” or “0”.

  Although not shown in the figure, for the packet bits, the header portion is to be written in the second register 302 and the payload portion is to be written in the first register 301 before the correction, and after the correction, It shall be actually written in

  In the case A shown in FIG. 8, although the payload portion is scheduled to be written to the first register 301 as a packet bit, the H bit scheduled to be written in the same cycle is “1”. This is a case where an error has occurred. This case is the same as the case of FIG. 7 described above, and the combination of H bits after correction is (1, 0), and the combination of V bits is (0, 0).

  In case B, there is an error in the H bit that the H bit scheduled to be written in the same cycle is “0” even though the header portion is scheduled to be written in the second register 302 as a packet bit. This is the case.

  In cases C and D, no error has occurred in the H bit, but an error has occurred in the V bit, and the combination of V bits means an empty packet (0, 0), or normal This is a case that is not any combination of (1, 1) meaning a packet.

  Also in these cases B to D, the transmission / reception control unit 303 in the cleaner node 30 corrects the H bit or the V bit and sets the combination of the H bits to (1, 0) and the combination of the V bits as in the case A. Is (0, 0).

  As described above, when the transmission / reception control unit 303 finds an error of the H bit or the V bit, the transmission / reception control unit 303 corrects the H bit or the V bit and sets the combination of the V bits for the packet corresponding to the bit in which the error has occurred. By setting (0, 0), such a packet is output as an empty packet from the partial path NIO1b.

A5. Effects of the embodiment:
As described above, in the device system 10, the cleaner node 30 is installed on the communication path NIO in addition to the nodes 22A to 22D of the devices 20A to 20D. Only the cleaner node 30 performs the initialization process of the communication path NIO. Accordingly, since the node provided in any device becomes the master node and the communication path NIO is not configured to be initialized, the communication path NIO should be initialized even if a system configuration change such as device replacement occurs. Is possible.

  Further, since only the cleaner node 30 initializes the communication path NIO, it is not necessary to provide a circuit for performing the initialization process in all the devices 20A to 20D. Therefore, an increase in manufacturing cost of the device system 10 can be suppressed as compared with a configuration in which a circuit that performs initialization processing is provided in all the devices 20A to 20D.

  In addition, after initialization, the cleaner node 30 monitors the H bit and the V bit, and if an error is found in any of the bits, the cleaner node 30 corrects the H bit and the V bit and corresponds to the bit. The packet is output to the partial path NIO1b as an empty packet. Therefore, when an error occurs in a packet bit at the same timing as an H bit or V bit error, it is possible to prevent a packet containing such an error from being stored in the reception buffer at the destination node. Also, in the case where an error occurs in the header part DID in the packet bit at the same timing as the error of the H bit or the V bit, and the DID is changed to a non-existing DID, the cleaner node 30 causes such a packet. Since the packet is output as an empty packet, it is possible to prevent a packet that is not taken in by any node from continuing to circulate through the communication path NIO.

B. Variation:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible. .

B1. Modification 1:
In the embodiment described above, the cleaner node 30 is provided only on the partial path NIO1, but may be configured not only on the partial path NIO1 but also on the other partial paths NIO2 to NIO4. With this configuration, the number of nodes that send empty packets to the communication path NIO increases in the initialization process, so that the initialization process can be completed earlier.

B2. Modification 2:
In the above-described embodiment, when the H bit is “1”, it indicates that the packet bit transmitted in the same cycle is the header part, and when it is “0”, the packet bit transmitted in the same cycle is Although the payload portion is indicated, the present invention is not limited to this. On the contrary, when the H bit is “1”, it indicates that the packet bit transmitted in the same cycle is the payload part, and when it is “0”, the packet bit transmitted in the same cycle is It does not matter if it is a header part.

  As for the V bit, in the above-described embodiment, if the combination of two V bits transmitted in the same cycle as the two packet bits constituting one packet is “0, 0”, an empty packet is indicated. "1, 1" indicates a normal packet, but the present invention is not limited to this. On the contrary, if the combination of V bits is “0, 0”, a normal packet may be indicated, and if “1, 1”, an empty packet may be indicated.

B3. Modification 3:
In the embodiment described above, when the cleaner node 30 finds an invalid H bit or V bit, the packet corresponding to the found bit is set to (0, 0) to set the packet to (0, 0). Is output as an empty packet, but the combination of V bit bits may be (0, 0) and all the packet bits corresponding to the packet may be set to 0 before output.

  Each of the devices 20A to 20D determines whether or not the packet is an empty packet only by a combination of V bits. Therefore, regardless of whether or not all the packet bits are 0, if the combination of the V bits in the packet is (0, 0), it is determined as an empty packet, and if the transmission waiting packet is in the transmission buffer, This is because control information and communication data are stored (overwritten) in the header part and the payload part, respectively.

B4. Modification 4:
In the embodiment described above, the packet (64 bits) is transferred in parallel as packet bits for each header part (32 bits) and payload part (32 bits), but the present invention is not limited to this. is not. For example, assuming that parallel transfer is performed every 16 bits, the transfer may be performed in the order of header portion (first half), header portion (second half), payload portion (first half), payload portion (second half),.

  In this case, the cleaner node may send the H bits to the communication path NIO in the order of 1, 1, 0, 0,. In addition, each node and cleaner node may identify a free packet (0, 0, 0, 0) or a normal packet (1, 1, 1, 1) by a combination of four V bits.

B5. Modification 5:
In the embodiment described above, the cleaner node 30 monitors the H bit and the V bit separately in the control bit correction process, but instead of this, one pattern consisting of the H bit and the V bit is used. However, it may be monitored by determining whether or not a predetermined reference pattern.

  Specifically, for example, in the cleaner node 30, a reference pattern of H bits (2 bits) and V bits (2 bits) of the same cycle as two packet bits constituting one packet is previously stored in the transmission / reception control unit 303. Set it.

  This reference pattern is a pattern (1,0, 1, 1) indicating a normal packet or a pattern (1,0, 0, 0) indicating an empty packet. Each pattern indicates (first half of H bit, second half of H bit, first half of V bit, second half of V bit).

  Then, it is determined whether or not the combination of the H bit and the V bit for one input packet matches the above-described reference pattern. If the combination does not match, the combination of the H bit and the V bit for the packet is determined. The H bit and the V bit may be corrected so that the pattern (1, 0, 0, 0) indicating the empty packet is obtained.

  Even in this case, it is possible to suppress a packet that is not taken in by any node from continuing to circulate through the communication path NIO due to an error of the H bit or the V bit.

B6. Modification 6:
In the embodiment described above, the device system 10 is configured to include four devices 20A to 20D, but is not limited to four, and is configured to include two or three devices or five or more devices. It doesn't matter.

B7. Modification 7:
In the above-described embodiment, the device system 10 is integrated on one semiconductor substrate. However, each device may be mounted on a separate semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which shows schematic structure of the device system as one Example of this invention. Explanatory drawing which shows the data structure of the packet transmitted / received between each device. Explanatory drawing which shows the detailed structure of the communication path | route NIO shown in FIG. Explanatory drawing which shows the structure of the node with which a device is provided. Explanatory drawing explaining operation | movement of transmission / reception of the packet in node 22A. An explanatory view showing the composition of cleaner node 30. FIG. Explanatory drawing explaining the bit correction process for control in the cleaner node. Explanatory drawing which shows an example of the correction of H bit or V bit in the control bit correction process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Device system NIO ... Communication path | route NIO1-NIO4, NIO1a, NIO1b ... Partial path | route 20A-20D ... Device 22A-22D ... Node 24 ... Reception buffer 26 ... Transmission buffer 30 ... Cleaner node 221 ... 1st register 222 ... 2nd Register 223 ... transmission / reception control unit 301 ... first register 302 ... second register 303 ... transmission / reception control unit SCK ... system clock

Claims (7)

A device system comprising a plurality of devices connected by a loop communication path,
Among the plurality of devices, at least two or more devices are configured by a processor,
The communication path is formed in a loop shape by sequentially connecting a first node provided in each device and at least one second node, and circulates a packet composed of a plurality of packet elements in one direction. Is possible and
Each node sequentially inputs the packet in units of packet elements from the upstream node via the communication path in substantially synchronization with the other nodes, and the packet is transmitted to the downstream node via the communication path. Sequentially sent in element units,
When the second node sends the packet to the downstream node in units of the packet element, a flag indicating that the packet element to be sent is a header part, or the packet element to be sent is a payload part. A device system characterized in that any one of the flags indicating that is added to a packet element to be transmitted as a first flag according to the order of transmission. The device system according to claim 1,
In addition to the first flag, each packet element has one of a flag indicating that the packet element is valid or a flag indicating that the packet element is invalid. 2 is added as a flag,
When the second node inputs the packet in units of packet elements from the upstream node via the communication path, the second node adds the second flag added to each packet element constituting the packet. Detecting each and determining whether the pattern indicated by the second flag is a predetermined reference pattern;
When it is determined that the second node is not the predetermined reference pattern, when the packet is sent to the downstream node in units of the packet element, the second node is added to the packet element constituting the packet. Changing the second flag so that the pattern indicated by the second flag is a specific pattern of the predetermined reference pattern;
Device system. The device system according to claim 2,
The specific pattern is a pattern indicating that the packet transmitted in units of packet elements to a downstream node is an empty packet.
Device system. The device system according to claim 3.
The first node adds, to each packet element constituting the packet, whether or not a packet input in units of packet elements from an upstream node via the communication path is an empty packet. A determination based on the pattern indicated by the second flag,
When it is determined that the first node is an empty packet, the packet element that is the header portion indicated by the first flag among the packet elements constituting the packet includes control information. A packet element that stores a header, stores data to be transmitted to the first node as a destination, in a packet element that is the payload portion indicated by the first flag, and stores the header And a packet composed of packet elements in which the data is stored can be sent in units of the packet elements to a downstream node via the communication path.
Device system. The device system according to any one of claims 1 to 4,
The packet consists of two packet elements,
Device system. The device system according to any one of claims 1 to 5,
The device system is integrated on one semiconductor substrate,
Device system. A device system comprising a plurality of devices connected by a loop communication path,
Among the plurality of devices, at least two or more devices are configured by a processor,
The communication path is formed in a loop shape by sequentially connecting a first node provided in each device and at least one second node, and circulates a packet composed of a plurality of packet elements in one direction. Is possible and
Each node sequentially inputs the packet in units of packet elements from the upstream node via the communication path in substantially synchronization with the other nodes, and the packet is transmitted to the downstream node via the communication path. Sequentially sent in element units,
Each packet element has a flag attached,
When the second node inputs the packet in units of packet elements from the upstream node via the communication path, the second node detects each flag added to each packet element constituting the packet. And determining whether or not the pattern indicated by the flags is a predetermined reference pattern,
When it is determined that the second node is not the predetermined reference pattern, when the packet is sent to the downstream node in units of the packet element, the second node is added to the packet element constituting the packet. A device system, wherein the flag is changed so that a pattern indicated by the flag becomes a specific pattern of the predetermined reference pattern.

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