JP2007139995A - Display device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board which is suitably applied to a device. <P>SOLUTION: The circuit board has a wiring layer formed by coating an insulating substrate with ink of superconducting ultrafine particles, and the wiring layer having been sintered includes 0.1 to 10 vol.% of vacancy. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device in which a thin film transistor or the like is formed on an insulating substrate by drawing an ink paste using printing, an inkjet method, or the like, and a manufacturing method thereof.

  For example, in the manufacture of a liquid crystal display, an organic EL display, etc., when a circuit including a thin film transistor is formed on a substrate, it is normal to sequentially form a wiring, an insulating layer, and a semiconductor layer on the substrate surface. This is because the structure of the thin film transistor becomes dominant.

  The pattern of each layer at that time is a selective etching method using a photolithography technique. The formation of a material layer constituting each layer, the formation of a photoresist film, the selective exposure, and the development remaining photoresist are used as a mask. A series of steps of etching the material layer and stripping the photoresist film are performed.

  In these steps, a sputtering / CVD apparatus, an exposure / coating / developing apparatus, a dry etching / wet etching apparatus, a peeling / oxygen ashing apparatus, and the like are required.

  By arranging these devices for the number of steps, circuit boards such as liquid crystal displays and organic EL displays can be manufactured.

  Furthermore, when manufacturing a panel with a large area, for efficient production, it is manufactured using a large area substrate capable of multi-cavity.

  These techniques are disclosed, for example, in Patent Documents 1 and 2 below.

JP-A-11-207959 JP 2002-324966 A

  However, in the above-described series of processes, since a film is first formed on the entire surface of the substrate and then etched using the patterned resist film as a mask, most of the material is discarded, which is not an efficient usage method. Also, from an environmental point of view, it is indispensable to treat waste gas and waste liquid containing an etched wiring film component, which is not an environmentally friendly manufacturing method.

  In addition, the above-described apparatus capable of handling a substrate having a large area is expensive in price, and requires a large amount of apparatus cost when the number of units for a mass production line is prepared.

  Here, as a method of eliminating such inconvenience, there is a method of drawing with an inkjet, for example, as a method of forming a patterned conductive layer.

  However, as an example of the ink metal fine particle ink, it can be seen in, for example, Japanese Patent Application Laid-Open No. 2002-324966, but there is a problem that the material structure is not considered in consideration of the device structure. In particular, regarding Ag of a low-resistance material, generation of hillocks is concerned due to surface diffusion during heating, and there is no description on how to prevent this.

  Further, as can be seen in, for example, Japanese Patent Application Laid-Open No. 11-207959, the details of the device have not been discussed even when the conductor wiring is formed on the surface using the difference in wettability.

Furthermore, when applied to thin film transistor wiring, no consideration has been given to contact with semiconductor layers and electrodes.
The present invention has been made based on such circumstances, and an object thereof is to provide a display device suitable for application to a device and a method for manufacturing the same.

The above problem is solved by the following means.
(1)
The display device according to the present invention is, for example, a display device in which a conductive fine particle ink is applied on an insulating substrate to form a wiring, and the sintered wiring layer has an empty space of 0.1 vol% to 10 vol%. It is characterized by including a hole.
(2)
The display device according to the present invention is, for example, a display device in which a conductive fine particle ink is applied on an insulating substrate to form a wiring, and has a specific gravity with respect to Ag or Cu which is a conductive fine particle having a low specific resistance. It is characterized in that fine particles of heavy elements are added.
(3)
The display device according to the present invention is characterized in that, for example, fine particles of an element having a high specific gravity are simultaneously a silicide-forming element.
(4)
In the display device according to the present invention, for example, the added fine particles are at least one of rhodium, platinum, lead, palladium, tantalum, tungsten, gold, iridium, and neodymium.
(5)
In the display device according to the present invention, for example, a wiring formed by applying conductive fine particle ink and a Si layer formed thereunder are connected via a contact hole, and rhodium, platinum, lead are connected at the interface. At least one of palladium, tantalum, tungsten, gold, iridium, and neodymium forms silicide.
(6)
In the method for manufacturing a display device according to the present invention, for example, at least one high specific gravity additive element selected from rhodium, platinum, lead, palladium, tantalum, tungsten, gold, iridium, and neodymium added in Ag or Cu fine particles is used for wiring. It is segregated in the lower layer side of the wiring fine particle ink layer within the coating holding time, and is baked in this state to form a contact silicide layer at the interface with the Si layer.

  When the wiring is formed by sintering the fine particles in this manner, vacancies remain in the film depending on the firing conditions. From the viewpoint of specific resistance, it is desirable that there are no holes. However, from the viewpoint of heat resistance, on the contrary, it is desirable to have an appropriate proportion of holes.

  This is because there is a hillock suppression effect due to the stress relaxation effect of the holes. In other words, the remaining vacancies absorb the expansion of hillocks that are generated by extruding weakly oriented crystal grains due to the compressive stress that is generated during thermal expansion during heating. This is because it can be prevented. Therefore, the amount of pores is good enough to offset the amount of thermal expansion at the heating temperature of the material, and the volume ratio is in the range of 0.1% to 10%. Excess vacancies may cause voids due to their growth and disconnection due to this, so it is desirable not to introduce more vacancies than necessary. In view of the specific resistance of the material, it is desirable to introduce indispensable pores.

  The required void fraction depends on the material. In Ag and Al, which are materials with relatively poor heat resistance, it is preferable to introduce relatively large holes so that the effect of reducing the compressive stress is large so that generation of hillocks during heating can be further suppressed. On the other hand, in the case of a material having high heat resistance such as Cu, hillocks are not easily generated. Therefore, the amount of compressive stress relaxation during heating may be small, and therefore the amount of introduction of holes may be small.

  In addition, it is effective to add fine particles of elements having a high specific gravity to Ag or Cu, which are conductive particles having a low specific resistance, in the case where any circuit using a thin film transistor is configured. After drawing a conductive ink paste mixed with fine particles of Ag or Cu in a solvent using fine particles of Ag or Cu on the substrate using the inkjet method, the high specific gravity is added due to the difference in specific gravity in the state of being dissolved in the solvent. The element moves below the paste layer and segregates near the base.

  When the underlying layer is a silicon film, if this additive element is a silicide forming element, a silicide layer is preferentially formed at the interface with silicon during firing. This layer acts as a barrier layer that prevents Ag or Cu from diffusing into the silicon.

  Rhodium, platinum, lead, palladium, tantalum, tungsten, gold, iridium, and neodymium are effective as examples of elements that have higher specific gravity than Ag or Cu and form silicide. One of these may be used, but it goes without saying that a combination of two or more elements is also effective.

  Since it takes time for the above additive elements to segregate or settle down to the vicinity of the bottom surface of the lower layer of the wiring after drawing the wiring, it is not immediately fired after drawing the wiring by inkjet, but the holding time for several hours thereafter In the meantime, it is important to adjust the ink state so that segregation and sedimentation occur.

  Contact with silicon is made at the contact hole, but in other regions, it is formed on the insulating film. In that case, no silicide is formed at the base interface, but the reactivity is higher than that of Ag or Cu, so that the base adhesiveness of the wiring pattern can be improved.

  With this method, it is possible to form a wiring structure having good contact characteristics with silicon by one ink-jet drawing without separately forming a barrier layer in contact with the silicon layer.

  The present invention can be applied to any structure as long as it is a thin film transistor in which a Si layer is disposed under an inkjet wiring. The present invention can be similarly applied to a polysilicon TFT having a coplanar structure or an amorphous silicon TFT having a reverse stagger structure or a normal stagger structure.

Hereinafter, embodiments of a display device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.
FIG. 1 shows a cross-sectional view of a contact hole of the display device. The contact hole has a function for electrically connecting the first conductive layer in the lower layer and the second conductive layer in the upper layer through the insulating film through the contact hole, and is in the pixel region. Or formed outside the display portion formed by the aggregate of pixels and formed in a circuit for driving the pixels.

  In FIG. 1, a semiconductor layer 2 is used as the first conductive layer in an enlarged view of a main part commonly showing these cases. That is, there is a substrate 1 made of an insulator, and a semiconductor layer 2 is selectively formed on the surface of the substrate 1. An insulating film 3 is formed on the surface of the substrate 1 so as to cover the semiconductor layer 2. A contact hole 4 is formed in the insulating film 3 so as to expose a part of the semiconductor layer 2. Yes. A conductive layer 5 is formed on the upper surface of the insulating film 3 so as to cover the contact hole 4, and the conductive layer 5 is electrically connected to the semiconductor layer 2 at the contact hole 4.

  The semiconductor layer 2 is formed by patterning a silicon (Si) film formed by, for example, a CVD method by photoetching, and the insulating film 3 is formed by, for example, the CVD method and then the contact hole 4 is formed by photoetching. It is formed. The conductive layer 5 functions as a wiring layer formed on the insulating film 3, and is formed by applying and drawing a paste made of ultrafine metal particles on the insulating film 3 using an ink jet.

  In this case, most of the conductive layer 5 is formed on the insulating layer 3, but is embedded in the contact hole 4 and in contact with the surface of the semiconductor layer 2 exposed from the contact hole 4. It is formed.

  A metal paste having a low specific resistance is selected as the material of the conductive layer 5. For example, Ag, Cu, Al, Au, etc. In this case, Ag and Cu are particularly easy to form as ultrafine particles, and selecting them is suitable for increasing the effect of the present invention.

  After the metal paste containing the ultrafine particles described above is drawn in a pattern as a wiring layer, the solvent contained therein is removed by heating at a low temperature, and further heated and fired at 300 ° C. to 400 ° C. The conductive layer 5 is formed by promoting the sintering of the fine particles.

  It is important that the holes 6 remain in the conductive layer 5 after sintering in this case. For that purpose, it is important that the ultrafine particles have a particle diameter of 10 nm to 50 nm and are optimally distributed in the metal paste, and that the firing temperature is not increased more than necessary. As the firing temperature, for example, 300 ° C. is sufficient in the case of a metal paste using Ag ultrafine particles, and 400 ° C. is the optimum firing temperature in the case of a metal paste using Cu ultrafine particles.

  In this way, by controlling the particle size of the ultrafine particles and the firing temperature, the volume fraction of the remaining pores 6 can be between 0.1% and 10%, and further from 0.5% It is also possible to limit the range to 2%.

  In addition, since Ag and Cu differ in the degree of their heat resistance, it is preferable that the optimum pore volume fraction is set to be different. In the case of Ag having lower heat resistance, it is better to increase the void volume fraction so as to cause more structural relaxation, and 1.0% to 10%, preferably 2.0% to 5.0%. Suitable. On the other hand, in the case of Cu having high heat resistance, the optimum pore volume fraction is small, 0.2% to 5.0% is good, and 0.5% to 2% is suitable.

  Thus, the remaining holes 6 in the conductive layer 5 have an effect of sufficiently relaxing the film stress generated during the formation of the conductive layer 5 and the subsequent heating process. FIG. 2 is a characteristic diagram showing a case of a sputtered thin film material having hillock resistance in (c) when there are no holes in (a), when holes remain in (b), and on the horizontal axis respectively. The temperature T (temperature) and the vertical axis indicate the tensile force TS (tensile stress) and the compressive force CS (compressive stress).

  That is, as shown in FIG. 2A, when there is no hole 6 in the conductive layer 5, the compressive film stress increases due to the expansion SW of the volume expansion of the material itself accompanying heating, and this is relaxed. When the grains protrude as hillocks, a phenomenon of relaxing the compressive stress occurs (process PQ in the figure). In the figure, symbol RT indicates the residual tensile stress.

  On the other hand, when the vacancies 6 remain in the conductive layer 5 as shown in FIG. 2B, when a certain compressive stress CS is reached by the expansion SW, the crystal grains are deformed so that the vacancies 6 are crushed. Stress will be relieved. Therefore, even if the temperature rises, the compressive stress does not increase and hillocks are not generated. In addition, when the volume is reduced during cooling, deformation occurs so that holes are generated again, so there is no change in stress (process PQ in the figure). In the elastic deformation region, the tensile stress RT changes in the tensile direction as opposed to during heating. Accordingly, it is possible to cope with the generated film stress by utilizing the deformation via the holes at the time of heating and cooling.

  Further, FIG. 2 (c) shows a case where hillocks are dealt with by reducing the volume by forming an intermetallic compound with these in Ag or Cu ultrafine particles. When Nd is added as an additional element, it precipitates as an AgNd compound at around 300 ° C., and hillocks are prevented by the volume reduction associated therewith. This is to reduce the compressive stress by reducing the volume accompanying the precipitation of the compound, as in the case of the conductive layer formed by the sputtering method. Even in this case, hillock countermeasures are sufficiently possible, but vacancies at the time of forming the compound may lead to micro disconnection due to tensile stress RT during cooling.

  From this, when the holes 6 are initially present in advance, the holes 6 are only re-formed during heat shrinkage so that the holes 6 are not propagated and disconnected. It turns out that you can.

  FIG. 3 shows an example in which rhodium, platinum, lead, palladium, tantalum, tungsten, gold, iridium, or neodymium is added as an example of an element that has a higher specific gravity than Ag or Cu as an ultrafine particle and forms silicide. Show. As shown in FIG. 3A, immediately after the ink jet drawing, the additive particles 7 having a high specific gravity are uniformly dispersed in the conductive layer 5.

  The density of Ag and Cu is 10.49 and 8.93 respectively, whereas rhodium is 12.44, platinum is 21.45, lead is 11.34, palladium is 12.16, tantalum is 16.6, tungsten is 19.3, gold is 19.26 and iridium is 22.4. Since the specific gravity of the additive fine particles 7 is heavier than that of the ultrafine particles of Ag or Cu as the parent phase, the additive element 7 is caused by gravity as shown in FIG. The conductive layer 5 settles downward and segregates. In this case, it is important to control the state of the colloid so that it is difficult to uniformly disperse.

  After that, by firing, the conductive particles 5 are formed, and at the same time, the added fine particles segregated in the lower layer are also sintered. In this case, if the silicide formation tendency is stronger than that of the additive elements Ag and Cu as the parent phase, silicide of each additive element is formed at the interface with the lower Si layer as shown in FIG. A barrier layer 8 can be formed between the phase Ag or Cu wiring. When the density difference is small, segregation to the lower layer is small. However, if the silicide formation tendency of the element is strong, silicide is formed at the Si interface only by the additive element existing at the interface, and the barrier layer 8 is formed. It becomes possible. At the time of sintering the ultrafine particles, Ag or Cu particles are combined to form a monolithic structure. At this time, instead of setting the sintering density to 100%, 0.5% to 1% of voids 6 are left. By being sintered, it is possible to have the stress relaxation effect due to the holes described in FIG.

  FIG. 4 is a diagram showing an embodiment in which the above-described invention is applied to formation of a thin film transistor TFT of a display device. The thin film transistor TFT uses amorphous silicon as its semiconductor layer, and is called a so-called bottom gate type.

  Note that the thin film transistor TFT in the display device is provided in each pixel arranged in a matrix, for example, and a pixel group composed of pixels arranged in one direction is selected by turning on the thin film transistor TFT, and the timing of the selection is selected. Accordingly, it is used as a switching element for supplying a video signal to each pixel of the pixel group.

  As shown in FIG. 4, the gate wiring 18 is first patterned on the glass substrate 11 by applying, for example, ink in which 2 vol% of rhodium ultrafine particles are added to an Ag ultrafine particle paste by inkjet. A part of the gate wiring 18 functions as a gate electrode of the thin film transistor TFT.

  Since rhodium is about 20% denser than Ag, it settles in the lower layer. Thereafter, by firing at 300 ° C., a two-layer structure of a high-density layer made of rhodium and a wiring layer made of low-resistance Ag is sequentially formed. Although the gate wiring 18 has no portion in contact with the underlying material layer, the adhesion of the gate wiring 18 to the glass substrate 11 is improved by forming a layer having higher base adhesion than Ag on the glass substrate 11. It comes to have an effect. In this case, the gate wiring 18 is formed in a state where 1 vol% of vacancies are introduced into the film, and the effect becomes clear in the formation of the insulating film 19 described below.

  In other words, the amorphous silicon layer, the amorphous silicon layer, and the n + Si layer are successively formed by the CVD method, and the amorphous silicon layer and the n + silicon layer are patterned, and the silicon nitride remaining as it is is connected to the insulating film 19. Therefore, the insulating film 19 is formed so as to cover the gate wiring 18. The insulating film 19 has a function as a gate insulating film of the thin film transistor TFT. The insulating film 19 may be formed by applying and baking a Si—O—C insulating film as another material.

  In any case, the process temperature required for forming the insulating film 19 is about 300 ° C., and the heat resistance of Ag can be secured at this temperature. Further, as described above, since the gate wiring 18 is formed by introducing 1 vol% of vacancies in the film, the compressive stress at the time of heating the insulating film 19 can be alleviated by the collapse of the vacancies. The occurrence of hillocks can be prevented.

  The same effect can be obtained by introducing neodymium and forming a high-density AgNd intermetallic compound by heating and introducing the pores into the film by utilizing the volume reduction in addition to the firing conditions for introducing the pores. can get. Thereby, a void | hole can be introduce | transduced in a film | membrane more reliably. Since the density of neodymium is 7.0, which is not much different from Ag and Cu, it is possible to ensure a state in which the neodymium is uniformly dispersed throughout the film without being settled in the lower region of the film like other added fine particles. Therefore, by heating this, a minute intermetallic compound can be formed in the entire film, and vacancies can be introduced throughout the film.

  A semiconductor layer (Si layer) 12 is formed on the upper surface of the insulating film 19 across a gate wiring (gate electrode) 18. A source / drain electrode and a drain electrode are formed on both ends of the Si layer 12 across the gate wiring 18. By forming the wiring 21 connected to these, the thin film transistor TFT is formed.

  Here, the source / drain electrodes and the wiring 21 connected to them are formed by drawing Ag fine particle ink to which rhodium fine particles are added by an ink jet method. In this case, after the rhodium is settled by holding for a certain time, the rhodium silicide layer is formed at the Si layer interface and the vacancies are simultaneously introduced by firing at about 300 ° C.

  The effect in this case is the same as described with reference to FIGS. In the description of FIG. 1, the connection between the Si layer and the conductive layer is made through the through hole, whereas in this embodiment, the through hole does not exist, but this influences the effect of the present invention. is not.

  A passivation film 22 is formed by, for example, a CVD method so as to cover the source / drain electrodes and the wiring 21 connected thereto. The passivation film 22 has a function of protecting the thin film transistor TFT.

  If the display device to which this embodiment is applied is, for example, a liquid crystal display device, the passivation film 22 avoids direct contact of the thin film transistor TFT with the liquid crystal and avoids deterioration of the characteristics of the thin film transistor TFT. It is like that.

  Similarly, if it is a liquid crystal display device, a pixel electrode 23 made of, for example, ITO (Indium Tin Oxide) is formed on the surface of the passivation film 22, and a part of the pixel electrode 23 is a passivation layer below it. It is electrically connected to the source electrode of the thin film transistor TFT through a through hole formed in the film 22. Here, the pixel electrode 23 generates an electric field with another electrode provided with liquid crystal interposed therebetween, and performs optical modulation of the liquid crystal according to the strength of the electric field.

  Since the ITO used as the material of the pixel electrode 23 has a low contact resistance with the Ag film, the ITO can be directly contacted without forming a separate contact layer.

  According to this embodiment, a display device to which low resistance wiring is applied can be manufactured with a small number of steps by adopting a simple wiring formation process.

  FIG. 5 is a diagram showing another embodiment when the above-described invention is applied to formation of a thin film transistor TFT of a display device. The thin film transistor TFT uses polysilicon as its semiconductor layer, and is also referred to as a top gate type.

In FIG. 5, first, a SiN layer 34 and a SiO ₂ layer 35 are formed on a glass substrate 31. These layers are so-called underlayers, and have a function of blocking the entry of an ionic substance in the glass substrate 31 into a thin film transistor TFT described later.

A semiconductor layer 46 made of polysilicon is formed on a part of the upper surface of the SiO ₂ layer 35. The semiconductor layer 46 is formed over the entire substrate by, for example, plasma CVD, crystallized by laser annealing, and further patterned. This semiconductor layer 46 functions as that of the thin film transistor TFT.

A first insulating film 35A is formed so as to cover the semiconductor layer 46 as well. The first insulating film 35A is made of, for example, a SiO ₂ film formed by a CVD method, and functions as a gate insulating film of the thin film transistor TFT.

A gate electrode (gate signal line) 38 is formed on the upper surface of the first insulating film 35 </ b> A across the semiconductor layer 46. The gate electrode 38 is patterned by drawing ultrafine ink made of Cu using an ink jet. In this ink, rhodium is added as additive fine particles. The gate electrode 38 is formed by sintering the ultrafine particles of Cu by firing at 350 ° C. to 400 ° C. after the added fine particles settle in the lower layer with a density difference at a constant holding time. Although the gate electrode 38 is formed on the first insulating film 35A made of SiO ₂ , the adhesion of the base is low with Cu alone, whereas the ultrafine particles of precipitated rhodium form a high base adhesion layer and have high adhesion. Can be secured.

  A second insulating film 42 is formed over the gate electrode 38 by a CVD method or a coating type insulating film. A contact hole 44 is formed in the second insulating film 42 so that the drain and source regions of the semiconductor layer 46 are exposed. ing.

  A conductive layer 41 is formed on the upper surface of the second insulating film 42, and the conductive layer 41 forms a drain and source electrode and a wiring layer connected thereto at the contact hole 44.

  The conductive layer 41 is patterned by drawing an ultrafine particle paste made of Cu by an ink jet method. In this case, the rhodium ultrafine particles 39 added for a certain holding time are settled on the bottom surface of the contact hole, for example. Thereafter, firing is performed at 350 ° C. to 400 ° C., thereby forming voids in the conductive layer 41 while forming rhodium silicide at the Si interface. When Cu having high heat resistance is used as the material of the conductive layer 41, the volume fraction of holes may be small because it has higher hillock resistance than Ag.

  When the degree of sedimentation of the ultrafine particles 39 is small, platinum, tantalum, and tungsten having a larger density difference may be added. Since these all have a high tendency to form silicide, a barrier layer 45 made of a silicide layer can be formed at the Si interface, and the diffusion of Cu to the Si layer in the subsequent hydrogenation annealing step at 400 ° C. can be prevented. it can.

  A passivation film 40 is formed so as to cover the source / drain electrodes and the conductive layer 41 connected thereto. The passivation film 40 is composed of a sequential laminated body of, for example, a SiN film 40a formed by a CVD method and an organic material layer 40b formed by coating. This is because the dielectric constant of the entire passivation film 40 can be reduced and the surface can be flattened. The passivation film 40 has a function of protecting the thin film transistor TFT.

  Further, a pixel electrode 43 made of, for example, ITO (Indium Tin Oxide) is formed on the surface of the passivation film 40, and a part of the pixel electrode 43 passes through a contact hole 47 formed in the underlying passivation film 40 and is a thin film transistor. It is electrically connected to the source electrode of the TFT.

  In the display device having such a configuration, an inkjet process is applied to each of two wirings having different layers, and the eight manufacturing processes, which are the conventional manufacturing processes, can be reduced to four by half. Therefore, the display device can be manufactured with a greatly reduced number of steps.

It is sectional drawing explaining the circuit board of 1st Example of this invention. It is a schematic diagram explaining the thermal stress at the time of the process of forming 1st Example. It is sectional drawing of the circuit board explaining 1st Example. It is sectional drawing explaining the amorphous SiTFT board | substrate which applied the circuit board of 1st Example. It is sectional drawing explaining the low-temperature polysilicon TFT substrate which applied the circuit board of 2nd Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Semiconductor layer, 3 ... Insulating film, 4 ... Contact hole, 5 ... Conductive layer, 6 ... Hole, 7 ... Additive fine particle, 8 ... Barrier layer, 11, 31 ...... Glass substrate, 12 ... insulating film, 18 ... gate wiring, TFT ... thin film transistor, 19 ... insulating film, 21 ... wiring, 22 ... passivation film, 23 ... pixel electrode, 35 ... first Insulating film, 38 ... gate electrode, 40 ... passivation film, 41 ... conductive layer, 42 ... second insulating film, 44, 47 ... contact hole, 46 ... semiconductor layer.

Claims (6)

  A display device in which a conductive layer ink is applied on an insulating substrate to form a wiring layer, wherein the wiring layer after sintering contains 0.1 vol% to 10 vol% of holes. Display device.   A display device in which a conductive layer is coated on an insulating substrate to form a wiring layer, wherein the wiring layer has a higher specific gravity than Ag or Cu, which is a conductive particle having a low specific resistance. A display device to which elemental fine particles are added.   3. The display device according to claim 2, wherein the fine particles of the element having a high specific gravity are simultaneously a silicide-forming element.   The added fine particles are at least one of rhodium, platinum, lead, palladium, tantalum, tungsten, gold, iridium, and neodymium. Display device.   The wiring formed by applying the conductive fine particle ink and the Si layer formed thereunder are connected through a contact hole, and rhodium, platinum, lead, palladium, tantalum, tungsten, gold, A display device, wherein at least one of iridium and neodymium forms silicide. At least one high specific gravity additive element selected from rhodium, platinum, lead, palladium, tantalum, tungsten, gold, iridium, and neodymium added to the Ag or Cu fine particles is contained in the fine particle ink layer for wiring within the holding time of wiring application. A method for manufacturing a display device, characterized in that a contact silicide layer is formed at an interface with an Si layer by being segregated on a lower layer side and firing in that state.

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