JP2007134579A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a high performance semiconductor device having an emitter layer of a micronized width. <P>SOLUTION: An epitaxial layer 2 (active region 2a) surrounded by an element isolation region 3 is formed on a silicon substrate 1. An SiGe alloy layer 4 is formed on this active region 2a, and a silicon film 5 and an n-type diffusion layer (emitter layer) 6 are formed on the SiGe alloy layer 4. This n-type diffusion layer 6 is formed by diffusing an n-type impurity into part of the silicon film 5 having a convex cross-sectional shape. Moreover, a polycrystalline silicon film 7a and a silicide film 11a are formed on the n-type diffusion layer 6. Further, the n-type diffusion layer 6, the polycrystalline silicon film 7a, and the silicide film 11a are surrounded by a sidewall film 9 consisting of an insulating film. Furthermore, a p<SP>+</SP>diffusion layer 10 and a silicide film 11b are formed as an external base layer outside the region acting as an internal base layer in the SiGe alloy layer 4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  As portable electronic devices such as mobile phones, PDAs, DVCs, and DSCs are accelerating their functions, miniaturization and weight reduction are essential for their acceptance in the market. There is a need for a system LSI.

One example of a module that realizes such a highly integrated system LSI is a high-frequency bipolar transistor. An example of a structure that aims to improve the performance of a high-frequency bipolar transistor is a heterojunction bipolar transistor whose base layer is made of a silicon germanium (SiGe) alloy. .
The configuration of the SiGe-based heterojunction bipolar transistor in the bipolar transistor manufacturing technique described in Japanese Patent Laid-Open No. 4-179235 will be described with reference to FIGS. FIG. 13 is an element cross-sectional view of a SiGe-based heterojunction bipolar transistor, and FIG. 14 is a partially enlarged view centering on an emitter / base region.

In FIG. 13, an n ⁻ type layer (epitaxial layer) 102 serving as a collector layer is epitaxially grown on a p ⁻ type silicon substrate (not shown) via an n ⁺ type collector buried layer 101. The n ⁻ -type layer 102 is removed by etching leaving portions necessary as a collector layer and a collector take-out layer. A trench is formed in the element isolation region, and a polycrystalline silicon film 104 is embedded in the trench via an oxide film 103. The substrate surface on which collector formation and element isolation embedding have been performed is planarized by an oxide film (buried oxide film) 105, and a base and an emitter are further formed thereon by epitaxial growth. That is, a p-type SiGe layer (SiGe alloy layer) 106 serving as an internal base layer is epitaxially grown, and an n-type silicon layer 107 serving as an emitter layer and an n ⁺ -type silicon layer 108 serving as an emitter contact layer (emitter electrode) are formed thereon. Sequentially epitaxially grown. The n ⁺ -type silicon layer 108 and the n-type silicon layer 107 are removed by etching using the oxide film 109 as a mask, leaving only a region necessary as an emitter. Of the remaining p-type SiGe layer 106, the outside of the region serving as the internal base layer is etched to a predetermined depth using the oxide film (side wall film) 110 and the oxide film 109 as a mask, and p ^{+ serving as the} external base layer is formed here. The type SiGe layer 111 is formed by selective epitaxial growth.

As shown in FIG. 14, in the conventional SiGe-based heterojunction bipolar transistor structure, the n-type silicon layer 107 which is an emitter layer has a convex cross section (the contact surface 150 between the emitter layer 107 and the emitter electrode 108 is the side wall film 110). The shape is located above the lower surface 160). Since the emitter-base junction is formed on the bottom side of the convex portion, the dimension width of the junction portion (dimension width of the emitter layer) is W _e2 , and from the dimension width W _{e1 of} the n ⁺ -type silicon layer (emitter electrode) 108. Is also getting bigger.

When manufacturing a higher performance semiconductor device (SiGe-based heterojunction bipolar transistor) in the future, W _e1 is made thinner by further finely processing the n ⁺ -type silicon layer (emitter electrode) 108 in the conventional structure. As a result, it is necessary to reduce the dimension width W _e2 of the emitter layer. However, for this purpose, it is indispensable to introduce a highly accurate exposure apparatus, which leads to an increase in manufacturing cost.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for manufacturing a high-performance semiconductor device in which the dimension width of the emitter layer is reduced.

  In order to achieve the above object, a semiconductor device manufacturing method according to the present invention forms a conductive layer and a silicon film functioning as a base layer on a semiconductor substrate on which an active region surrounded by an element isolation region is formed. A second step of forming an emitter electrode containing a first impurity on the silicon film above the active region, a third step of etching the silicon film using the emitter electrode as a mask, After forming the insulating film so as to cover the entire surface of the semiconductor substrate, the insulating film is etched back to form a fourth step of forming a side wall film covering the side wall of the emitter electrode, and after forming the side wall film, A fifth impurity is introduced so as to reach the surface and an impurity region is formed in the conductive layer and the silicon film, and the first impurity contained in the emitter electrode is spread on the surface of the silicon film. And a sixth step of forming a first region containing the first impurity and a second region not containing the first impurity in the silicon film. In the third step, The contact surface between the first region and the emitter electrode is processed into a convex shape so as to be located above the lower surface of the side wall film. In the sixth step, at least a part of the second region of the silicon film is a conductive layer. And the sidewall film, and is formed so as to be in contact with the conductive layer and the sidewall film.

  By adopting such a manufacturing method, the dimension width of the first region as the emitter layer is less than that of the conventional structure in which the dimension width of the emitter layer is the same as the dimension width of the interface between the silicon film and the conductive layer. Since it is smaller than the dimension width of the conductive layer interface, the same current density can be obtained with a small current, and a high current amplification factor can be obtained. Therefore, a transistor with low power consumption can be formed. In addition, since at least a part of the second region of the silicon film is located between the conductive layer and the side wall film and is in contact with the conductive layer and the side wall film, the emitter-base junction area has a conventional structure ( The second region is narrower than the case where the second region also functions as an emitter layer. For this reason, a transistor in which the junction capacitance is reduced because the junction area is smaller than that of the conventional structure can be obtained. As a result, a high-performance semiconductor device can be provided.

  Further, according to this manufacturing method, at least a part of the second region of the silicon film is located between the conductive layer and the sidewall film, and the conductive layer and the sidewall film are not in direct contact with each other. Recombination of the base current at the interface with the film can be suppressed, and a semiconductor device having good base current characteristics can be manufactured.

  Further, in the diffusion of the first impurity in the sixth step, since the contact surface between the first region and the emitter electrode is located above the lower surface of the sidewall film, the sidewall film serves as an impurity diffusion barrier in the lateral direction. Diffusion is suppressed, and the dimensional width of the first region can be reduced with better controllability.

  In such a manufacturing method, the conductive layer is preferably a silicon germanium (SiGe) alloy layer, and it is desirable that the lower surface of the first region reaches the conductive layer. By doing so, since the band gap of the SiGe alloy layer is narrower than the band gap of the silicon film, the lower surface of the first region does not reach the conductive layer (the lower surface of the first region is the silicon film). Compared to the case of the above, the height of the barrier against electrons injected from the emitter layer to the base layer is reduced. As a result, the emitter injection efficiency is increased, and a higher current amplification factor can be obtained. A semiconductor device can be provided.

  In the present invention, the conductive layer includes a conductive layer obtained by introducing a P-type or N-type impurity into a semiconductor.

  Furthermore, in such a manufacturing method, a seventh step of forming a silicide film on the surface of the impurity region is further provided after the sixth step, and the damage layer on the surface of the impurity region is formed at least before the seventh step. An eighth step of removing is performed.

  When a silicide film is formed on the surface of an impurity region (silicon film) including a damaged layer, the resistance of the silicide film corresponding to the damaged layer is deteriorated and the shape of the silicide film is increased, resulting in an increase in wiring resistance. However, with the above manufacturing method, a silicide film is formed on the surface of the impurity region from which the damaged layer has been removed, so that the film quality of the silicide film on the impurity region is improved and the wiring resistance can be reduced. . In particular, when the eighth step of removing the damaged layer on the surface of the impurity region is performed only once just before the seventh step, not only the cost is reduced by reducing the number of steps but also the damaged layer. Since the film loss of the impurity region due to the removal of the impurity region can be minimized, the silicon film constituting the impurity region can be thinned, and the manufacturing cost can be further reduced. As a result, a high-performance semiconductor device can be provided at low cost.

  According to the method for manufacturing a semiconductor device of the present invention, a high-performance semiconductor device in which the dimension width of the emitter layer is miniaturized is provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.
(First embodiment)
1st Embodiment of this invention is described based on FIG. 1 and FIG. FIG. 1 is an element cross-sectional view of a SiGe-based heterojunction bipolar transistor according to the present invention, and FIG. 2 is a partially enlarged view centering on an emitter / base region.

In FIG. 1, an epitaxial layer 2 used as a collector layer and an element isolation region 3 which is STI (Shallow Trench Isolation) are formed on a part of the epitaxial layer 2 on a silicon substrate 1. A part of the epitaxial layer 2 surrounded by the element isolation region 3 becomes an active region 2a. Further, a SiGe alloy layer 4 used as a base region is formed on the active region 2a, and a silicon film 5 and an n-type diffusion layer 6 used as an emitter layer are formed on the SiGe alloy layer 4. The n-type diffusion layer 6 is formed by diffusing an n-type impurity in a silicon film 5 having a convex cross section, and the silicon film 5 before diffusion is processed into a convex shape. On the n-type diffusion layer 6, a polycrystalline silicon film 7a and a silicide film 11a are formed. Further, the n-type diffusion layer 6, the polycrystalline silicon film 7a, and the silicide film 11a are surrounded by a sidewall film 9 (commonly referred to as a sidewall) made of an insulating film. Here, the contact surface 50 between the n-type diffusion layer 6 and the polycrystalline silicon film 7 a is located above the lower surface 60 of the sidewall film 9. The silicon film 5 is located between the sidewall film 9 made of an insulating film and the SiGe alloy layer 4 and is in contact with the sidewall film 9 and the SiGe alloy layer 4. A p ⁺ diffusion layer 10 connected to the base region is formed around the periphery, and a silicide film 11b used as a low resistance layer of the external base layer is formed on the surface of the p ⁺ diffusion layer 10. The SiGe alloy layer 4 is the “conductive layer” of the present invention, the silicon film 5 is the “second region” of the present invention, the n-type diffusion layer 6 is the “first region” of the present invention, and the polycrystalline silicon film 7a. The “emitter electrode” of the present invention and the p ⁺ diffusion layer 10 are examples of the “impurity region” of the present invention.

  3 to 11 are cross-sectional views for explaining a semiconductor device manufacturing process according to the first embodiment of the present invention.

(Step 1: See FIG. 3) An element isolation region 3 such as STI is formed on the p-type silicon substrate 1. Next, in order to produce the active region 2a (collector layer 2), n-type impurities are ion-implanted and activated. For example, phosphorus (P) is implanted at an acceleration energy of about 500 to 4000 keV to a concentration of about 3 × 10 ¹³ cm ⁻² to 3 × 10 ¹⁵ cm ⁻² .

(Step 2: see FIG. 4) Silicon germanium (SiGe) alloy layer 4 doped with about 1 × 10 ¹⁹ cm ^{−3 of} boron (B) by low pressure CVD (Chemical Vapor Deposition) method, and does not include germanium (Ge) The silicon film 5 is epitaxially grown. The film thicknesses of the SiGe alloy layer 4e and the silicon film 5e are about 10 nm to 100 nm, respectively.

  The Ge concentration in the SiGe alloy layer 4e may be constant in the layer. However, if the Ge profile is a gradient type profile in which the Ge concentration gradually increases from the side in contact with the silicon film 5e toward the collector layer 2, the base is reduced. The traveling time of the traveling electrons can be shortened, and a transistor operating at high speed can be formed. At this time, the Ge concentration is preferably about 0% on the side in contact with the silicon film 5e, and preferably about 15% to 20% on the side in contact with the collector layer 2e.

  The silicon film 5e may be doped with boron (B) in the same manner as the SiGe alloy layer 4e, or may not be doped.

  Further, before the formation of the SiGe alloy layer 4e, a silicon film not containing boron (B) or a SiGe alloy layer not containing boron (B) may be epitaxially grown by a low pressure CVD method.

(Step 3: refer to FIG. 5) Next, a resist pattern is provided by lithography, and unnecessary portions of the silicon film 5e and the SiGe alloy layer 4e are removed by dry etching. Thus, the SiGe alloy layer 4 and the silicon film 5 used as the base region processed into a desired pattern are formed on the active region 2a. As dry etching conditions, for example, the pressure is 15 mT, the gas flow rate O ₂ / HBr = 2/180 sccm, and the RF power Upper / Lower = 250/12 W.

(Step 4: refer to FIG. 6) A polycrystalline silicon film 7e doped with an n-type impurity of about 1 × 10 ²⁰ cm ⁻³ or more is formed by a low pressure CVD method, and a silicon nitride film 8e is further formed. For example, arsenic (As) or phosphorus (P) is used as the n-type impurity. The thickness of the polycrystalline silicon film 7e is about 100 nm to 300 nm, and the thickness of the silicon nitride film 8e is about 50 nm to 200 nm. The n-type impurity is an example of the “first impurity” in the present invention.
(Step 5: see FIG. 7) A resist pattern is provided by a lithography method, and the silicon nitride film 8e, the polycrystalline silicon film 7e, and the silicon film 5 are etched in this order by dry etching. At this time, the dry etching is not performed until the silicon film 5 is completely removed, and is finished in a state where a part remains on the entire surface of the SiGe alloy layer 4. As a result, the silicon film 5 is finished in a shape 70 having a convex cross section. Furthermore, etching damage enters the surface 80a of the silicon film 5, and a damaged layer is formed. At this time, the polycrystalline silicon film 7e is processed as a polycrystalline silicon film 7a to be an emitter electrode, and a sidewall film 7b made of a polycrystalline silicon film around the SiGe alloy layer 4 and the silicon film 5. The silicon nitride film 8e is processed as the silicon nitride film 8, and functions as a mask when the polycrystalline silicon film 7e is etched. As dry etching conditions, for example, the pressure is 15 mT, the gas flow rate O ₂ / HBr = 2/180 sccm, and the RF power Upper / Lower = 250/12 W.

(Step 6: see FIG. 8) A silicon oxide film, which is an insulating film, is formed using a CVD method, and then etched back using dry etching, whereby the silicon nitride film 8, the polycrystalline silicon film 7a, and A sidewall film 9 made of a silicon oxide film called a sidewall is formed around the convex portion of the silicon film 5. By this dry etching, etching damage is further applied to the surface 80b of the silicon film 5, and a damaged layer is formed. The silicon oxide film is formed by, for example, heat treatment of a mixed gas of tetraethoxysilane (TEOS) / oxygen (O ₂ ) at about 720 ° C., and the film thickness is about 100 nm to 400 nm. The dry etching conditions are, for example, pressure 250 mT, gas flow rate: CHF ₃ / CF ₄ / Ar = 20/20/400 sccm, RF power 395 W).

(Step 7: see FIG. 9) After ion implantation of boron (B) using an ion implantation method, activation by heat treatment is performed to form a p ⁺ diffusion layer 10 that functions as an external base layer. As the ion implantation conditions, for example, BF ₂ is implanted at an acceleration energy of 1 keV to 40 keV and an implantation amount of 1 × 10 ¹⁴ cm ⁻² to 5 × 10 ¹⁵ cm ⁻² . Under this implantation condition, since ions do not pass through the silicon nitride film 8 having a thickness of about 50 nm existing on the polycrystalline silicon film 7a, boron is not implanted into the polycrystalline silicon film 7a. Boron is an example of the “second impurity” in the present invention.

  (Step 8: see FIG. 10) Next, heat treatment is performed to diffuse the n-type impurities of the polycrystalline silicon film 7a into the silicon film 5, thereby forming the n-type diffusion layer 6. As a result, an emitter-base junction is formed in the silicon film 5. The heat treatment is performed at about 1050 ° C. for about 5 seconds to 30 seconds using an RTA apparatus.

  Here, the emitter layer (n-type diffusion layer 6) formed in the silicon film 5 is formed by diffusion of n-type impurities from the polycrystalline silicon film 7a, but the diffusion is not only in the depth direction but also in the lateral direction. Therefore, the effective emitter width may be wider than the width of the polycrystalline silicon film 7a. However, in the first embodiment of the present invention, the contact surface 50 between the emitter layer (n-type diffusion layer 6) and the emitter electrode (polycrystalline silicon film 7a) is located above the lower surface 60 of the sidewall film 9. The side wall film 9 becomes a diffusion barrier, and the lateral diffusion of the n-type diffusion layer 6 is suppressed. For this reason, the dimension width of the emitter layer is miniaturized.

(Step 9: see FIG. 11) After the heat treatment, the silicon nitride film 8 on the base electrode (not shown), the emitter electrode, and the collector electrode (not shown) is removed using dilute hydrofluoric acid and phosphoric acid. . Further, in order to remove the etching damage (damage layer) applied to the surfaces 80a and 80b of the silicon film 5 in the steps 5 and 6 described above, the surface of the p ⁺ diffusion layer 10 (silicon film 5) is subjected to dry etching. Remove part of the side. Here, the dry etching conditions are, for example, a pressure of 1250 mT, a gas flow rate: O ₂ / CF ₄ = 200/100 sccm, and an RF power of 450 W. Unlike the dry etching conditions in Step 5 and Step 6, p ⁺ diffusion layer 10 (silicon film 5) is performed under a condition with little damage. The thickness of the p ⁺ diffusion layer 10 (silicon film 5) removed by this dry etching is, for example, about 10 nm.

  The etching damage (damage layer) on the surface 80a of the silicon film 5 is removed after the dry etching in step 5, or the etching damage (damage layer) on the surface 80b of the silicon film 5 is removed after the dry etching in step 6. However, when etching damage (damage layer) is removed for each process, the film thickness of the silicon film 5 is increased. For example, the silicon film 5 is removed by etching, and the SiGe alloy layer 4 is removed. When exposed, the formation of a silicide film is hindered at that portion, and it becomes difficult to provide a silicide film having a uniform film quality and film thickness. For this reason, the etching damage (damage layer) is removed at once from the last step in which the etching damage is applied to the silicon film 5 to immediately before the silicide film formation step (step 12) described later. It is more preferable.

(Step 12: see FIG. 1) Cobalt (Co) is formed on the surface of the polycrystalline silicon 7a and the surface of the p ⁺ diffusion layer 10, and heat treatment is performed to form cobalt silicide films (silicide films) 11a and 11b. The sheet resistance values of the silicide films 11a and 11b are about 7Ω / □, which is extremely low compared to the sheet resistance value of about 100Ω / □ of the conventional p ⁺ type SiGe layer (p ⁺ diffusion layer 10). . For this reason, the parasitic resistance which generate | occur | produces between an internal base layer and the base electrode (not shown) connected to an external base layer can be lowered | hung.

  In the silicidation process, the same effect can be obtained by forming titanium (Ti) instead of cobalt to form a titanium silicide film.

  Next, although not particularly shown, an interlayer insulating film such as a plasma TEOS film is deposited on the surface of the semiconductor substrate, and contact openings of the collector electrode part, the base electrode part, and the emitter electrode part of the NPN transistor are made and made of titanium or the like. A bipolar transistor having an NPN transistor can be manufactured by forming a barrier metal layer and a conductive layer made of aluminum or an aluminum alloy.

As shown in FIG. 14 above, in the emitter layer having the conventional structure, the dimensional width of the emitter-base junction portion was _We2 . On the other hand, in the first embodiment of the present invention, as shown in FIG. 2, the first region and the second region exist inside the silicon film having the same processing size, and this first region is further used as the emitter. Used as a layer. Since the emitter-base junction is formed at the bottom portion of the emitter layer, the dimension width of the junction is W _e3 , which is smaller than the dimension width of the interface between the silicon film and the SiGe alloy layer (dimension width W _e2 in the conventional structure). Become. Further, by controlling the diffusion of the n-type impurity into the silicon film 5, the dimension width of the junction portion of the emitter layer can be made substantially equal to _We1 . As a result, the dimension width of the emitter layer can be reduced without introducing a high-precision exposure apparatus. When the dimensional width of the emitter layer is reduced, that is, when the dimensional width is W _e3 or W _e1 , the same current density can be obtained with a smaller current than in the case of the dimensional width W _{e2 at} the interface between the silicon film and the SiGe alloy layer. Therefore, a transistor with low power consumption can be formed, and as a result, a high-performance semiconductor device can be obtained.

  In the first embodiment of the present invention, at least a part of the silicon film 5 is located between the SiGe alloy layer 4 and the side wall film 9 and is in contact with the SiGe alloy layer 4 and the side wall film 9. -The base junction area is smaller than that of the conventional structure (when the silicon film 5 also functions as an emitter layer). Therefore, it is possible to provide a transistor (semiconductor device) in which the junction capacitance is reduced because the junction dimension area is smaller than that of the conventional structure.

Further, when a silicide film is formed on the surface of the p ⁺ diffusion layer 10 including etching damage (damage layer), the silicide film quality deterioration corresponding to the etching damage (damage layer) and the silicide film shape variation are caused. However, according to the present manufacturing method, a silicide film is formed on the surface of the p ⁺ diffusion layer 10 (silicon film 5) from which etching damage (damage layer) has been removed. The film quality is improved, and the wiring resistance can be reduced. In particular, since it is performed only once just before the step 12 for removing the etching damage (damage layer) on the surface of the p ⁺ diffusion layer 10 (silicon film 5), the cost can be reduced only by reducing the number of steps. In addition, since the film loss of the p ⁺ diffusion layer 10 (silicon film 5) associated with the removal of the etching damage (damage layer) can be minimized, the silicon film 5 can be made thinner and the manufacturing cost can be further reduced. can do.

  Table 1 shows the measurement results of the sheet resistance of the silicide film produced under each condition. In the table, (a) when the silicide film is formed after removing the damage on the surface of the silicon film (condition 1), (b) the silicide film is formed without removing the damage on the surface of the silicon film. A case (condition 2) and a case (c) where a silicide film is formed without damaging the silicon film (condition 3) are shown. As can be seen from Table 1, when the surface of the silicon film is damaged, the sheet resistance value of the silicide film formed thereafter is greatly increased. On the other hand, when the treatment for removing the damage is performed, it can be seen that the sheet resistance value is recovered to the same extent as before the damage is applied to the silicon film.

（第２実施形態）
図１２は、本発明の第２実施形態によるＳｉＧｅベースへテロ接合バイポーラトランジスタの素子断面図である。第１実施形態と異なる箇所は、ｎ型拡散層６の下面がＳｉＧｅ合金層の中に設けられていることである。なお、シリコン膜５ａは本発明の「第２の領域」およびｎ型拡散層６ａは本発明の「第１の領域」の一例である。

(Second Embodiment)
FIG. 12 is a device cross-sectional view of a SiGe-based heterojunction bipolar transistor according to a second embodiment of the present invention. The difference from the first embodiment is that the lower surface of the n-type diffusion layer 6 is provided in the SiGe alloy layer. The silicon film 5a is an example of the “second region” in the present invention, and the n-type diffusion layer 6a is an example of the “first region” in the present invention.

  Since the lower surface of the n-type diffusion layer 6a has reached the SiGe alloy layer 4, the collector layer 2 is exposed from the lower surface of the n-type diffusion layer 6a functioning as an emitter layer, compared to the case where the lower surface does not reach the SiGe alloy layer 4. The distance to the collector layer can be shortened, and a transistor operating at high speed can be formed. Therefore, a higher performance semiconductor device can be provided.

  In order to manufacture the semiconductor device according to the second embodiment of the present invention, in Step 2 of the first embodiment, the silicon film 5a is formed to about 30 nm by the low pressure CVD method, and in Step 8, using the RTA apparatus, about 1050 ° C. The heat treatment is performed for about 5 seconds. By doing so, the n-type impurity in the polycrystalline silicon film 7a diffuses about 40 nm toward the collector layer 2 side, so that it passes through the silicon film 5a having a thickness of about 30 nm and reaches the SiGe alloy layer 4. . As a result, the lower surface (emitter-base junction) of the n-type diffusion layer 6a does not reach the SiGe alloy layer 4 (when the lower surface of the n-type diffusion layer 6a is in the silicon film 5a). The emitter injection efficiency is high, and a higher current amplification factor can be obtained. This is because when the lower surface of the n-type diffusion layer 6a is in the SiGe alloy layer 4, the lower surface of the n-type diffusion layer 6a is less than the silicon film 5a because the band gap of the SiGe alloy layer is narrower than the band gap of the silicon film. This is because the height of the barrier against electrons injected from the emitter layer to the base layer is smaller than that in the case of the above. As a result, the height of the barrier against electrons injected from the emitter layer into the base layer can be made smaller than the height of the barrier against holes injected from the base layer into the emitter layer, thereby increasing the emitter injection efficiency. And a higher current gain can be realized. Therefore, a higher performance semiconductor device can be provided.

  Although the present invention has been described in detail with reference to the embodiments, the present invention is not limited to this, and can be applied to various bipolar transistors without departing from the spirit of the present invention.

It is sectional drawing for demonstrating the semiconductor device which concerns on 1st Embodiment of this invention. It is the elements on larger scale for explaining the semiconductor device concerning a 1st embodiment of the present invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the semiconductor device which concerns on 2nd Embodiment of this invention. It is sectional drawing for demonstrating the conventional SiGe base heterojunction bipolar transistor structure. It is the elements on larger scale for demonstrating the conventional SiGe base heterojunction bipolar transistor structure.

Explanation of symbols

1 p-type silicon substrate 2 collector layer (epitaxial layer)
2a Active region 3 Element isolation region (STI)
4 Silicon germanium (SiGe) alloy layer 5 Silicon film 6 N-type diffusion layer (emitter layer)
7a Polycrystalline silicon film (emitter electrode)
9 Side wall film (side wall) made of silicon oxide film
10 p ⁺ diffusion layer 11a, 11b silicide film 50 interface between n-type diffusion layer and polycrystalline silicon film 60 lower surface of side wall film 70 convex portion of silicon film formed in convex shape

Claims (3)

A first step of forming a conductive layer and a silicon film functioning as a base layer on a semiconductor substrate on which an active region surrounded by an element isolation region is formed;
A second step of forming an emitter electrode containing a first impurity on the silicon film above the active region;
A third step of etching the silicon film using the emitter electrode as a mask;
Forming an insulating film so as to cover the entire surface of the semiconductor substrate, and then etching back the insulating film to form a sidewall film covering the sidewall of the emitter electrode;
A fifth step of introducing a second impurity so as to reach the surface of the active region after forming the sidewall film, and forming an impurity region in the conductive layer and the silicon film;
The first impurity contained in the emitter electrode is diffused on the surface of the silicon film, and a first region containing the first impurity and a second region not containing the first impurity are formed in the silicon film. A sixth step of:
With
In the third step, the silicon film is processed into a convex shape such that the contact surface between the first region and the emitter electrode is located above the lower surface of the sidewall film,
In the sixth step, at least a part of the second region of the silicon film is formed between the conductive layer and the sidewall film and in contact with the conductive layer and the sidewall film. A method of manufacturing a semiconductor device characterized by the above.   The method of manufacturing a semiconductor device according to claim 1, wherein the conductive layer is a silicon germanium (SiGe) alloy layer, and a lower surface of the first region reaches the conductive layer. After the sixth step, the method further comprises a seventh step of forming a silicide film on the surface of the impurity region,
The method of manufacturing a semiconductor device according to claim 1, wherein an eighth step of removing a damaged layer on the surface of the impurity region is performed at least before the seventh step.

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